Next: BFIN Directives, Up: BFIN-Dependent

#### 9.5.1 Syntax

`Special Characters`
  Assembler input is free format and may appear anywhere on the line. One instruction may extend across multiple lines or more than one instruction may appear on the same line. White space (space, tab, comments or newline) may appear anywhere between tokens. A token must not have embedded spaces. Tokens include numbers, register names, keywords, user identifiers, and also some multicharacter special symbols like "+=", "/*" or "||".
`Instruction Delimiting`
  A semicolon must terminate every instruction. Sometimes a complete instruction will consist of more than one operation. There are two cases where this occurs. The first is when two general operations are combined. Normally a comma separates the different parts, as in

                a0= r3.h * r2.l, a1 = r3.l * r2.h ;

  The second case occurs when a general instruction is combined with one or two memory references for joint issue. The latter portions are set off by a "||" token.

                a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];

`Register Names`
  The assembler treats register names and instruction keywords in a case insensitive manner. User identifiers are case sensitive. Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the assembler.

  Register names are reserved and may not be used as program identifiers.

  Some operations (such as "Move Register") require a register pair. Register pairs are always data registers and are denoted using a colon, eg., R3:2. The larger number must be written firsts. Note that the hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.

  Some instructions (such as –SP (Push Multiple)) require a group of adjacent registers. Adjacent registers are denoted in the syntax by the range enclosed in parentheses and separated by a colon, eg., (R7:3). Again, the larger number appears first.

  Portions of a particular register may be individually specified. This is written with a dot (".") following the register name and then a letter denoting the desired portion. For 32-bit registers, ".H" denotes the most significant ("High") portion. ".L" denotes the least-significant portion. The subdivisions of the 40-bit registers are described later.

`Accumulators`
  The set of 40-bit registers A1 and A0 that normally contain data that is being manipulated. Each accumulator can be accessed in four ways.
  `one 40-bit register`
    The register will be referred to as A1 or A0.
  `one 32-bit register`
    The registers are designated as A1.W or A0.W.
  `two 16-bit registers`
    The registers are designated as A1.H, A1.L, A0.H or A0.L.
  `one 8-bit register`
    The registers are designated as A1.X or A0.X for the bits that extend beyond bit 31.
`Data Registers`
  The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that normally contain data for manipulation. These are abbreviated as D-register or Dreg. Data registers can be accessed as 32-bit registers or as two independent 16-bit registers. The least significant 16 bits of each register is called the "low" half and is designated with ".L" following the register name. The most significant 16 bits are called the "high" half and is designated with ".H" following the name.

                   R7.L, r2.h, r4.L, R0.H

`Pointer Registers`
  The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that normally contain byte addresses of data structures. These are abbreviated as P-register or Preg.

                p2, p5, fp, sp

`Stack Pointer SP`
  The stack pointer contains the 32-bit address of the last occupied byte location in the stack. The stack grows by decrementing the stack pointer.
`Frame Pointer FP`
  The frame pointer contains the 32-bit address of the previous frame pointer in the stack. It is located at the top of a frame.
`Loop Top`
  LT0 and LT1. These registers contain the 32-bit address of the top of a zero overhead loop.
`Loop Count`
  LC0 and LC1. These registers contain the 32-bit counter of the zero overhead loop executions.
`Loop Bottom`
  LB0 and LB1. These registers contain the 32-bit address of the bottom of a zero overhead loop.
`Index Registers`
  The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte addresses of data structures. Abbreviated I-register or Ireg.
`Modify Registers`
  The set of 32-bit registers (M0, M1, M2, M3) that normally contain offset values that are added and subracted to one of the index registers. Abbreviated as Mreg.
`Length Registers`
  The set of 32-bit registers (L0, L1, L2, L3) that normally contain the length in bytes of the circular buffer. Abbreviated as Lreg. Clear the Lreg to disable circular addressing for the corresponding Ireg.
`Base Registers`
  The set of 32-bit registers (B0, B1, B2, B3) that normally contain the base address in bytes of the circular buffer. Abbreviated as Breg.
`Floating Point`
  The Blackfin family has no hardware floating point but the .float directive generates ieee floating point numbers for use with software floating point libraries.
`Blackfin Opcodes`
  For detailed information on the Blackfin machine instruction set, see the Blackfin(r) Processor Instruction Set Reference.