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<a name="PowerPC_002dOpts"></a>Next:&nbsp;<a rel="next" accesskey="n" href="PowerPC_002dPseudo.html#PowerPC_002dPseudo">PowerPC-Pseudo</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="PPC_002dDependent.html#PPC_002dDependent">PPC-Dependent</a>
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<h4 class="subsection">9.27.1 Options</h4>
<p><a name="index-options-for-PowerPC-1430"></a><a name="index-PowerPC-options-1431"></a><a name="index-architectures_002c-PowerPC-1432"></a><a name="index-PowerPC-architectures-1433"></a>The PowerPC chip family includes several successive levels, using the same
core instruction set, but including a few additional instructions at
each level. There are exceptions to this however. For details on what
instructions each variant supports, please see the chip's architecture
reference manual.
<p>The following table lists all available PowerPC options.
<dl>
<dt><code>-mpwrx | -mpwr2</code><dd>Generate code for POWER/2 (RIOS2).
<br><dt><code>-mpwr</code><dd>Generate code for POWER (RIOS1)
<br><dt><code>-m601</code><dd>Generate code for PowerPC 601.
<br><dt><code>-mppc, -mppc32, -m603, -m604</code><dd>Generate code for PowerPC 603/604.
<br><dt><code>-m403, -m405</code><dd>Generate code for PowerPC 403/405.
<br><dt><code>-m440</code><dd>Generate code for PowerPC 440. BookE and some 405 instructions.
<br><dt><code>-m7400, -m7410, -m7450, -m7455</code><dd>Generate code for PowerPC 7400/7410/7450/7455.
<br><dt><code>-m750cl</code><dd>Generate code for PowerPC 750CL.
<br><dt><code>-mppc64, -m620</code><dd>Generate code for PowerPC 620/625/630.
<br><dt><code>-me500, -me500x2</code><dd>Generate code for Motorola e500 core complex.
<br><dt><code>-mspe</code><dd>Generate code for Motorola SPE instructions.
<br><dt><code>-mppc64bridge</code><dd>Generate code for PowerPC 64, including bridge insns.
<br><dt><code>-mbooke64</code><dd>Generate code for 64-bit BookE.
<br><dt><code>-mbooke, mbooke32</code><dd>Generate code for 32-bit BookE.
<br><dt><code>-me300</code><dd>Generate code for PowerPC e300 family.
<br><dt><code>-maltivec</code><dd>Generate code for processors with AltiVec instructions.
<br><dt><code>-mvsx</code><dd>Generate code for processors with Vector-Scalar (VSX) instructions.
<br><dt><code>-mpower4</code><dd>Generate code for Power4 architecture.
<br><dt><code>-mpower5</code><dd>Generate code for Power5 architecture.
<br><dt><code>-mpower6</code><dd>Generate code for Power6 architecture.
<br><dt><code>-mpower7</code><dd>Generate code for Power7 architecture.
<br><dt><code>-mcell</code><dd>Generate code for Cell Broadband Engine architecture.
<br><dt><code>-mcom</code><dd>Generate code Power/PowerPC common instructions.
<br><dt><code>-many</code><dd>Generate code for any architecture (PWR/PWRX/PPC).
<br><dt><code>-mregnames</code><dd>Allow symbolic names for registers.
<br><dt><code>-mno-regnames</code><dd>Do not allow symbolic names for registers.
<br><dt><code>-mrelocatable</code><dd>Support for GCC's -mrelocatable option.
<br><dt><code>-mrelocatable-lib</code><dd>Support for GCC's -mrelocatable-lib option.
<br><dt><code>-memb</code><dd>Set PPC_EMB bit in ELF flags.
<br><dt><code>-mlittle, -mlittle-endian</code><dd>Generate code for a little endian machine.
<br><dt><code>-mbig, -mbig-endian</code><dd>Generate code for a big endian machine.
<br><dt><code>-msolaris</code><dd>Generate code for Solaris.
<br><dt><code>-mno-solaris</code><dd>Do not generate code for Solaris.
</dl>
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