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HTML
193 lines
12 KiB
HTML
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<html lang="en">
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<head>
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<title>ARM - Untitled</title>
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<meta http-equiv="Content-Type" content="text/html">
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<meta name="description" content="Untitled">
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<meta name="generator" content="makeinfo 4.7">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Machine-Dependent.html#Machine-Dependent" title="Machine Dependent">
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<link rel="prev" href="i960.html#i960" title="i960">
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<link rel="next" href="HPPA-ELF32.html#HPPA-ELF32" title="HPPA ELF32">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU linker LD
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(GNU Binutils)
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version 2.19.
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Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000,
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2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.1
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.-->
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<meta http-equiv="Content-Style-Type" content="text/css">
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<style type="text/css"><!--
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pre.smalldisplay { font-family:inherit; font-size:smaller }
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pre.smallformat { font-family:inherit; font-size:smaller }
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pre.smallexample { font-size:smaller }
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pre.smalllisp { font-size:smaller }
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span.sc { font-variant:small-caps }
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span.roman { font-family: serif; font-weight: normal; }
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--></style>
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</head>
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<body>
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<div class="node">
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<p>
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<a name="ARM"></a>Next: <a rel="next" accesskey="n" href="HPPA-ELF32.html#HPPA-ELF32">HPPA ELF32</a>,
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Previous: <a rel="previous" accesskey="p" href="i960.html#i960">i960</a>,
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Up: <a rel="up" accesskey="u" href="Machine-Dependent.html#Machine-Dependent">Machine Dependent</a>
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<hr><br>
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</div>
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<h3 class="section">4.4 <span class="command">ld</span> and the ARM family</h3>
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<p><a name="index-ARM-interworking-support-532"></a><a name="index-_002d_002dsupport_002dold_002dcode-533"></a>For the ARM, <span class="command">ld</span> will generate code stubs to allow functions calls
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between ARM and Thumb code. These stubs only work with code that has
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been compiled and assembled with the <span class="samp">-mthumb-interwork</span> command
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line option. If it is necessary to link with old ARM object files or
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libraries, which have not been compiled with the -mthumb-interwork
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option then the <span class="samp">--support-old-code</span> command line switch should be
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given to the linker. This will make it generate larger stub functions
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which will work with non-interworking aware ARM code. Note, however,
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the linker does not support generating stubs for function calls to
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non-interworking aware Thumb code.
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<p><a name="index-thumb-entry-point-534"></a><a name="index-entry-point_002c-thumb-535"></a><a name="index-_002d_002dthumb_002dentry_003d_0040var_007bentry_007d-536"></a>The <span class="samp">--thumb-entry</span> switch is a duplicate of the generic
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<span class="samp">--entry</span> switch, in that it sets the program's starting address.
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But it also sets the bottom bit of the address, so that it can be
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branched to using a BX instruction, and the program will start
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executing in Thumb mode straight away.
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<p><a name="index-BE8-537"></a><a name="index-_002d_002dbe8-538"></a>The <span class="samp">--be8</span> switch instructs <span class="command">ld</span> to generate BE8 format
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executables. This option is only valid when linking big-endian objects.
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The resulting image will contain big-endian data and little-endian code.
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<p><a name="index-TARGET1-539"></a><a name="index-_002d_002dtarget1_002drel-540"></a><a name="index-_002d_002dtarget1_002dabs-541"></a>The <span class="samp">R_ARM_TARGET1</span> relocation is typically used for entries in the
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<span class="samp">.init_array</span> section. It is interpreted as either <span class="samp">R_ARM_REL32</span>
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or <span class="samp">R_ARM_ABS32</span>, depending on the target. The <span class="samp">--target1-rel</span>
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and <span class="samp">--target1-abs</span> switches override the default.
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<p><a name="index-TARGET2-542"></a><a name="index-_002d_002dtarget2_003d_0040var_007btype_007d-543"></a>The <span class="samp">--target2=type</span> switch overrides the default definition of the
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<span class="samp">R_ARM_TARGET2</span> relocation. Valid values for <span class="samp">type</span>, their
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meanings, and target defaults are as follows:
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<dl>
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<dt><span class="samp">rel</span><dd><span class="samp">R_ARM_REL32</span> (arm*-*-elf, arm*-*-eabi)
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<br><dt><span class="samp">abs</span><dd><span class="samp">R_ARM_ABS32</span> (arm*-*-symbianelf)
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<br><dt><span class="samp">got-rel</span><dd><span class="samp">R_ARM_GOT_PREL</span> (arm*-*-linux, arm*-*-*bsd)
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</dl>
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<p><a name="index-FIX_005fV4BX-544"></a><a name="index-_002d_002dfix_002dv4bx-545"></a>The <span class="samp">R_ARM_V4BX</span> relocation (defined by the ARM AAELF
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specification) enables objects compiled for the ARMv4 architecture to be
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interworking-safe when linked with other objects compiled for ARMv4t, but
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also allows pure ARMv4 binaries to be built from the same ARMv4 objects.
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<p>In the latter case, the switch <span class="option">--fix-v4bx</span> must be passed to the
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linker, which causes v4t <code>BX rM</code> instructions to be rewritten as
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<code>MOV PC,rM</code>, since v4 processors do not have a <code>BX</code> instruction.
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<p>In the former case, the switch should not be used, and <span class="samp">R_ARM_V4BX</span>
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relocations are ignored.
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<p><a name="index-FIX_005fV4BX_005fINTERWORKING-546"></a><a name="index-_002d_002dfix_002dv4bx_002dinterworking-547"></a>Replace <code>BX rM</code> instructions identified by <span class="samp">R_ARM_V4BX</span>
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relocations with a branch to the following veneer:
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<pre class="smallexample"> TST rM, #1
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MOVEQ PC, rM
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BX Rn
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</pre>
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<p>This allows generation of libraries/applications that work on ARMv4 cores
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and are still interworking safe. Note that the above veneer clobbers the
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condition flags, so may cause incorrect progrm behavior in rare cases.
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<p><a name="index-USE_005fBLX-548"></a><a name="index-_002d_002duse_002dblx-549"></a>The <span class="samp">--use-blx</span> switch enables the linker to use ARM/Thumb
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BLX instructions (available on ARMv5t and above) in various
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situations. Currently it is used to perform calls via the PLT from Thumb
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code using BLX rather than using BX and a mode-switching stub before
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each PLT entry. This should lead to such calls executing slightly faster.
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<p>This option is enabled implicitly for SymbianOS, so there is no need to
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specify it if you are using that target.
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<p><a name="index-VFP11_005fDENORM_005fFIX-550"></a><a name="index-_002d_002dvfp11_002ddenorm_002dfix-551"></a>The <span class="samp">--vfp11-denorm-fix</span> switch enables a link-time workaround for a
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bug in certain VFP11 coprocessor hardware, which sometimes allows
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instructions with denorm operands (which must be handled by support code)
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to have those operands overwritten by subsequent instructions before
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the support code can read the intended values.
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<p>The bug may be avoided in scalar mode if you allow at least one
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intervening instruction between a VFP11 instruction which uses a register
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and another instruction which writes to the same register, or at least two
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intervening instructions if vector mode is in use. The bug only affects
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full-compliance floating-point mode: you do not need this workaround if
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you are using "runfast" mode. Please contact ARM for further details.
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<p>If you know you are using buggy VFP11 hardware, you can
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enable this workaround by specifying the linker option
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<span class="samp">--vfp-denorm-fix=scalar</span> if you are using the VFP11 scalar
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mode only, or <span class="samp">--vfp-denorm-fix=vector</span> if you are using
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vector mode (the latter also works for scalar code). The default is
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<span class="samp">--vfp-denorm-fix=none</span>.
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<p>If the workaround is enabled, instructions are scanned for
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potentially-troublesome sequences, and a veneer is created for each
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such sequence which may trigger the erratum. The veneer consists of the
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first instruction of the sequence and a branch back to the subsequent
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instruction. The original instruction is then replaced with a branch to
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the veneer. The extra cycles required to call and return from the veneer
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are sufficient to avoid the erratum in both the scalar and vector cases.
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<p><a name="index-NO_005fENUM_005fSIZE_005fWARNING-552"></a><a name="index-_002d_002dno_002denum_002dsize_002dwarning-553"></a>The <span class="option">--no-enum-size-warning</span> switch prevents the linker from
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warning when linking object files that specify incompatible EABI
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enumeration size attributes. For example, with this switch enabled,
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linking of an object file using 32-bit enumeration values with another
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using enumeration values fitted into the smallest possible space will
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not be diagnosed.
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<p><a name="index-NO_005fWCHAR_005fSIZE_005fWARNING-554"></a><a name="index-_002d_002dno_002dwchar_002dsize_002dwarning-555"></a>The <span class="option">--no-wchar-size-warning</span> switch prevents the linker from
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warning when linking object files that specify incompatible EABI
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<code>wchar_t</code> size attributes. For example, with this switch enabled,
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linking of an object file using 32-bit <code>wchar_t</code> values with another
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using 16-bit <code>wchar_t</code> values will not be diagnosed.
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<p><a name="index-PIC_005fVENEER-556"></a><a name="index-_002d_002dpic_002dveneer-557"></a>The <span class="samp">--pic-veneer</span> switch makes the linker use PIC sequences for
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ARM/Thumb interworking veneers, even if the rest of the binary
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is not PIC. This avoids problems on uClinux targets where
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<span class="samp">--emit-relocs</span> is used to generate relocatable binaries.
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<p><a name="index-STUB_005fGROUP_005fSIZE-558"></a><a name="index-_002d_002dstub_002dgroup_002dsize_003d_0040var_007bN_007d-559"></a>The linker will automatically generate and insert small sequences of
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code into a linked ARM ELF executable whenever an attempt is made to
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perform a function call to a symbol that is too far away. The
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placement of these sequences of instructions - called stubs - is
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controlled by the command line option <span class="option">--stub-group-size=N</span>.
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The placement is important because a poor choice can create a need for
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duplicate stubs, increasing the code sizw. The linker will try to
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group stubs together in order to reduce interruptions to the flow of
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code, but it needs guidance as to how big these groups should be and
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where they should be placed.
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<p>The value of <span class="samp">N</span>, the parameter to the
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<span class="option">--stub-group-size=</span> option controls where the stub groups are
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placed. If it is negative then all stubs are placed before the first
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branch that needs them. If it is positive then the stubs can be
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placed either before or after the branches that need them. If the
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value of <span class="samp">N</span> is 1 (either +1 or -1) then the linker will choose
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exactly where to place groups of stubs, using its built in heuristics.
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A value of <span class="samp">N</span> greater than 1 (or smaller than -1) tells the
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linker that a single group of stubs can service at most <span class="samp">N</span> bytes
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from the input sections.
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<p>The default, if <span class="option">--stub-group-size=</span> is not specified, is
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<span class="samp">N = +1</span>.
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<p>Farcalls stubs insertion is fully supported for the ARM-EABI target
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only, because it relies on object files properties not present
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otherwise.
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</body></html>
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