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248 lines
15 KiB
Plaintext
248 lines
15 KiB
Plaintext
15 years ago
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# $Id: README.opcodes,v 1.3 2001/12/02 21:54:45 troth Exp $
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#
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##############################################################################
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##
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## Most of the information in this file was taken directly from the Atmel
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## data sheets and is most likely copyrighted by Atmel. As such, this file
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## may need to disappear.
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##
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##############################################################################
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Instruction Set Nomenclature:
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Status Register (SREG)
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SREG: Status register
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C: Carry flag in status register
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Z: Zero flag in status register
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N: Negative flag in status register
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V: Two's complement overflow indicator
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S: N A* V, For signed tests
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H: Half Carry flag in the status register
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T: Transfer bit used by BLD and BST instructions
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I: Global interrupt enable/disable flag
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Registers and Operands
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Rd: Destination (and source) register in the register file
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Rr: Source register in the register file
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R: Result after instruction is executed
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K: Constant data
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k: Constant address
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b: Bit in the register file or I/O register (3 bit)
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s: Bit in the status register (3 bit)
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X,Y,Z: Indirect address register (X=R27:R26, Y=R29:R28 and Z=R31:R30)
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A: I/O location address
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q: Displacement for direct addressing (6 bit)
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I/O Registers
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RAMPX, RAMPY, RAMPZ
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Registers concatenated with the X, Y and Z registers enabling indirect
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addressing of the whole data space on MCUs withmore than 64K bytes data space,
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and constant data fetch on MCUs with more than 64K bytes program space.
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RAMPD
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Register concatenated with the Z register enabling direct addressing of the
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whole data space on MCUs with more than 64Kbytes data space.
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EIND
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Register concatenated with the instruction word enabling indirect jump and
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call to the whole program space on MCUs withmore than 64K bytes program space.
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Stack
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STACK: Stack for return address and pushed registers
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SP: Stack Pointer to STACK
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Flags
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<=>: Flag affected by instruction
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0: Flag cleared by instruction
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1: Flag set by instruction
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-: Flag not affected by instruction
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Conditional Branch Summary
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Note: 1. Interchange Rd and Rr in the operation before the test. i.e.
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CP Rd,Rr -> CP Rr,Rd
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Test Boolean Mnemonic Complementary Boolean Mnemonic Comment
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Rd > Rr Z&(N ^ V) = 0 BRLT(1) Rd <= Rr Z+(N ^ V) = 1 BRGE* Signed
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Rd >= Rr (N ^ V) = 0 BRGE Rd < Rr (N ^ V) = 1 BRLT Signed
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Rd = Rr Z = 1 BREQ Rd != Rr Z = 0 BRNE Signed
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Rd <= Rr Z+(N ^ V) = 1 BRGE(1) Rd > Rr Z&(N ^ V) = 0 BRLT* Signed
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Rd < Rr (N ^ V) = 1 BRLT Rd >= Rr (N ^ V) = 0 BRGE Signed
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Rd > Rr C + Z = 0 BRLO(1) Rd <= Rr C + Z = 1 BRSH* Unsigned
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Rd >= Rr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS Unsigned
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Rd = Rr Z = 1 BREQ Rd != Rr Z = 0 BRNE Unsigned
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Rd <= Rr C + Z = 1 BRSH(1) Rd > Rr C + Z = 0 BRLO* Unsigned
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Rd < Rr C = 1 BRLO/BRCS Rd >= Rr C = 0 BRSH/BRCC Unsigned
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Carry C = 1 BRCS No carry C = 0 BRCC Simple
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Negative N = 1 BRMI Positive N = 0 BRPL Simple
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Overflow V = 1 BRVS No overflow V = 0 BRVC Simple
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Zero Z = 1 BREQ Not zero Z = 0 BRNE Simple
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Complete Instruction Set Summary
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Notes:
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1. Not all instructions are available in all devices. Refer to the device
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specific instruction summary.
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2. Cycle times for data memory accesses assume internal memory accesses, and
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are not valid for accesses via the external RAM interface. For LD, ST, LDS,
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STS, PUSH, POP, add one cycle plus one cycle for each wait state. For CALL,
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ICALL, EICALL, RCALL, RET, RETI in devices with 16 bit PC, add three cycles
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plus two cycles for each wait state. For CALL, ICALL, EICALL, RCALL, RET,
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RETI in devices with 22 bit PC, add five cycles plus three cycles for each
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wait state.
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Instruction Set Summary
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Arithmetic and Logic Instructions
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| | | | Device Availability|
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Mnem | Opcode | Operands | Method Name | 1200 | 4414 | 8515 |
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=======|=====================|==========|=============|======|======|======|
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ADC | 0001 11rd dddd rrrr | Rd, Rr | ADC | * | * | * |
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ADD | 0000 11rd dddd rrrr | Rd, Rr | ADD | * | * | * |
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ADIW | 1001 0110 KKdd KKKK | Rd, Rr | ADIW | - | * | * |
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AND | 0010 00rd dddd rrrr | Rd, Rr | AND | * | * | * |
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ANDI | 0111 KKKK dddd KKKK | Rd, K | ANDI | * | * | * |
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ASR | 1001 010d dddd 0101 | Rd | ASR | * | * | * |
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BCLR | 1001 0100 1sss 1000 | s | BCLR | * | * | * |
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BLD | 1111 100d dddd 0bbb | Rd, b | BLD | * | * | * |
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BRBC | 1111 01kk kkkk ksss | s, k | BRCS | * | * | * |
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BRBS | 1111 00kk kkkk ksss | s, k | BRBS | * | * | * |
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BRCC | 1111 01kk kkkk k000 | k | BRCC | * | * | * |
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BRCS | 1111 00kk kkkk k000 | k | BRCS | * | * | * |
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BREQ | 1111 00kk kkkk k001 | k | BREQ | * | * | * |
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BRGE | 1111 01kk kkkk k100 | k | BRGE | * | * | * |
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BRHC | 1111 01kk kkkk k101 | k | BRHC | * | * | * |
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BRHS | 1111 00kk kkkk k101 | k | BRHS | * | * | * |
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BRID | 1111 01kk kkkk k111 | k | BRID | * | * | * |
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BRIE | 1111 00kk kkkk k111 | k | BRIE | * | * | * |
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BRLO | 1111 00kk kkkk k000 | k | BRCS | * | * | * |
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BRLT | 1111 00kk kkkk k100 | k | BRLT | * | * | * |
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BRMI | 1111 00kk kkkk k010 | k | BRMI | * | * | * |
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BRNE | 1111 01kk kkkk k001 | k | BRNE | * | * | * |
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BRPL | 1111 01kk kkkk k010 | k | BRPL | * | * | * |
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BRSH | 1111 01kk kkkk k000 | k | BRCC | * | * | * |
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BRTC | 1111 01kk kkkk k110 | k | BRTC | * | * | * |
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BRTS | 1111 00kk kkkk k110 | k | BRTS | * | * | * |
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BRVC | 1111 01kk kkkk k011 | k | BRVC | * | * | * |
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BRVS | 1111 00kk kkkk k011 | k | BRVS | * | * | * |
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BSET | 1001 0100 0sss 1000 | s | BSET | * | * | * |
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BST | 1111 101d dddd 0bbb | Rr, b | BST | * | * | * |
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CALL | 1001 010k kkkk 111k | k | CALL | - | - | - |
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| kkkk kkkk kkkk kkkk | | | | | |
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CBI | 1001 1000 AAAA Abbb | A, b | CBI | * | * | * |
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CBR | 0111 KKKK dddd KKKK | Rd, K | CBR | * | * | * |
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CLC | 1001 0100 1000 1000 | | CLC | * | * | * |
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CLH | 1001 0100 1101 1000 | | CLH | * | * | * |
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CLI | 1001 0100 1111 1000 | | CLI | * | * | * |
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CLN | 1001 0100 1010 1000 | | CLN | * | * | * |
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CLR | 0010 01dd dddd dddd | Rd | EOR | * | * | * |
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CLS | 1001 0100 1100 1000 | | CLS | * | * | * |
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CLT | 1001 0100 1110 1000 | | CLT | * | * | * |
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CLV | 1001 0100 1011 1000 | | CLV | * | * | * |
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CLZ | 1001 0100 1001 1000 | | CLZ | * | * | * |
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COM | 1001 010d dddd 0000 | Rd | COM | * | * | * |
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CP | 0001 01rd dddd rrrr | Rd, Rr | CP | * | * | * |
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CPC | 0000 01rd dddd rrrr | Rd, Rr | CPC | * | * | * |
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CPI | 0011 KKKK dddd KKKK | Rd, K | CPI | * | * | * |
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CPSE | 0001 00rd dddd rrrr | Rd, Rr | CPSE | * | * | * |
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DEC | 1001 010d dddd 1010 | Rd | DEC | * | * | * |
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EICALL | 1001 0101 0001 1001 | | EICALL | - | - | - |
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EIJMP | 1001 0100 0001 1001 | | EIJMP | - | - | - |
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ELPM | 1001 0101 1101 1000 | | ELPM | - | - | - |
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ELPM | 1001 000d dddd 0110 | Rd, Z | ELPM_Z | - | - | - |
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ELPM | 1001 000d dddd 0111 | Rd, Z+ | ELPM_Z_incr | - | - | - |
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EOR | 0010 01rd dddd rrrr | Rd, Rr | EOR | * | * | * |
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ESPM | 1001 0101 1111 1000 | | ESPM | - | - | - |
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FMUL | 0000 0011 0ddd 1rrr | Rd, Rr | FMUL | - | - | - |
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FMULS | 0000 0011 1ddd 0rrr | Rd, Rr | FMULS | - | - | - |
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FMULSU | 0000 0011 1ddd 1rrr | Rd, Rr | FMULSU | - | - | - |
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ICALL | 1001 0101 0000 1001 | | ICALL | - | * | * |
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IJMP | 1001 0100 0000 1001 | | IJMP | - | * | * |
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IN | 1011 0AAd dddd AAAA | Rd, A | IN | * | * | * |
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INC | 1001 010d dddd 0011 | Rd | INC | * | * | * |
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JMP | 1001 010k kkkk 110k | k | JMP | - | - | - |
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| kkkk kkkk kkkk kkkk | | | | | |
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LD | 1000 000d dddd 1000 | Rd, Y | LDD_Y | - | * | * |
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LD | 1001 000d dddd 1001 | Rd, Y+ | LD_Y_incr | - | * | * |
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LD | 1000 000d dddd 0000 | Rd, Z | LDD_Z | * | * | * |
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LD | 1001 000d dddd 0001 | Rd, Z+ | LD_Z_incr | - | * | * |
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LD | 1001 000d dddd 1110 | Rd, -X | LD_X_decr | - | * | * |
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LD | 1001 000d dddd 1010 | Rd, -Y | LD_Y_decr | - | * | * |
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LD | 1001 000d dddd 0010 | Rd, -Z | LD_Z_decr | - | * | * |
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LD | 1001 000d dddd 1100 | Rd, X | LD_X | - | * | * |
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LD | 1001 000d dddd 1101 | Rd, X+ | LD_X_incr | - | * | * |
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LDD | 10q0 qq0d dddd 1qqq | Rd, Y+q | LDD_Y | - | * | * |
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LDD | 10q0 qq0d dddd 0qqq | Rd, Z+q | LDD_Z | - | * | * |
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LDI | 1110 KKKK dddd KKKK | Rd, K | LDI | * | * | * |
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LDS | 1001 000d dddd 0000 | Rd, k | LDS | - | * | * |
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| kkkk kkkk kkkk kkkk | | | | | |
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LPM | 1001 0101 1100 1000 | | LPM | - | * | * |
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LPM | 1001 000d dddd 0100 | Rd, Z | LPM_Z | - | - | - |
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LPM | 1001 000d dddd 0101 | Rd, Z+ | LPM_Z_incr | - | - | - |
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LSL | 0000 11dd dddd dddd | Rd | AND | * | * | * |
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LSR | 1001 010d dddd 0110 | Rd | LSR | * | * | * |
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MOV | 0010 11rd dddd rrrr | Rd, Rr | MOV | * | * | * |
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MOVW | 0000 0001 dddd rrrr | Rd, Rr | MOVW | - | - | - |
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MUL | 1001 11rd dddd rrrr | Rd, Rr | MUL | - | - | - |
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MULS | 0000 0010 dddd rrrr | Rd, Rr | MULS | - | - | - |
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MULSU | 0000 0011 dddd rrrr | Rd, Rr | MULSU | - | - | - |
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NEG | 1001 010d dddd 0001 | Rd | NEG | * | * | * |
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NOP | 0000 0000 0000 0000 | | NOP | * | * | * |
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OR | 0010 10rd dddd rrrr | Rd, Rr | OR | * | * | * |
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ORI | 0110 KKKK dddd KKKK | Rd, K | ORI | * | * | * |
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OUT | 1011 1AAd dddd AAAA | A, Rd | OUT | * | * | * |
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POP | 1001 000d dddd 1111 | Rd | POP | - | * | * |
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PUSH | 1001 001d dddd 1111 | Rd | PUSH | - | * | * |
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RCALL | 1101 kkkk kkkk kkkk | k | RCALL | * | * | * |
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RET | 1001 0101 0000 1000 | | RET | * | * | * |
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RETI | 1001 0101 0001 1000 | | RETI | * | * | * |
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RJMP | 1100 kkkk kkkk kkkk | k | RJMP | * | * | * |
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ROL | 0001 11dd dddd dddd | Rd | ADC | * | * | * |
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ROR | 1001 010d dddd 0111 | Rd | ROR | * | * | * |
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SBC | 0000 10rd dddd rrrr | Rd, Rr | SBC | * | * | * |
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SBCI | 0100 KKKK dddd KKKK | Rd, K | SBCI | * | * | * |
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SBI | 1001 1010 AAAA Abbb | A, b | SBI | * | * | * |
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SBIC | 1001 1001 AAAA Abbb | A, b | SBIC | * | * | * |
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SBIS | 1001 1011 AAAA Abbb | A, b | SBIS | * | * | * |
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SBIW | 1001 0111 KKdd KKKK | Rd, K | SBIW | - | - | - |
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SBR | 0110 KKKK dddd KKKK | Rd, K | SBR | * | * | * |
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SBRC | 1111 110d dddd 0bbb | Rd, b | SBRC | * | * | * |
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SBRS | 1111 111d dddd 0bbb | Rd, b | SBRS | * | * | * |
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SEC | 1001 0100 0000 1000 | | SEC | * | * | * |
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SEH | 1001 0100 0101 1000 | | SEH | * | * | * |
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SEI | 1001 0100 0111 1000 | | SEI | * | * | * |
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SEN | 1001 0100 0010 1000 | | SEN | * | * | * |
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SER | 1110 1111 dddd 1111 | Rd | LDI | * | * | * |
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SES | 1001 0100 0100 1000 | | SES | * | * | * |
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SET | 1001 0100 0110 1000 | | SET | * | * | * |
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SEV | 1001 0100 0011 1000 | | SEV | * | * | * |
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SEZ | 1001 0100 0001 1000 | | SEZ | * | * | * |
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SLEEP | 1001 0101 1000 1000 | | SLEEP | * | * | * |
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SPM | 1001 0101 1110 1000 | | SPM | - | - | - |
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ST | 1001 001d dddd 1101 | X+, Rd | ST_X_incr | - | * | * |
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ST | 1001 001d dddd 1100 | X, Rd | ST_X | - | * | * |
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ST | 1001 001d dddd 1001 | Y+, Rd | ST_Y_incr | - | * | * |
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ST | 1000 001d dddd 1000 | Y, Rd | STD_Y | - | * | * |
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ST | 1001 001d dddd 0001 | Z+, Rd | ST_Z_incr | - | * | * |
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ST | 1000 001d dddd 0000 | Z, Rd | STD_Z | * | * | * |
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ST | 1001 001d dddd 1110 |-X, Rd | ST_X_decr | - | * | * |
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ST | 1001 001d dddd 1010 |-Y, Rd | ST_Y_decr | - | * | * |
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ST | 1001 001d dddd 0010 |-Z, Rd | ST_Z_decr | - | * | * |
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STD | 10q0 qq1d dddd 1qqq | Y+q, Rd | STD_Y | - | * | * |
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STD | 10q0 qq1d dddd 0qqq | Z+q, Rd | STD_Z | - | * | * |
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STS | 1001 001d dddd 0000 | k, Rd | STS | - | * | * |
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| kkkk kkkk kkkk kkkk | | | | | |
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SUB | 0001 10rd dddd rrrr | Rd, Rr | SUB | * | * | * |
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SUBI | 0101 KKKK dddd KKKK | Rd, K | SUBI | * | * | * |
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SWAP | 1001 010d dddd 0010 | Rd | SWAP | * | * | * |
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TST | 0010 00dd dddd dddd | Rd | AND | * | * | * |
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WDR | 1001 0101 1010 1000 | | WDR | * | * | * |
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