101 lines
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101 lines
4.5 KiB
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<html lang="en">
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<head>
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<title>Opcodes for i860 - Using as</title>
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<meta name="description" content="Using as">
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<meta name="generator" content="makeinfo 4.7">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="i860_002dDependent.html#i860_002dDependent" title="i860-Dependent">
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<link rel="prev" href="Directives_002di860.html#Directives_002di860" title="Directives-i860">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
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2006, 2007 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.1
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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man end-->
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<style type="text/css"><!--
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--></style>
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</head>
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<body>
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<div class="node">
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<p>
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<a name="Opcodes-for-i860"></a>Previous: <a rel="previous" accesskey="p" href="Directives_002di860.html#Directives_002di860">Directives-i860</a>,
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Up: <a rel="up" accesskey="u" href="i860_002dDependent.html#i860_002dDependent">i860-Dependent</a>
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<hr><br>
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</div>
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<h4 class="subsection">9.14.4 i860 Opcodes</h4>
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<p><a name="index-opcodes_002c-i860-972"></a><a name="index-i860-opcodes-973"></a>All of the Intel i860XR and i860XP machine instructions are supported. Please see
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either <em>i860 Microprocessor Programmer's Reference Manual</em> or <em>i860 Microprocessor Architecture</em> for more information.
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<h5 class="subsubsection">9.14.4.1 Other instruction support (pseudo-instructions)</h5>
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<p>For compatibility with some other i860 assemblers, a number of
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pseudo-instructions are supported. While these are supported, they are
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a very undesirable feature that should be avoided – in particular, when
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they result in an expansion to multiple actual i860 instructions. Below
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are the pseudo-instructions that result in expansions.
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<ul>
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<li>Load large immediate into general register:
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<p>The pseudo-instruction <code>mov imm,%rn</code> (where the immediate does
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not fit within a signed 16-bit field) will be expanded into:
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<pre class="smallexample"> orh large_imm@h,%r0,%rn
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or large_imm@l,%rn,%rn
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</pre>
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<li>Load/store with relocatable address expression:
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<p>For example, the pseudo-instruction <code>ld.b addr_exp(%rx),%rn</code>
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will be expanded into:
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<pre class="smallexample"> orh addr_exp@ha,%rx,%r31
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ld.l addr_exp@l(%r31),%rn
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</pre>
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<p>The analogous expansions apply to <code>ld.x, st.x, fld.x, pfld.x, fst.x</code>, and <code>pst.x</code> as well.
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<li>Signed large immediate with add/subtract:
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<p>If any of the arithmetic operations <code>adds, addu, subs, subu</code> are used
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with an immediate larger than 16-bits (signed), then they will be expanded.
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For instance, the pseudo-instruction <code>adds large_imm,%rx,%rn</code> expands to:
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<pre class="smallexample"> orh large_imm@h,%r0,%r31
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or large_imm@l,%r31,%r31
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adds %r31,%rx,%rn
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</pre>
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<li>Unsigned large immediate with logical operations:
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<p>Logical operations (<code>or, andnot, or, xor</code>) also result in expansions.
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The pseudo-instruction <code>or large_imm,%rx,%rn</code> results in:
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<pre class="smallexample"> orh large_imm@h,%rx,%r31
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or large_imm@l,%r31,%rn
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</pre>
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<p>Similarly for the others, except for <code>and</code> which expands to:
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<pre class="smallexample"> andnot (-1 - large_imm)@h,%rx,%r31
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andnot (-1 - large_imm)@l,%r31,%rn
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</pre>
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</ul>
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<!-- Copyright 1991, 1992, 1993, 1994, 1995, 1996, 2002 -->
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<!-- Free Software Foundation, Inc. -->
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<!-- This is part of the GAS manual. -->
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<!-- For copying conditions, see the file as.texinfo. -->
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</body></html>
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