arduino-0018-windows
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arduino-0018-windows/hardware/arduino/boards.txt
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arduino-0018-windows/hardware/arduino/boards.txt
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##############################################################
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atmega328.name=Arduino Duemilanove or Nano w/ ATmega328
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atmega328.upload.protocol=stk500
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atmega328.upload.maximum_size=30720
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atmega328.upload.speed=57600
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atmega328.bootloader.low_fuses=0xFF
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atmega328.bootloader.high_fuses=0xDA
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atmega328.bootloader.extended_fuses=0x05
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atmega328.bootloader.path=atmega
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atmega328.bootloader.file=ATmegaBOOT_168_atmega328.hex
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atmega328.bootloader.unlock_bits=0x3F
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atmega328.bootloader.lock_bits=0x0F
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atmega328.build.mcu=atmega328p
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atmega328.build.f_cpu=16000000L
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atmega328.build.core=arduino
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##############################################################
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diecimila.name=Arduino Diecimila, Duemilanove, or Nano w/ ATmega168
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diecimila.upload.protocol=stk500
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diecimila.upload.maximum_size=14336
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diecimila.upload.speed=19200
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diecimila.bootloader.low_fuses=0xff
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diecimila.bootloader.high_fuses=0xdd
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diecimila.bootloader.extended_fuses=0x00
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diecimila.bootloader.path=atmega
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diecimila.bootloader.file=ATmegaBOOT_168_diecimila.hex
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diecimila.bootloader.unlock_bits=0x3F
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diecimila.bootloader.lock_bits=0x0F
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diecimila.build.mcu=atmega168
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diecimila.build.f_cpu=16000000L
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diecimila.build.core=arduino
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##############################################################
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mega.name=Arduino Mega
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mega.upload.protocol=stk500
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mega.upload.maximum_size=126976
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mega.upload.speed=57600
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mega.bootloader.low_fuses=0xFF
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mega.bootloader.high_fuses=0xDA
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mega.bootloader.extended_fuses=0xF5
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mega.bootloader.path=atmega
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mega.bootloader.file=ATmegaBOOT_168_atmega1280.hex
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mega.bootloader.unlock_bits=0x3F
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mega.bootloader.lock_bits=0x0F
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mega.build.mcu=atmega1280
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mega.build.f_cpu=16000000L
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mega.build.core=arduino
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##############################################################
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mini.name=Arduino Mini
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mini.upload.protocol=stk500
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mini.upload.maximum_size=14336
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mini.upload.speed=19200
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mini.bootloader.low_fuses=0xff
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mini.bootloader.high_fuses=0xdd
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mini.bootloader.extended_fuses=0x00
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mini.bootloader.path=atmega
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mini.bootloader.file=ATmegaBOOT_168_ng.hex
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mini.bootloader.unlock_bits=0x3F
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mini.bootloader.lock_bits=0x0F
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mini.build.mcu=atmega168
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mini.build.f_cpu=16000000L
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mini.build.core=arduino
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##############################################################
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bt.name=Arduino BT
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bt.upload.protocol=stk500
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bt.upload.maximum_size=14336
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bt.upload.speed=19200
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bt.upload.disable_flushing=true
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bt.bootloader.low_fuses=0xff
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bt.bootloader.high_fuses=0xdd
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bt.bootloader.extended_fuses=0x00
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bt.bootloader.path=bt
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bt.bootloader.file=ATmegaBOOT_168.hex
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bt.bootloader.unlock_bits=0x3F
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bt.bootloader.lock_bits=0x0F
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bt.build.mcu=atmega168
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bt.build.f_cpu=16000000L
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bt.build.core=arduino
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##############################################################
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lilypad328.name=LilyPad Arduino w/ ATmega328
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lilypad328.upload.protocol=stk500
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lilypad328.upload.maximum_size=30720
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lilypad328.upload.speed=57600
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lilypad328.bootloader.low_fuses=0xFF
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lilypad328.bootloader.high_fuses=0xDA
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lilypad328.bootloader.extended_fuses=0x05
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lilypad328.bootloader.path=atmega
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lilypad328.bootloader.file=ATmegaBOOT_168_atmega328_pro_8MHz.hex
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lilypad328.bootloader.unlock_bits=0x3F
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lilypad328.bootloader.lock_bits=0x0F
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lilypad328.build.mcu=atmega328p
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lilypad328.build.f_cpu=8000000L
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lilypad328.build.core=arduino
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##############################################################
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lilypad.name=LilyPad Arduino w/ ATmega168
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lilypad.upload.protocol=stk500
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lilypad.upload.maximum_size=14336
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lilypad.upload.speed=19200
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lilypad.bootloader.low_fuses=0xe2
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lilypad.bootloader.high_fuses=0xdd
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lilypad.bootloader.extended_fuses=0x00
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lilypad.bootloader.path=lilypad
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lilypad.bootloader.file=LilyPadBOOT_168.hex
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lilypad.bootloader.unlock_bits=0x3F
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lilypad.bootloader.lock_bits=0x0F
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lilypad.build.mcu=atmega168
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lilypad.build.f_cpu=8000000L
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lilypad.build.core=arduino
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##############################################################
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pro328.name=Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega328
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pro328.upload.protocol=stk500
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pro328.upload.maximum_size=30720
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pro328.upload.speed=57600
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pro328.bootloader.low_fuses=0xFF
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pro328.bootloader.high_fuses=0xDA
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pro328.bootloader.extended_fuses=0x05
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pro328.bootloader.path=atmega
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pro328.bootloader.file=ATmegaBOOT_168_atmega328_pro_8MHz.hex
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pro328.bootloader.unlock_bits=0x3F
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pro328.bootloader.lock_bits=0x0F
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pro328.build.mcu=atmega328p
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pro328.build.f_cpu=8000000L
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pro328.build.core=arduino
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##############################################################
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pro.name=Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega168
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pro.upload.protocol=stk500
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pro.upload.maximum_size=14336
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pro.upload.speed=19200
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pro.bootloader.low_fuses=0xc6
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pro.bootloader.high_fuses=0xdd
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pro.bootloader.extended_fuses=0x00
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pro.bootloader.path=atmega
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pro.bootloader.file=ATmegaBOOT_168_pro_8MHz.hex
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pro.bootloader.unlock_bits=0x3F
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pro.bootloader.lock_bits=0x0F
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pro.build.mcu=atmega168
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pro.build.f_cpu=8000000L
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pro.build.core=arduino
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##############################################################
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atmega168.name=Arduino NG or older w/ ATmega168
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atmega168.upload.protocol=stk500
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atmega168.upload.maximum_size=14336
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atmega168.upload.speed=19200
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atmega168.bootloader.low_fuses=0xff
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atmega168.bootloader.high_fuses=0xdd
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atmega168.bootloader.extended_fuses=0x00
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atmega168.bootloader.path=atmega
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atmega168.bootloader.file=ATmegaBOOT_168_ng.hex
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atmega168.bootloader.unlock_bits=0x3F
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atmega168.bootloader.lock_bits=0x0F
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atmega168.build.mcu=atmega168
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atmega168.build.f_cpu=16000000L
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atmega168.build.core=arduino
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##############################################################
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atmega8.name=Arduino NG or older w/ ATmega8
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atmega8.upload.protocol=stk500
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atmega8.upload.maximum_size=7168
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atmega8.upload.speed=19200
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atmega8.bootloader.low_fuses=0xdf
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atmega8.bootloader.high_fuses=0xca
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atmega8.bootloader.path=atmega8
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atmega8.bootloader.file=ATmegaBOOT.hex
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atmega8.bootloader.unlock_bits=0x3F
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atmega8.bootloader.lock_bits=0x0F
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atmega8.build.mcu=atmega8
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atmega8.build.f_cpu=16000000L
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atmega8.build.core=arduino
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:103B3000CAC083E00E94E21C80E0DACF0E94761CBB
|
||||
:103B4000809309020E94761C8093080280910C02E7
|
||||
:103B50008E7F80930C020E94761C853409F4C4C0C9
|
||||
:103B600000E010E0809108029091090218161906F1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:103C7000F0930701E09306012091080230910902B8
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:103D000087FD6FC010920B02809106019091070110
|
||||
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|
||||
:103D200080FF09C08091080290910902019690934A
|
||||
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|
||||
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|
||||
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|
||||
:103D600003E000935700E89500915700017001307F
|
||||
:103D7000D9F301E100935700E8950990199000915B
|
||||
:103D8000570001700130D9F301E000935700E89526
|
||||
:103D90001395103498F011270091570001700130ED
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:103DE00012CE81E080930B028FCF82E00E94C31C31
|
||||
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|
||||
:103E000002CE84910E94A21C2091080230910902E6
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:103E7000C82F85958595859585958A3034F0895A22
|
||||
:103E8000CF70CA3034F0C95A05C0805DCF70CA30D7
|
||||
:103E9000D4F7C05D0E94A21C8C2F0E94A21CCF915F
|
||||
:043EA0000895FFCFB3
|
||||
:023EA40080009C
|
||||
:0400000300003800C1
|
||||
:00000001FF
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
:103800000C94341C0C94511C0C94511C0C94511CA1
|
||||
:103810000C94511C0C94511C0C94511C0C94511C74
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:1038A000D51F0C94001C982F9595959595959595F9
|
||||
:1038B000905D8F708A307CF0282F295A8091C0004B
|
||||
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|
||||
:1038D0002093C6000895282F205DF0CF982F809167
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:103F00000802909109020196909309028093080299
|
||||
:103F1000F894F999FECF1127E0910601F09107017D
|
||||
:103F2000C8E0D1E08091080290910902103091F42C
|
||||
:103F30000091570001700130D9F303E0009357005E
|
||||
:103F4000E8950091570001700130D9F301E1009329
|
||||
:103F50005700E895099019900091570001700130C1
|
||||
:103F6000D9F301E000935700E8951395103498F0C9
|
||||
:103F700011270091570001700130D9F305E000933B
|
||||
:103F80005700E8950091570001700130D9F301E125
|
||||
:103F900000935700E8953296029709F0C7CF10308A
|
||||
:0E3FA00011F00296E5CF11245CCFF894FFCF0C
|
||||
:023FAE00800091
|
||||
:0400000300003800C1
|
||||
:00000001FF
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
# Makefile for ATmegaBOOT
|
||||
# E.Lins, 18.7.2005
|
||||
# $Id$
|
||||
#
|
||||
# Instructions
|
||||
#
|
||||
# To make bootloader .hex file:
|
||||
# make diecimila
|
||||
# make lilypad
|
||||
# make ng
|
||||
# etc...
|
||||
#
|
||||
# To burn bootloader .hex file:
|
||||
# make diecimila_isp
|
||||
# make lilypad_isp
|
||||
# make ng_isp
|
||||
# etc...
|
||||
|
||||
# program name should not be changed...
|
||||
PROGRAM = ATmegaBOOT_168
|
||||
|
||||
# enter the parameters for the avrdude isp tool
|
||||
ISPTOOL = stk500v2
|
||||
ISPPORT = usb
|
||||
ISPSPEED = -b 115200
|
||||
|
||||
MCU_TARGET = atmega168
|
||||
LDSECTION = --section-start=.text=0x3800
|
||||
|
||||
# the efuse should really be 0xf8; since, however, only the lower
|
||||
# three bits of that byte are used on the atmega168, avrdude gets
|
||||
# confused if you specify 1's for the higher bits, see:
|
||||
# http://tinker.it/now/2007/02/24/the-tale-of-avrdude-atmega168-and-extended-bits-fuses/
|
||||
#
|
||||
# similarly, the lock bits should be 0xff instead of 0x3f (to
|
||||
# unlock the bootloader section) and 0xcf instead of 0x0f (to
|
||||
# lock it), but since the high two bits of the lock byte are
|
||||
# unused, avrdude would get confused.
|
||||
|
||||
ISPFUSES = avrdude -c $(ISPTOOL) -p $(MCU_TARGET) -P $(ISPPORT) $(ISPSPEED) \
|
||||
-e -u -U lock:w:0x3f:m -U efuse:w:0x$(EFUSE):m -U hfuse:w:0x$(HFUSE):m -U lfuse:w:0x$(LFUSE):m
|
||||
ISPFLASH = avrdude -c $(ISPTOOL) -p $(MCU_TARGET) -P $(ISPPORT) $(ISPSPEED) \
|
||||
-U flash:w:$(PROGRAM)_$(TARGET).hex -U lock:w:0x0f:m
|
||||
|
||||
STK500 = "C:\Program Files\Atmel\AVR Tools\STK500\Stk500.exe"
|
||||
STK500-1 = $(STK500) -e -d$(MCU_TARGET) -pf -vf -if$(PROGRAM)_$(TARGET).hex \
|
||||
-lFF -LFF -f$(HFUSE)$(LFUSE) -EF8 -ms -q -cUSB -I200kHz -s -wt
|
||||
STK500-2 = $(STK500) -d$(MCU_TARGET) -ms -q -lCF -LCF -cUSB -I200kHz -s -wt
|
||||
|
||||
|
||||
OBJ = $(PROGRAM).o
|
||||
OPTIMIZE = -O2
|
||||
|
||||
DEFS =
|
||||
LIBS =
|
||||
|
||||
CC = avr-gcc
|
||||
|
||||
# Override is only needed by avr-lib build system.
|
||||
|
||||
override CFLAGS = -g -Wall $(OPTIMIZE) -mmcu=$(MCU_TARGET) -DF_CPU=$(AVR_FREQ) $(DEFS)
|
||||
override LDFLAGS = -Wl,$(LDSECTION)
|
||||
#override LDFLAGS = -Wl,-Map,$(PROGRAM).map,$(LDSECTION)
|
||||
|
||||
OBJCOPY = avr-objcopy
|
||||
OBJDUMP = avr-objdump
|
||||
|
||||
all:
|
||||
|
||||
lilypad: TARGET = lilypad
|
||||
lilypad: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>1' '-DNUM_LED_FLASHES=3'
|
||||
lilypad: AVR_FREQ = 8000000L
|
||||
lilypad: $(PROGRAM)_lilypad.hex
|
||||
|
||||
lilypad_isp: lilypad
|
||||
lilypad_isp: TARGET = lilypad
|
||||
lilypad_isp: HFUSE = DD
|
||||
lilypad_isp: LFUSE = E2
|
||||
lilypad_isp: EFUSE = 00
|
||||
lilypad_isp: isp
|
||||
|
||||
lilypad_resonator: TARGET = lilypad_resonator
|
||||
lilypad_resonator: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>4' '-DNUM_LED_FLASHES=3'
|
||||
lilypad_resonator: AVR_FREQ = 8000000L
|
||||
lilypad_resonator: $(PROGRAM)_lilypad_resonator.hex
|
||||
|
||||
lilypad_resonator_isp: lilypad_resonator
|
||||
lilypad_resonator_isp: TARGET = lilypad_resonator
|
||||
lilypad_resonator_isp: HFUSE = DD
|
||||
lilypad_resonator_isp: LFUSE = C6
|
||||
lilypad_resonator_isp: EFUSE = 00
|
||||
lilypad_resonator_isp: isp
|
||||
|
||||
pro8: TARGET = pro_8MHz
|
||||
pro8: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>4' '-DNUM_LED_FLASHES=1' '-DWATCHDOG_MODS'
|
||||
pro8: AVR_FREQ = 8000000L
|
||||
pro8: $(PROGRAM)_pro_8MHz.hex
|
||||
|
||||
pro8_isp: pro8
|
||||
pro8_isp: TARGET = pro_8MHz
|
||||
pro8_isp: HFUSE = DD
|
||||
pro8_isp: LFUSE = C6
|
||||
pro8_isp: EFUSE = 00
|
||||
pro8_isp: isp
|
||||
|
||||
pro16: TARGET = pro_16MHz
|
||||
pro16: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>4' '-DNUM_LED_FLASHES=1' '-DWATCHDOG_MODS'
|
||||
pro16: AVR_FREQ = 16000000L
|
||||
pro16: $(PROGRAM)_pro_16MHz.hex
|
||||
|
||||
pro16_isp: pro16
|
||||
pro16_isp: TARGET = pro_16MHz
|
||||
pro16_isp: HFUSE = DD
|
||||
pro16_isp: LFUSE = C6
|
||||
pro16_isp: EFUSE = 00
|
||||
pro16_isp: isp
|
||||
|
||||
pro20: TARGET = pro_20mhz
|
||||
pro20: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>4' '-DNUM_LED_FLASHES=1' '-DWATCHDOG_MODS'
|
||||
pro20: AVR_FREQ = 20000000L
|
||||
pro20: $(PROGRAM)_pro_20mhz.hex
|
||||
|
||||
pro20_isp: pro20
|
||||
pro20_isp: TARGET = pro_20mhz
|
||||
pro20_isp: HFUSE = DD
|
||||
pro20_isp: LFUSE = C6
|
||||
pro20_isp: EFUSE = 00
|
||||
pro20_isp: isp
|
||||
|
||||
diecimila: TARGET = diecimila
|
||||
diecimila: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>4' '-DNUM_LED_FLASHES=1'
|
||||
diecimila: AVR_FREQ = 16000000L
|
||||
diecimila: $(PROGRAM)_diecimila.hex
|
||||
|
||||
diecimila_isp: diecimila
|
||||
diecimila_isp: TARGET = diecimila
|
||||
diecimila_isp: HFUSE = DD
|
||||
diecimila_isp: LFUSE = FF
|
||||
diecimila_isp: EFUSE = 00
|
||||
diecimila_isp: isp
|
||||
|
||||
ng: TARGET = ng
|
||||
ng: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>1' '-DNUM_LED_FLASHES=3'
|
||||
ng: AVR_FREQ = 16000000L
|
||||
ng: $(PROGRAM)_ng.hex
|
||||
|
||||
ng_isp: ng
|
||||
ng_isp: TARGET = ng
|
||||
ng_isp: HFUSE = DD
|
||||
ng_isp: LFUSE = FF
|
||||
ng_isp: EFUSE = 00
|
||||
ng_isp: isp
|
||||
|
||||
atmega328: TARGET = atmega328
|
||||
atmega328: MCU_TARGET = atmega328p
|
||||
atmega328: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>4' '-DNUM_LED_FLASHES=1' -DBAUD_RATE=57600
|
||||
atmega328: AVR_FREQ = 16000000L
|
||||
atmega328: LDSECTION = --section-start=.text=0x7800
|
||||
atmega328: $(PROGRAM)_atmega328.hex
|
||||
|
||||
atmega328_isp: atmega328
|
||||
atmega328_isp: TARGET = atmega328
|
||||
atmega328_isp: MCU_TARGET = atmega328p
|
||||
atmega328_isp: HFUSE = DA
|
||||
atmega328_isp: LFUSE = FF
|
||||
atmega328_isp: EFUSE = 05
|
||||
atmega328_isp: isp
|
||||
|
||||
atmega328_pro8: TARGET = atmega328_pro_8MHz
|
||||
atmega328_pro8: MCU_TARGET = atmega328p
|
||||
atmega328_pro8: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>4' '-DNUM_LED_FLASHES=1' -DBAUD_RATE=57600 -DDOUBLE_SPEED
|
||||
atmega328_pro8: AVR_FREQ = 8000000L
|
||||
atmega328_pro8: LDSECTION = --section-start=.text=0x7800
|
||||
atmega328_pro8: $(PROGRAM)_atmega328_pro_8MHz.hex
|
||||
|
||||
atmega328_pro8_isp: atmega328_pro8
|
||||
atmega328_pro8_isp: TARGET = atmega328_pro_8MHz
|
||||
atmega328_pro8_isp: MCU_TARGET = atmega328p
|
||||
atmega328_pro8_isp: HFUSE = DA
|
||||
atmega328_pro8_isp: LFUSE = FF
|
||||
atmega328_pro8_isp: EFUSE = 05
|
||||
atmega328_pro8_isp: isp
|
||||
|
||||
mega: TARGET = atmega1280
|
||||
mega: MCU_TARGET = atmega1280
|
||||
mega: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>4' '-DNUM_LED_FLASHES=0' -DBAUD_RATE=57600
|
||||
mega: AVR_FREQ = 16000000L
|
||||
mega: LDSECTION = --section-start=.text=0x1F000
|
||||
mega: $(PROGRAM)_atmega1280.hex
|
||||
|
||||
mega_isp: mega
|
||||
mega_isp: TARGET = atmega1280
|
||||
mega_isp: MCU_TARGET = atmega1280
|
||||
mega_isp: HFUSE = DA
|
||||
mega_isp: LFUSE = FF
|
||||
mega_isp: EFUSE = F5
|
||||
mega_isp: isp
|
||||
|
||||
isp: $(TARGET)
|
||||
$(ISPFUSES)
|
||||
$(ISPFLASH)
|
||||
|
||||
isp-stk500: $(PROGRAM)_$(TARGET).hex
|
||||
$(STK500-1)
|
||||
$(STK500-2)
|
||||
|
||||
%.elf: $(OBJ)
|
||||
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS)
|
||||
|
||||
clean:
|
||||
rm -rf *.o *.elf *.lst *.map *.sym *.lss *.eep *.srec *.bin *.hex
|
||||
|
||||
%.lst: %.elf
|
||||
$(OBJDUMP) -h -S $< > $@
|
||||
|
||||
%.hex: %.elf
|
||||
$(OBJCOPY) -j .text -j .data -O ihex $< $@
|
||||
|
||||
%.srec: %.elf
|
||||
$(OBJCOPY) -j .text -j .data -O srec $< $@
|
||||
|
||||
%.bin: %.elf
|
||||
$(OBJCOPY) -j .text -j .data -O binary $< $@
|
||||
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
/**********************************************************/
|
||||
/* Serial Bootloader for Atmel mega8 AVR Controller */
|
||||
/* */
|
||||
/* ATmegaBOOT.c */
|
||||
/* */
|
||||
/* Copyright (c) 2003, Jason P. Kyle */
|
||||
/* */
|
||||
/* Hacked by DojoCorp - ZGZ - MMX - IVR */
|
||||
/* Hacked by David A. Mellis */
|
||||
/* */
|
||||
/* This program is free software; you can redistribute it */
|
||||
/* and/or modify it under the terms of the GNU General */
|
||||
/* Public License as published by the Free Software */
|
||||
/* Foundation; either version 2 of the License, or */
|
||||
/* (at your option) any later version. */
|
||||
/* */
|
||||
/* This program is distributed in the hope that it will */
|
||||
/* be useful, but WITHOUT ANY WARRANTY; without even the */
|
||||
/* implied warranty of MERCHANTABILITY or FITNESS FOR A */
|
||||
/* PARTICULAR PURPOSE. See the GNU General Public */
|
||||
/* License for more details. */
|
||||
/* */
|
||||
/* You should have received a copy of the GNU General */
|
||||
/* Public License along with this program; if not, write */
|
||||
/* to the Free Software Foundation, Inc., */
|
||||
/* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
/* */
|
||||
/* Licence can be viewed at */
|
||||
/* http://www.fsf.org/licenses/gpl.txt */
|
||||
/* */
|
||||
/* Target = Atmel AVR m8 */
|
||||
/**********************************************************/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <avr/io.h>
|
||||
#include <avr/pgmspace.h>
|
||||
#include <avr/eeprom.h>
|
||||
#include <avr/interrupt.h>
|
||||
#include <avr/delay.h>
|
||||
|
||||
//#define F_CPU 16000000
|
||||
|
||||
/* We, Malmoitians, like slow interaction
|
||||
* therefore the slow baud rate ;-)
|
||||
*/
|
||||
//#define BAUD_RATE 9600
|
||||
|
||||
/* 6.000.000 is more or less 8 seconds at the
|
||||
* speed configured here
|
||||
*/
|
||||
//#define MAX_TIME_COUNT 6000000
|
||||
#define MAX_TIME_COUNT (F_CPU>>1)
|
||||
///#define MAX_TIME_COUNT_MORATORY 1600000
|
||||
|
||||
/* SW_MAJOR and MINOR needs to be updated from time to time to avoid warning message from AVR Studio */
|
||||
#define HW_VER 0x02
|
||||
#define SW_MAJOR 0x01
|
||||
#define SW_MINOR 0x12
|
||||
|
||||
// AVR-GCC compiler compatibility
|
||||
// avr-gcc compiler v3.1.x and older doesn't support outb() and inb()
|
||||
// if necessary, convert outb and inb to outp and inp
|
||||
#ifndef outb
|
||||
#define outb(sfr,val) (_SFR_BYTE(sfr) = (val))
|
||||
#endif
|
||||
#ifndef inb
|
||||
#define inb(sfr) _SFR_BYTE(sfr)
|
||||
#endif
|
||||
|
||||
/* defines for future compatibility */
|
||||
#ifndef cbi
|
||||
#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
|
||||
#endif
|
||||
#ifndef sbi
|
||||
#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
|
||||
#endif
|
||||
|
||||
/* Adjust to suit whatever pin your hardware uses to enter the bootloader */
|
||||
#define eeprom_rb(addr) eeprom_read_byte ((uint8_t *)(addr))
|
||||
#define eeprom_rw(addr) eeprom_read_word ((uint16_t *)(addr))
|
||||
#define eeprom_wb(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
|
||||
|
||||
/* Onboard LED is connected to pin PB5 */
|
||||
#define LED_DDR DDRB
|
||||
#define LED_PORT PORTB
|
||||
#define LED_PIN PINB
|
||||
#define LED PINB5
|
||||
|
||||
|
||||
#define SIG1 0x1E // Yep, Atmel is the only manufacturer of AVR micros. Single source :(
|
||||
#define SIG2 0x93
|
||||
#define SIG3 0x07
|
||||
#define PAGE_SIZE 0x20U //32 words
|
||||
|
||||
|
||||
void putch(char);
|
||||
char getch(void);
|
||||
void getNch(uint8_t);
|
||||
void byte_response(uint8_t);
|
||||
void nothing_response(void);
|
||||
|
||||
union address_union {
|
||||
uint16_t word;
|
||||
uint8_t byte[2];
|
||||
} address;
|
||||
|
||||
union length_union {
|
||||
uint16_t word;
|
||||
uint8_t byte[2];
|
||||
} length;
|
||||
|
||||
struct flags_struct {
|
||||
unsigned eeprom : 1;
|
||||
unsigned rampz : 1;
|
||||
} flags;
|
||||
|
||||
uint8_t buff[256];
|
||||
//uint8_t address_high;
|
||||
|
||||
uint8_t pagesz=0x80;
|
||||
|
||||
uint8_t i;
|
||||
//uint8_t bootuart0=0,bootuart1=0;
|
||||
|
||||
|
||||
void (*app_start)(void) = 0x0000;
|
||||
|
||||
int main(void)
|
||||
{
|
||||
uint8_t ch,ch2;
|
||||
uint16_t w;
|
||||
|
||||
//cbi(BL_DDR,BL);
|
||||
//sbi(BL_PORT,BL);
|
||||
|
||||
asm volatile("nop\n\t");
|
||||
|
||||
/* check if flash is programmed already, if not start bootloader anyway */
|
||||
//if(pgm_read_byte_near(0x0000) != 0xFF) {
|
||||
|
||||
/* check if bootloader pin is set low */
|
||||
//if(bit_is_set(BL_PIN,BL)) app_start();
|
||||
//}
|
||||
|
||||
/* initialize UART(s) depending on CPU defined */
|
||||
/* m8 */
|
||||
UBRRH = (((F_CPU/BAUD_RATE)/16)-1)>>8; // set baud rate
|
||||
UBRRL = (((F_CPU/BAUD_RATE)/16)-1);
|
||||
UCSRB = (1<<RXEN)|(1<<TXEN); // enable Rx & Tx
|
||||
UCSRC = (1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0); // config USART; 8N1
|
||||
|
||||
//UBRRL = (uint8_t)(F_CPU/(BAUD_RATE*16L)-1);
|
||||
//UBRRH = (F_CPU/(BAUD_RATE*16L)-1) >> 8;
|
||||
//UCSRA = 0x00;
|
||||
//UCSRC = 0x86;
|
||||
//UCSRB = _BV(TXEN)|_BV(RXEN);
|
||||
|
||||
|
||||
/* this was giving uisp problems, so I removed it; without it, the boot
|
||||
works on with uisp and avrdude on the mac (at least). */
|
||||
//putch('\0');
|
||||
|
||||
//uint32_t l;
|
||||
//uint32_t time_count;
|
||||
//time_count=0;
|
||||
|
||||
/* set LED pin as output */
|
||||
sbi(LED_DDR,LED);
|
||||
for (i = 0; i < 16; i++) {
|
||||
outb(LED_PORT, inb(LED_PORT) ^ _BV(LED));
|
||||
_delay_loop_2(0);
|
||||
}
|
||||
|
||||
//for (l=0; l<40000000; l++)
|
||||
//outb(LED_PORT, inb(LED_PORT) ^= _BV(LED));
|
||||
|
||||
/* flash onboard LED three times to signal entering of bootloader */
|
||||
//for(i=0; i<3; ++i) {
|
||||
//for(l=0; l<40000000; ++l);
|
||||
//sbi(LED_PORT,LED);
|
||||
//for(l=0; l<40000000; ++l);
|
||||
//cbi(LED_PORT,LED);
|
||||
//}
|
||||
|
||||
/* see comment at previous call to putch() */
|
||||
//putch('\0'); // this line is needed for the synchronization of the programmer
|
||||
|
||||
/* forever */
|
||||
for (;;) {
|
||||
//if((inb(UCSRA) & _BV(RXC))){
|
||||
/* get character from UART */
|
||||
ch = getch();
|
||||
|
||||
/* A bunch of if...else if... gives smaller code than switch...case ! */
|
||||
|
||||
/* Hello is anyone home ? */
|
||||
if(ch=='0') {
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
/* Request programmer ID */
|
||||
/* Not using PROGMEM string due to boot block in m128 being beyond 64kB boundry */
|
||||
/* Would need to selectively manipulate RAMPZ, and it's only 9 characters anyway so who cares. */
|
||||
else if(ch=='1') {
|
||||
if (getch() == ' ') {
|
||||
putch(0x14);
|
||||
putch('A');
|
||||
putch('V');
|
||||
putch('R');
|
||||
putch(' ');
|
||||
putch('I');
|
||||
putch('S');
|
||||
putch('P');
|
||||
putch(0x10);
|
||||
}
|
||||
}
|
||||
|
||||
/* AVR ISP/STK500 board commands DON'T CARE so default nothing_response */
|
||||
else if(ch=='@') {
|
||||
ch2 = getch();
|
||||
if (ch2>0x85) getch();
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
/* AVR ISP/STK500 board requests */
|
||||
else if(ch=='A') {
|
||||
ch2 = getch();
|
||||
if(ch2==0x80) byte_response(HW_VER); // Hardware version
|
||||
else if(ch2==0x81) byte_response(SW_MAJOR); // Software major version
|
||||
else if(ch2==0x82) byte_response(SW_MINOR); // Software minor version
|
||||
//else if(ch2==0x98) byte_response(0x03); // Unknown but seems to be required by avr studio 3.56
|
||||
else byte_response(0x00); // Covers various unnecessary responses we don't care about
|
||||
}
|
||||
|
||||
/* Device Parameters DON'T CARE, DEVICE IS FIXED */
|
||||
else if(ch=='B') {
|
||||
getNch(20);
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
/* Parallel programming stuff DON'T CARE */
|
||||
else if(ch=='E') {
|
||||
getNch(5);
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
/* Enter programming mode */
|
||||
else if(ch=='P') {
|
||||
nothing_response();
|
||||
// FIXME: modified only here by DojoCorp, Mumbai, India, 20050626
|
||||
//time_count=0; // exted the delay once entered prog.mode
|
||||
}
|
||||
|
||||
/* Leave programming mode */
|
||||
else if(ch=='Q') {
|
||||
nothing_response();
|
||||
//time_count=MAX_TIME_COUNT_MORATORY; // once the programming is done,
|
||||
// we should start the application
|
||||
// but uisp has problems with this,
|
||||
// therefore we just change the times
|
||||
// and give the programmer 1 sec to react
|
||||
}
|
||||
|
||||
/* Erase device, don't care as we will erase one page at a time anyway. */
|
||||
else if(ch=='R') {
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
/* Set address, little endian. EEPROM in bytes, FLASH in words */
|
||||
/* Perhaps extra address bytes may be added in future to support > 128kB FLASH. */
|
||||
/* This might explain why little endian was used here, big endian used everywhere else. */
|
||||
else if(ch=='U') {
|
||||
address.byte[0] = getch();
|
||||
address.byte[1] = getch();
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
/* Universal SPI programming command, disabled. Would be used for fuses and lock bits. */
|
||||
else if(ch=='V') {
|
||||
getNch(4);
|
||||
byte_response(0x00);
|
||||
}
|
||||
|
||||
/* Write memory, length is big endian and is in bytes */
|
||||
else if(ch=='d') {
|
||||
length.byte[1] = getch();
|
||||
length.byte[0] = getch();
|
||||
flags.eeprom = 0;
|
||||
if (getch() == 'E') flags.eeprom = 1;
|
||||
for (w=0;w<length.word;w++) {
|
||||
buff[w] = getch(); // Store data in buffer, can't keep up with serial data stream whilst programming pages
|
||||
}
|
||||
if (getch() == ' ') {
|
||||
if (flags.eeprom) { //Write to EEPROM one byte at a time
|
||||
for(w=0;w<length.word;w++) {
|
||||
eeprom_wb(address.word,buff[w]);
|
||||
address.word++;
|
||||
}
|
||||
} else { //Write to FLASH one page at a time
|
||||
//if (address.byte[1]>127) address_high = 0x01; //Only possible with m128, m256 will need 3rd address byte. FIXME
|
||||
//else address_high = 0x00;
|
||||
|
||||
//address.word = address.word << 1; //address * 2 -> byte location
|
||||
//if ((length.byte[0] & 0x01)) length.word++; //Even up an odd number of bytes
|
||||
cli(); //Disable interrupts, just to be sure
|
||||
while(bit_is_set(EECR,EEWE)); //Wait for previous EEPROM writes to complete
|
||||
asm volatile(
|
||||
"clr r17 \n\t" //page_word_count
|
||||
"lds r30,address \n\t" //Address of FLASH location (in words)
|
||||
"lds r31,address+1 \n\t"
|
||||
"lsl r30 \n\t" //address * 2 -> byte location
|
||||
"rol r31 \n\t"
|
||||
"ldi r28,lo8(buff) \n\t" //Start of buffer array in RAM
|
||||
"ldi r29,hi8(buff) \n\t"
|
||||
"lds r24,length \n\t" //Length of data to be written (in bytes)
|
||||
"lds r25,length+1 \n\t"
|
||||
"sbrs r24,0 \n\t" //Even up an odd number of bytes
|
||||
"rjmp length_loop \n\t"
|
||||
"adiw r24,1 \n\t"
|
||||
"length_loop: \n\t" //Main loop, repeat for number of words in block
|
||||
"cpi r17,0x00 \n\t" //If page_word_count=0 then erase page
|
||||
"brne no_page_erase \n\t"
|
||||
"rcall wait_spm \n\t"
|
||||
// "wait_spm1: \n\t"
|
||||
// "lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
// "andi r16,1 \n\t"
|
||||
// "cpi r16,1 \n\t"
|
||||
// "breq wait_spm1 \n\t"
|
||||
"ldi r16,0x03 \n\t" //Erase page pointed to by Z
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
"rcall wait_spm \n\t"
|
||||
// "wait_spm2: \n\t"
|
||||
// "lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
// "andi r16,1 \n\t"
|
||||
// "cpi r16,1 \n\t"
|
||||
// "breq wait_spm2 \n\t"
|
||||
"ldi r16,0x11 \n\t" //Re-enable RWW section
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
"no_page_erase: \n\t"
|
||||
"ld r0,Y+ \n\t" //Write 2 bytes into page buffer
|
||||
"ld r1,Y+ \n\t"
|
||||
|
||||
"rcall wait_spm \n\t"
|
||||
// "wait_spm3: \n\t"
|
||||
// "lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
// "andi r16,1 \n\t"
|
||||
// "cpi r16,1 \n\t"
|
||||
// "breq wait_spm3 \n\t"
|
||||
"ldi r16,0x01 \n\t" //Load r0,r1 into FLASH page buffer
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
|
||||
"inc r17 \n\t" //page_word_count++
|
||||
"cpi r17,%1 \n\t"
|
||||
"brlo same_page \n\t" //Still same page in FLASH
|
||||
"write_page: \n\t"
|
||||
"clr r17 \n\t" //New page, write current one first
|
||||
"rcall wait_spm \n\t"
|
||||
// "wait_spm4: \n\t"
|
||||
// "lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
// "andi r16,1 \n\t"
|
||||
// "cpi r16,1 \n\t"
|
||||
// "breq wait_spm4 \n\t"
|
||||
"ldi r16,0x05 \n\t" //Write page pointed to by Z
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
"rcall wait_spm \n\t"
|
||||
// "wait_spm5: \n\t"
|
||||
// "lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
// "andi r16,1 \n\t"
|
||||
// "cpi r16,1 \n\t"
|
||||
// "breq wait_spm5 \n\t"
|
||||
"ldi r16,0x11 \n\t" //Re-enable RWW section
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
"same_page: \n\t"
|
||||
"adiw r30,2 \n\t" //Next word in FLASH
|
||||
"sbiw r24,2 \n\t" //length-2
|
||||
"breq final_write \n\t" //Finished
|
||||
"rjmp length_loop \n\t"
|
||||
|
||||
"wait_spm: \n\t"
|
||||
"lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
"andi r16,1 \n\t"
|
||||
"cpi r16,1 \n\t"
|
||||
"breq wait_spm \n\t"
|
||||
"ret \n\t"
|
||||
|
||||
"final_write: \n\t"
|
||||
"cpi r17,0 \n\t"
|
||||
"breq block_done \n\t"
|
||||
"adiw r24,2 \n\t" //length+2, fool above check on length after short page write
|
||||
"rjmp write_page \n\t"
|
||||
"block_done: \n\t"
|
||||
"clr __zero_reg__ \n\t" //restore zero register
|
||||
: "=m" (SPMCR) : "M" (PAGE_SIZE) : "r0","r16","r17","r24","r25","r28","r29","r30","r31");
|
||||
|
||||
/* Should really add a wait for RWW section to be enabled, don't actually need it since we never */
|
||||
/* exit the bootloader without a power cycle anyhow */
|
||||
}
|
||||
putch(0x14);
|
||||
putch(0x10);
|
||||
}
|
||||
}
|
||||
|
||||
/* Read memory block mode, length is big endian. */
|
||||
else if(ch=='t') {
|
||||
length.byte[1] = getch();
|
||||
length.byte[0] = getch();
|
||||
if (getch() == 'E') flags.eeprom = 1;
|
||||
else {
|
||||
flags.eeprom = 0;
|
||||
address.word = address.word << 1; // address * 2 -> byte location
|
||||
}
|
||||
if (getch() == ' ') { // Command terminator
|
||||
putch(0x14);
|
||||
for (w=0;w < length.word;w++) { // Can handle odd and even lengths okay
|
||||
if (flags.eeprom) { // Byte access EEPROM read
|
||||
putch(eeprom_rb(address.word));
|
||||
address.word++;
|
||||
} else {
|
||||
if (!flags.rampz) putch(pgm_read_byte_near(address.word));
|
||||
address.word++;
|
||||
}
|
||||
}
|
||||
putch(0x10);
|
||||
}
|
||||
}
|
||||
|
||||
/* Get device signature bytes */
|
||||
else if(ch=='u') {
|
||||
if (getch() == ' ') {
|
||||
putch(0x14);
|
||||
putch(SIG1);
|
||||
putch(SIG2);
|
||||
putch(SIG3);
|
||||
putch(0x10);
|
||||
}
|
||||
}
|
||||
|
||||
/* Read oscillator calibration byte */
|
||||
else if(ch=='v') {
|
||||
byte_response(0x00);
|
||||
}
|
||||
// } else {
|
||||
// time_count++;
|
||||
// if (time_count>=MAX_TIME_COUNT) {
|
||||
// app_start();
|
||||
// }
|
||||
// }
|
||||
} /* end of forever loop */
|
||||
}
|
||||
|
||||
void putch(char ch)
|
||||
{
|
||||
/* m8 */
|
||||
while (!(inb(UCSRA) & _BV(UDRE)));
|
||||
outb(UDR,ch);
|
||||
}
|
||||
|
||||
char getch(void)
|
||||
{
|
||||
/* m8 */
|
||||
uint32_t count = 0;
|
||||
while(!(inb(UCSRA) & _BV(RXC))) {
|
||||
/* HACKME:: here is a good place to count times*/
|
||||
count++;
|
||||
if (count > MAX_TIME_COUNT)
|
||||
app_start();
|
||||
}
|
||||
return (inb(UDR));
|
||||
}
|
||||
|
||||
void getNch(uint8_t count)
|
||||
{
|
||||
uint8_t i;
|
||||
for(i=0;i<count;i++) {
|
||||
/* m8 */
|
||||
//while(!(inb(UCSRA) & _BV(RXC)));
|
||||
//inb(UDR);
|
||||
getch(); // need to handle time out
|
||||
}
|
||||
}
|
||||
|
||||
void byte_response(uint8_t val)
|
||||
{
|
||||
if (getch() == ' ') {
|
||||
putch(0x14);
|
||||
putch(val);
|
||||
putch(0x10);
|
||||
}
|
||||
}
|
||||
|
||||
void nothing_response(void)
|
||||
{
|
||||
if (getch() == ' ') {
|
||||
putch(0x14);
|
||||
putch(0x10);
|
||||
}
|
||||
}
|
||||
|
||||
/* end of file ATmegaBOOT.c */
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
:101C000012C02BC02AC029C028C027C026C025C0AA
|
||||
:101C100024C023C022C021C020C01FC01EC01DC0C0
|
||||
:101C20001CC01BC01AC011241FBECFE5D4E0DEBF0C
|
||||
:101C3000CDBF10E0A0E6B0E0E8EEFFE102C0059005
|
||||
:101C40000D92A236B107D9F711E0A2E6B0E001C0CB
|
||||
:101C50001D92AA36B107E1F74FC0D2CFEF92FF92A3
|
||||
:101C60000F931F93EE24FF24870113C00894E11CF7
|
||||
:101C7000F11C011D111D81E0E81682E1F8068AE7DA
|
||||
:101C8000080780E0180728F0E0916200F0916300F7
|
||||
:101C900009955F9BEBCF8CB1992787FD90951F919C
|
||||
:101CA0000F91FF90EF9008955D9BFECF8CB9089542
|
||||
:101CB000D5DF803221F484E1F7DF80E1F5DF08959C
|
||||
:101CC0001F93182FCBDF803231F484E1EDDF812FB9
|
||||
:101CD000EBDF80E1E9DF1F9108951F93CF93DF933E
|
||||
:101CE000182FC0E0D0E002C0B9DF2196C117E0F3A1
|
||||
:101CF000DF91CF911F910895CFE5D4E0DEBFCDBF36
|
||||
:101D0000000010BC83E389B988E18AB986E880BD08
|
||||
:101D1000BD9A1092680130E2E0E0F0E02FE088B375
|
||||
:101D2000832788BBCF010197F1F7215027FFF7CF19
|
||||
:101D300020E12093680192DF803381F1813399F4AF
|
||||
:101D40008DDF8032C1F784E1AFDF81E4ADDF86E56E
|
||||
:101D5000ABDF82E5A9DF80E2A7DF89E4A5DF83E5C9
|
||||
:101D6000A3DF80E5C7C0803429F478DF8638B0F07F
|
||||
:101D700075DF14C0813471F471DF803811F482E0B2
|
||||
:101D80001DC1813811F481E019C1823809F015C1F3
|
||||
:101D900082E114C1823421F484E19FDF89DFCBCF5B
|
||||
:101DA000853411F485E0F9CF8035C1F38135B1F385
|
||||
:101DB0008235A1F3853539F451DF809364004EDF1D
|
||||
:101DC00080936500EBCF863519F484E086DFF5C09B
|
||||
:101DD000843609F093C042DF809367013FDF809330
|
||||
:101DE0006601809169018E7F8093690137DF8534B8
|
||||
:101DF00029F480916901816080936901C0E0D0E09D
|
||||
:101E000006E610E005C02ADFF80181938F012196D4
|
||||
:101E10008091660190916701C817D907A0F31EDF72
|
||||
:101E2000803209F088CF8091690180FF1FC020E0D7
|
||||
:101E300030E0E6E6F0E012C0A0916400B0916500E9
|
||||
:101E40008191082EC5D08091640090916500019623
|
||||
:101E500090936500809364002F5F3F4F80916601EF
|
||||
:101E6000909167012817390738F343C0F894E19936
|
||||
:101E7000FECF1127E0916400F0916500EE0FFF1F87
|
||||
:101E8000C6E6D0E0809166019091670180FF01C0B5
|
||||
:101E90000196103051F422D003E000935700E895EA
|
||||
:101EA0001DD001E100935700E8950990199016D0D4
|
||||
:101EB00001E000935700E8951395103258F0112770
|
||||
:101EC0000DD005E000935700E89508D001E100939C
|
||||
:101ED0005700E8953296029739F0DBCF0091570012
|
||||
:101EE00001700130D9F30895103011F00296E7CF58
|
||||
:101EF000112484E1D9DE80E1D7DE1DCF843709F0DB
|
||||
:101F00004BC0ACDE80936701A9DE80936601A6DE3C
|
||||
:101F100090916901853421F49160909369010DC01D
|
||||
:101F20009E7F909369018091640090916500880F75
|
||||
:101F3000991F909365008093640090DE803209F0D1
|
||||
:101F4000FACE84E1B1DEC0E0D0E01EC0809169012C
|
||||
:101F500080FF07C0A0916400B091650031D0802D52
|
||||
:101F600008C081FD07C0E0916400F0916500E49134
|
||||
:101F70008E2F9ADE80916400909165000196909377
|
||||
:101F800065008093640021968091660190916701BD
|
||||
:101F9000C817D907D8F2AFCF853761F45FDE80323A
|
||||
:101FA00009F0C9CE84E180DE8EE17EDE83E97CDE4D
|
||||
:101FB00087E0A0CF863709F0BECE80E081DEBBCEC1
|
||||
:101FC000E199FECFBFBBAEBBE09A11960DB208956A
|
||||
:101FD000E199FECFBFBBAEBB0DBA11960FB6F89418
|
||||
:081FE000E29AE19A0FBE089598
|
||||
:021FE800800077
|
||||
:0400000300001C00DD
|
||||
:00000001FF
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
# Makefile for ATmegaBOOT
|
||||
# E.Lins, 2004-10-14
|
||||
|
||||
# program name should not be changed...
|
||||
PROGRAM = ATmegaBOOT
|
||||
|
||||
PRODUCT=atmega8
|
||||
|
||||
# enter the parameters for the UISP isp tool
|
||||
ISPPARAMS = -dprog=stk500 -dserial=$(SERIAL) -dspeed=115200
|
||||
|
||||
|
||||
#DIRAVR = /usr/local/avr
|
||||
DIRAVRBIN = $(DIRAVR)/bin
|
||||
DIRAVRUTILS = $(DIRAVR)/utils/bin
|
||||
DIRINC = $(DIRAVR)/include
|
||||
DIRLIB = $(DIRAVR)/avr/lib
|
||||
|
||||
|
||||
MCU_TARGET = atmega8
|
||||
LDSECTION = --section-start=.text=0x1c00
|
||||
FUSE_L = 0xdf
|
||||
FUSE_H = 0xca
|
||||
ISPFUSES = $(DIRAVRBIN)/uisp -dpart=ATmega8 $(ISPPARAMS) --wr_fuse_l=$(FUSE_L) --wr_fuse_h=$(FUSE_H)
|
||||
ISPFLASH = $(DIRAVRBIN)/uisp -dpart=ATmega8 $(ISPPARAMS) --erase --upload if=$(PROGRAM).hex -v
|
||||
|
||||
|
||||
OBJ = $(PROGRAM).o
|
||||
OPTIMIZE = -Os
|
||||
|
||||
DEFS = -DF_CPU=16000000 -DBAUD_RATE=19200
|
||||
LIBS =
|
||||
|
||||
CC = $(DIRAVRBIN)/avr-gcc
|
||||
|
||||
|
||||
# Override is only needed by avr-lib build system.
|
||||
|
||||
override CFLAGS = -g -Wall $(OPTIMIZE) -mmcu=$(MCU_TARGET) -D$(PRODUCT) $(DEFS) -I$(DIRINC)
|
||||
override LDFLAGS = -Wl,-Map,$(PROGRAM).map,$(LDSECTION)
|
||||
|
||||
OBJCOPY = $(DIRAVRBIN)/avr-objcopy
|
||||
OBJDUMP = $(DIRAVRBIN)/avr-objdump
|
||||
SIZE = $(DIRAVRBIN)/avr-size
|
||||
|
||||
all: $(PROGRAM).elf lst text asm size
|
||||
|
||||
isp: $(PROGRAM).hex
|
||||
$(ISPFUSES)
|
||||
$(ISPFLASH)
|
||||
|
||||
$(PROGRAM).elf: $(OBJ)
|
||||
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS)
|
||||
|
||||
clean:
|
||||
rm -rf *.s
|
||||
rm -rf *.o *.elf
|
||||
rm -rf *.lst *.map
|
||||
|
||||
asm: $(PROGRAM).s
|
||||
|
||||
%.s: %.c
|
||||
$(CC) -S $(CFLAGS) -g1 $^
|
||||
|
||||
lst: $(PROGRAM).lst
|
||||
|
||||
%.lst: %.elf
|
||||
$(OBJDUMP) -h -S $< > $@
|
||||
|
||||
size: $(PROGRAM).hex
|
||||
$(SIZE) $^
|
||||
|
||||
# Rules for building the .text rom images
|
||||
|
||||
text: hex bin srec
|
||||
|
||||
hex: $(PROGRAM).hex
|
||||
bin: $(PROGRAM).bin
|
||||
srec: $(PROGRAM).srec
|
||||
|
||||
%.hex: %.elf
|
||||
$(OBJCOPY) -j .text -j .data -O ihex $< $@
|
||||
|
||||
%.srec: %.elf
|
||||
$(OBJCOPY) -j .text -j .data -O srec $< $@
|
||||
|
||||
%.bin: %.elf
|
||||
$(OBJCOPY) -j .text -j .data -O binary $< $@
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,121 @@
|
|||
:103800000C94341C0C944F1C0C944F1C0C944F1CA7
|
||||
:103810000C944F1C0C944F1C0C944F1C0C944F1C7C
|
||||
:103820000C944F1C0C944F1C0C944F1C0C944F1C6C
|
||||
:103830000C944F1C0C944F1C0C944F1C0C944F1C5C
|
||||
:103840000C944F1C0C944F1C0C944F1C0C944F1C4C
|
||||
:103850000C944F1C0C944F1C0C944F1C0C944F1C3C
|
||||
:103860000C944F1C0C944F1C11241FBECFEFD4E0BE
|
||||
:10387000DEBFCDBF11E0A0E0B1E0E0E6FFE302C0B3
|
||||
:1038800005900D92A230B107D9F712E0A2E0B1E0A5
|
||||
:1038900001C01D92AC30B107E1F70C94D61C0C941A
|
||||
:1038A000001C882309F483E01092090290E0981725
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
|
|
@ -0,0 +1,117 @@
|
|||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:00000001FF
|
||||
|
|
@ -0,0 +1,979 @@
|
|||
/**********************************************************/
|
||||
/* Serial Bootloader for Atmel megaAVR Controllers */
|
||||
/* */
|
||||
/* tested with ATmega8, ATmega128 and ATmega168 */
|
||||
/* should work with other mega's, see code for details */
|
||||
/* */
|
||||
/* ATmegaBOOT.c */
|
||||
/* */
|
||||
/* 20070626: hacked for Arduino Diecimila (which auto- */
|
||||
/* resets when a USB connection is made to it) */
|
||||
/* by D. Mellis */
|
||||
/* 20060802: hacked for Arduino by D. Cuartielles */
|
||||
/* based on a previous hack by D. Mellis */
|
||||
/* and D. Cuartielles */
|
||||
/* */
|
||||
/* Monitor and debug functions were added to the original */
|
||||
/* code by Dr. Erik Lins, chip45.com. (See below) */
|
||||
/* */
|
||||
/* Thanks to Karl Pitrich for fixing a bootloader pin */
|
||||
/* problem and more informative LED blinking! */
|
||||
/* */
|
||||
/* For the latest version see: */
|
||||
/* http://www.chip45.com/ */
|
||||
/* */
|
||||
/* ------------------------------------------------------ */
|
||||
/* */
|
||||
/* based on stk500boot.c */
|
||||
/* Copyright (c) 2003, Jason P. Kyle */
|
||||
/* All rights reserved. */
|
||||
/* see avr1.org for original file and information */
|
||||
/* */
|
||||
/* This program is free software; you can redistribute it */
|
||||
/* and/or modify it under the terms of the GNU General */
|
||||
/* Public License as published by the Free Software */
|
||||
/* Foundation; either version 2 of the License, or */
|
||||
/* (at your option) any later version. */
|
||||
/* */
|
||||
/* This program is distributed in the hope that it will */
|
||||
/* be useful, but WITHOUT ANY WARRANTY; without even the */
|
||||
/* implied warranty of MERCHANTABILITY or FITNESS FOR A */
|
||||
/* PARTICULAR PURPOSE. See the GNU General Public */
|
||||
/* License for more details. */
|
||||
/* */
|
||||
/* You should have received a copy of the GNU General */
|
||||
/* Public License along with this program; if not, write */
|
||||
/* to the Free Software Foundation, Inc., */
|
||||
/* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
/* */
|
||||
/* Licence can be viewed at */
|
||||
/* http://www.fsf.org/licenses/gpl.txt */
|
||||
/* */
|
||||
/* Target = Atmel AVR m128,m64,m32,m16,m8,m162,m163,m169, */
|
||||
/* m8515,m8535. ATmega161 has a very small boot block so */
|
||||
/* isn't supported. */
|
||||
/* */
|
||||
/* Tested with m168 */
|
||||
/**********************************************************/
|
||||
|
||||
/* $Id$ */
|
||||
|
||||
|
||||
/* some includes */
|
||||
#include <inttypes.h>
|
||||
#include <avr/io.h>
|
||||
#include <avr/pgmspace.h>
|
||||
#include <avr/interrupt.h>
|
||||
#include <avr/wdt.h>
|
||||
|
||||
|
||||
/* the current avr-libc eeprom functions do not support the ATmega168 */
|
||||
/* own eeprom write/read functions are used instead */
|
||||
#ifndef __AVR_ATmega168__
|
||||
#include <avr/eeprom.h>
|
||||
#endif
|
||||
|
||||
/* Use the F_CPU defined in Makefile */
|
||||
|
||||
/* 20060803: hacked by DojoCorp */
|
||||
/* 20070626: hacked by David A. Mellis to decrease waiting time for auto-reset */
|
||||
/* set the waiting time for the bootloader */
|
||||
/* get this from the Makefile instead */
|
||||
/* #define MAX_TIME_COUNT (F_CPU>>4) */
|
||||
|
||||
/* 20070707: hacked by David A. Mellis - after this many errors give up and launch application */
|
||||
#define MAX_ERROR_COUNT 5
|
||||
|
||||
/* set the UART baud rate */
|
||||
/* 20060803: hacked by DojoCorp */
|
||||
//#define BAUD_RATE 115200
|
||||
#define BAUD_RATE 19200
|
||||
|
||||
|
||||
/* SW_MAJOR and MINOR needs to be updated from time to time to avoid warning message from AVR Studio */
|
||||
/* never allow AVR Studio to do an update !!!! */
|
||||
#define HW_VER 0x02
|
||||
#define SW_MAJOR 0x01
|
||||
#define SW_MINOR 0x10
|
||||
|
||||
|
||||
/* Adjust to suit whatever pin your hardware uses to enter the bootloader */
|
||||
/* ATmega128 has two UARTS so two pins are used to enter bootloader and select UART */
|
||||
/* BL0... means UART0, BL1... means UART1 */
|
||||
#ifdef __AVR_ATmega128__
|
||||
#define BL_DDR DDRF
|
||||
#define BL_PORT PORTF
|
||||
#define BL_PIN PINF
|
||||
#define BL0 PINF7
|
||||
#define BL1 PINF6
|
||||
#else
|
||||
/* other ATmegas have only one UART, so only one pin is defined to enter bootloader */
|
||||
#define BL_DDR DDRD
|
||||
#define BL_PORT PORTD
|
||||
#define BL_PIN PIND
|
||||
#define BL PIND6
|
||||
#endif
|
||||
|
||||
|
||||
/* onboard LED is used to indicate, that the bootloader was entered (3x flashing) */
|
||||
/* if monitor functions are included, LED goes on after monitor was entered */
|
||||
#ifdef __AVR_ATmega128__
|
||||
/* Onboard LED is connected to pin PB7 (e.g. Crumb128, PROBOmega128, Savvy128) */
|
||||
#define LED_DDR DDRB
|
||||
#define LED_PORT PORTB
|
||||
#define LED_PIN PINB
|
||||
#define LED PINB7
|
||||
#else
|
||||
/* Onboard LED is connected to pin PB2 (e.g. Crumb8, Crumb168) */
|
||||
#define LED_DDR DDRB
|
||||
#define LED_PORT PORTB
|
||||
#define LED_PIN PINB
|
||||
/* 20060803: hacked by DojoCorp, LED pin is B5 in Arduino */
|
||||
/* #define LED PINB2 */
|
||||
#define LED PINB5
|
||||
#endif
|
||||
|
||||
|
||||
/* monitor functions will only be compiled when using ATmega128, due to bootblock size constraints */
|
||||
#ifdef __AVR_ATmega128__
|
||||
#define MONITOR
|
||||
#endif
|
||||
|
||||
|
||||
/* define various device id's */
|
||||
/* manufacturer byte is always the same */
|
||||
#define SIG1 0x1E // Yep, Atmel is the only manufacturer of AVR micros. Single source :(
|
||||
|
||||
#if defined __AVR_ATmega128__
|
||||
#define SIG2 0x97
|
||||
#define SIG3 0x02
|
||||
#define PAGE_SIZE 0x80U //128 words
|
||||
|
||||
#elif defined __AVR_ATmega64__
|
||||
#define SIG2 0x96
|
||||
#define SIG3 0x02
|
||||
#define PAGE_SIZE 0x80U //128 words
|
||||
|
||||
#elif defined __AVR_ATmega32__
|
||||
#define SIG2 0x95
|
||||
#define SIG3 0x02
|
||||
#define PAGE_SIZE 0x40U //64 words
|
||||
|
||||
#elif defined __AVR_ATmega16__
|
||||
#define SIG2 0x94
|
||||
#define SIG3 0x03
|
||||
#define PAGE_SIZE 0x40U //64 words
|
||||
|
||||
#elif defined __AVR_ATmega8__
|
||||
#define SIG2 0x93
|
||||
#define SIG3 0x07
|
||||
#define PAGE_SIZE 0x20U //32 words
|
||||
|
||||
#elif defined __AVR_ATmega88__
|
||||
#define SIG2 0x93
|
||||
#define SIG3 0x0a
|
||||
#define PAGE_SIZE 0x20U //32 words
|
||||
|
||||
#elif defined __AVR_ATmega168__
|
||||
#define SIG2 0x94
|
||||
#define SIG3 0x06
|
||||
#define PAGE_SIZE 0x40U //64 words
|
||||
|
||||
#elif defined __AVR_ATmega162__
|
||||
#define SIG2 0x94
|
||||
#define SIG3 0x04
|
||||
#define PAGE_SIZE 0x40U //64 words
|
||||
|
||||
#elif defined __AVR_ATmega163__
|
||||
#define SIG2 0x94
|
||||
#define SIG3 0x02
|
||||
#define PAGE_SIZE 0x40U //64 words
|
||||
|
||||
#elif defined __AVR_ATmega169__
|
||||
#define SIG2 0x94
|
||||
#define SIG3 0x05
|
||||
#define PAGE_SIZE 0x40U //64 words
|
||||
|
||||
#elif defined __AVR_ATmega8515__
|
||||
#define SIG2 0x93
|
||||
#define SIG3 0x06
|
||||
#define PAGE_SIZE 0x20U //32 words
|
||||
|
||||
#elif defined __AVR_ATmega8535__
|
||||
#define SIG2 0x93
|
||||
#define SIG3 0x08
|
||||
#define PAGE_SIZE 0x20U //32 words
|
||||
#endif
|
||||
|
||||
|
||||
/* function prototypes */
|
||||
void putch(char);
|
||||
char getch(void);
|
||||
void getNch(uint8_t);
|
||||
void byte_response(uint8_t);
|
||||
void nothing_response(void);
|
||||
char gethex(void);
|
||||
void puthex(char);
|
||||
void flash_led(uint8_t);
|
||||
|
||||
/* some variables */
|
||||
union address_union {
|
||||
uint16_t word;
|
||||
uint8_t byte[2];
|
||||
} address;
|
||||
|
||||
union length_union {
|
||||
uint16_t word;
|
||||
uint8_t byte[2];
|
||||
} length;
|
||||
|
||||
struct flags_struct {
|
||||
unsigned eeprom : 1;
|
||||
unsigned rampz : 1;
|
||||
} flags;
|
||||
|
||||
uint8_t buff[256];
|
||||
uint8_t address_high;
|
||||
|
||||
uint8_t pagesz=0x80;
|
||||
|
||||
uint8_t i;
|
||||
uint8_t bootuart = 0;
|
||||
|
||||
uint8_t error_count = 0;
|
||||
|
||||
void (*app_start)(void) = 0x0000;
|
||||
|
||||
|
||||
/* main program starts here */
|
||||
int main(void)
|
||||
{
|
||||
uint8_t ch,ch2;
|
||||
uint16_t w;
|
||||
|
||||
asm volatile("nop\n\t");
|
||||
|
||||
/* set pin direction for bootloader pin and enable pullup */
|
||||
/* for ATmega128, two pins need to be initialized */
|
||||
#ifdef __AVR_ATmega128__
|
||||
BL_DDR &= ~_BV(BL0);
|
||||
BL_DDR &= ~_BV(BL1);
|
||||
BL_PORT |= _BV(BL0);
|
||||
BL_PORT |= _BV(BL1);
|
||||
#else
|
||||
/* We run the bootloader regardless of the state of this pin. Thus, don't
|
||||
put it in a different state than the other pins. --DAM, 070709
|
||||
BL_DDR &= ~_BV(BL);
|
||||
BL_PORT |= _BV(BL);
|
||||
*/
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __AVR_ATmega128__
|
||||
/* check which UART should be used for booting */
|
||||
if(bit_is_clear(BL_PIN, BL0)) {
|
||||
bootuart = 1;
|
||||
}
|
||||
else if(bit_is_clear(BL_PIN, BL1)) {
|
||||
bootuart = 2;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* check if flash is programmed already, if not start bootloader anyway */
|
||||
if(pgm_read_byte_near(0x0000) != 0xFF) {
|
||||
|
||||
#ifdef __AVR_ATmega128__
|
||||
/* no UART was selected, start application */
|
||||
if(!bootuart) {
|
||||
app_start();
|
||||
}
|
||||
#else
|
||||
/* check if bootloader pin is set low */
|
||||
/* we don't start this part neither for the m8, nor m168 */
|
||||
//if(bit_is_set(BL_PIN, BL)) {
|
||||
// app_start();
|
||||
// }
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __AVR_ATmega128__
|
||||
/* no bootuart was selected, default to uart 0 */
|
||||
if(!bootuart) {
|
||||
bootuart = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* initialize UART(s) depending on CPU defined */
|
||||
#ifdef __AVR_ATmega128__
|
||||
if(bootuart == 1) {
|
||||
UBRR0L = (uint8_t)(F_CPU/(BAUD_RATE*16L)-1);
|
||||
UBRR0H = (F_CPU/(BAUD_RATE*16L)-1) >> 8;
|
||||
UCSR0A = 0x00;
|
||||
UCSR0C = 0x06;
|
||||
UCSR0B = _BV(TXEN0)|_BV(RXEN0);
|
||||
}
|
||||
if(bootuart == 2) {
|
||||
UBRR1L = (uint8_t)(F_CPU/(BAUD_RATE*16L)-1);
|
||||
UBRR1H = (F_CPU/(BAUD_RATE*16L)-1) >> 8;
|
||||
UCSR1A = 0x00;
|
||||
UCSR1C = 0x06;
|
||||
UCSR1B = _BV(TXEN1)|_BV(RXEN1);
|
||||
}
|
||||
#elif defined __AVR_ATmega163__
|
||||
UBRR = (uint8_t)(F_CPU/(BAUD_RATE*16L)-1);
|
||||
UBRRHI = (F_CPU/(BAUD_RATE*16L)-1) >> 8;
|
||||
UCSRA = 0x00;
|
||||
UCSRB = _BV(TXEN)|_BV(RXEN);
|
||||
#elif defined __AVR_ATmega168__
|
||||
UBRR0L = (uint8_t)(F_CPU/(BAUD_RATE*16L)-1);
|
||||
UBRR0H = (F_CPU/(BAUD_RATE*16L)-1) >> 8;
|
||||
UCSR0B = (1<<RXEN0) | (1<<TXEN0);
|
||||
UCSR0C = (1<<UCSZ00) | (1<<UCSZ01);
|
||||
|
||||
/* Enable internal pull-up resistor on pin D0 (RX), in order
|
||||
to supress line noise that prevents the bootloader from
|
||||
timing out (DAM: 20070509) */
|
||||
DDRD &= ~_BV(PIND0);
|
||||
PORTD |= _BV(PIND0);
|
||||
#elif defined __AVR_ATmega8__
|
||||
/* m8 */
|
||||
UBRRH = (((F_CPU/BAUD_RATE)/16)-1)>>8; // set baud rate
|
||||
UBRRL = (((F_CPU/BAUD_RATE)/16)-1);
|
||||
UCSRB = (1<<RXEN)|(1<<TXEN); // enable Rx & Tx
|
||||
UCSRC = (1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0); // config USART; 8N1
|
||||
#else
|
||||
/* m16,m32,m169,m8515,m8535 */
|
||||
UBRRL = (uint8_t)(F_CPU/(BAUD_RATE*16L)-1);
|
||||
UBRRH = (F_CPU/(BAUD_RATE*16L)-1) >> 8;
|
||||
UCSRA = 0x00;
|
||||
UCSRC = 0x06;
|
||||
UCSRB = _BV(TXEN)|_BV(RXEN);
|
||||
#endif
|
||||
|
||||
/* set LED pin as output */
|
||||
LED_DDR |= _BV(LED);
|
||||
|
||||
|
||||
/* flash onboard LED to signal entering of bootloader */
|
||||
#ifdef __AVR_ATmega128__
|
||||
// 4x for UART0, 5x for UART1
|
||||
flash_led(NUM_LED_FLASHES + bootuart);
|
||||
#else
|
||||
flash_led(NUM_LED_FLASHES);
|
||||
#endif
|
||||
|
||||
/* 20050803: by DojoCorp, this is one of the parts provoking the
|
||||
system to stop listening, cancelled from the original */
|
||||
//putch('\0');
|
||||
|
||||
|
||||
/* forever loop */
|
||||
for (;;) {
|
||||
|
||||
/* get character from UART */
|
||||
ch = getch();
|
||||
|
||||
/* A bunch of if...else if... gives smaller code than switch...case ! */
|
||||
|
||||
/* Hello is anyone home ? */
|
||||
if(ch=='0') {
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
|
||||
/* Request programmer ID */
|
||||
/* Not using PROGMEM string due to boot block in m128 being beyond 64kB boundry */
|
||||
/* Would need to selectively manipulate RAMPZ, and it's only 9 characters anyway so who cares. */
|
||||
else if(ch=='1') {
|
||||
if (getch() == ' ') {
|
||||
putch(0x14);
|
||||
putch('A');
|
||||
putch('V');
|
||||
putch('R');
|
||||
putch(' ');
|
||||
putch('I');
|
||||
putch('S');
|
||||
putch('P');
|
||||
putch(0x10);
|
||||
} else {
|
||||
if (++error_count == MAX_ERROR_COUNT)
|
||||
app_start();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* AVR ISP/STK500 board commands DON'T CARE so default nothing_response */
|
||||
else if(ch=='@') {
|
||||
ch2 = getch();
|
||||
if (ch2>0x85) getch();
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
|
||||
/* AVR ISP/STK500 board requests */
|
||||
else if(ch=='A') {
|
||||
ch2 = getch();
|
||||
if(ch2==0x80) byte_response(HW_VER); // Hardware version
|
||||
else if(ch2==0x81) byte_response(SW_MAJOR); // Software major version
|
||||
else if(ch2==0x82) byte_response(SW_MINOR); // Software minor version
|
||||
else if(ch2==0x98) byte_response(0x03); // Unknown but seems to be required by avr studio 3.56
|
||||
else byte_response(0x00); // Covers various unnecessary responses we don't care about
|
||||
}
|
||||
|
||||
|
||||
/* Device Parameters DON'T CARE, DEVICE IS FIXED */
|
||||
else if(ch=='B') {
|
||||
getNch(20);
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
|
||||
/* Parallel programming stuff DON'T CARE */
|
||||
else if(ch=='E') {
|
||||
getNch(5);
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
|
||||
/* Enter programming mode */
|
||||
else if(ch=='P') {
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
|
||||
/* Leave programming mode */
|
||||
else if(ch=='Q') {
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
|
||||
/* Erase device, don't care as we will erase one page at a time anyway. */
|
||||
else if(ch=='R') {
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
|
||||
/* Set address, little endian. EEPROM in bytes, FLASH in words */
|
||||
/* Perhaps extra address bytes may be added in future to support > 128kB FLASH. */
|
||||
/* This might explain why little endian was used here, big endian used everywhere else. */
|
||||
else if(ch=='U') {
|
||||
address.byte[0] = getch();
|
||||
address.byte[1] = getch();
|
||||
nothing_response();
|
||||
}
|
||||
|
||||
|
||||
/* Universal SPI programming command, disabled. Would be used for fuses and lock bits. */
|
||||
else if(ch=='V') {
|
||||
getNch(4);
|
||||
byte_response(0x00);
|
||||
}
|
||||
|
||||
|
||||
/* Write memory, length is big endian and is in bytes */
|
||||
else if(ch=='d') {
|
||||
length.byte[1] = getch();
|
||||
length.byte[0] = getch();
|
||||
flags.eeprom = 0;
|
||||
if (getch() == 'E') flags.eeprom = 1;
|
||||
for (w=0;w<length.word;w++) {
|
||||
buff[w] = getch(); // Store data in buffer, can't keep up with serial data stream whilst programming pages
|
||||
}
|
||||
if (getch() == ' ') {
|
||||
if (flags.eeprom) { //Write to EEPROM one byte at a time
|
||||
for(w=0;w<length.word;w++) {
|
||||
#ifdef __AVR_ATmega168__
|
||||
while(EECR & (1<<EEPE));
|
||||
EEAR = (uint16_t)(void *)address.word;
|
||||
EEDR = buff[w];
|
||||
EECR |= (1<<EEMPE);
|
||||
EECR |= (1<<EEPE);
|
||||
#else
|
||||
eeprom_write_byte((void *)address.word,buff[w]);
|
||||
#endif
|
||||
address.word++;
|
||||
}
|
||||
}
|
||||
else { //Write to FLASH one page at a time
|
||||
if (address.byte[1]>127) address_high = 0x01; //Only possible with m128, m256 will need 3rd address byte. FIXME
|
||||
else address_high = 0x00;
|
||||
#ifdef __AVR_ATmega128__
|
||||
RAMPZ = address_high;
|
||||
#endif
|
||||
address.word = address.word << 1; //address * 2 -> byte location
|
||||
/* if ((length.byte[0] & 0x01) == 0x01) length.word++; //Even up an odd number of bytes */
|
||||
if ((length.byte[0] & 0x01)) length.word++; //Even up an odd number of bytes
|
||||
cli(); //Disable interrupts, just to be sure
|
||||
// HACKME: EEPE used to be EEWE
|
||||
while(bit_is_set(EECR,EEPE)); //Wait for previous EEPROM writes to complete
|
||||
asm volatile(
|
||||
"clr r17 \n\t" //page_word_count
|
||||
"lds r30,address \n\t" //Address of FLASH location (in bytes)
|
||||
"lds r31,address+1 \n\t"
|
||||
"ldi r28,lo8(buff) \n\t" //Start of buffer array in RAM
|
||||
"ldi r29,hi8(buff) \n\t"
|
||||
"lds r24,length \n\t" //Length of data to be written (in bytes)
|
||||
"lds r25,length+1 \n\t"
|
||||
"length_loop: \n\t" //Main loop, repeat for number of words in block
|
||||
"cpi r17,0x00 \n\t" //If page_word_count=0 then erase page
|
||||
"brne no_page_erase \n\t"
|
||||
"wait_spm1: \n\t"
|
||||
"lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
"andi r16,1 \n\t"
|
||||
"cpi r16,1 \n\t"
|
||||
"breq wait_spm1 \n\t"
|
||||
"ldi r16,0x03 \n\t" //Erase page pointed to by Z
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
#ifdef __AVR_ATmega163__
|
||||
".word 0xFFFF \n\t"
|
||||
"nop \n\t"
|
||||
#endif
|
||||
"wait_spm2: \n\t"
|
||||
"lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
"andi r16,1 \n\t"
|
||||
"cpi r16,1 \n\t"
|
||||
"breq wait_spm2 \n\t"
|
||||
|
||||
"ldi r16,0x11 \n\t" //Re-enable RWW section
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
#ifdef __AVR_ATmega163__
|
||||
".word 0xFFFF \n\t"
|
||||
"nop \n\t"
|
||||
#endif
|
||||
"no_page_erase: \n\t"
|
||||
"ld r0,Y+ \n\t" //Write 2 bytes into page buffer
|
||||
"ld r1,Y+ \n\t"
|
||||
|
||||
"wait_spm3: \n\t"
|
||||
"lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
"andi r16,1 \n\t"
|
||||
"cpi r16,1 \n\t"
|
||||
"breq wait_spm3 \n\t"
|
||||
"ldi r16,0x01 \n\t" //Load r0,r1 into FLASH page buffer
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
|
||||
"inc r17 \n\t" //page_word_count++
|
||||
"cpi r17,%1 \n\t"
|
||||
"brlo same_page \n\t" //Still same page in FLASH
|
||||
"write_page: \n\t"
|
||||
"clr r17 \n\t" //New page, write current one first
|
||||
"wait_spm4: \n\t"
|
||||
"lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
"andi r16,1 \n\t"
|
||||
"cpi r16,1 \n\t"
|
||||
"breq wait_spm4 \n\t"
|
||||
#ifdef __AVR_ATmega163__
|
||||
"andi r30,0x80 \n\t" // m163 requires Z6:Z1 to be zero during page write
|
||||
#endif
|
||||
"ldi r16,0x05 \n\t" //Write page pointed to by Z
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
#ifdef __AVR_ATmega163__
|
||||
".word 0xFFFF \n\t"
|
||||
"nop \n\t"
|
||||
"ori r30,0x7E \n\t" // recover Z6:Z1 state after page write (had to be zero during write)
|
||||
#endif
|
||||
"wait_spm5: \n\t"
|
||||
"lds r16,%0 \n\t" //Wait for previous spm to complete
|
||||
"andi r16,1 \n\t"
|
||||
"cpi r16,1 \n\t"
|
||||
"breq wait_spm5 \n\t"
|
||||
"ldi r16,0x11 \n\t" //Re-enable RWW section
|
||||
"sts %0,r16 \n\t"
|
||||
"spm \n\t"
|
||||
#ifdef __AVR_ATmega163__
|
||||
".word 0xFFFF \n\t"
|
||||
"nop \n\t"
|
||||
#endif
|
||||
"same_page: \n\t"
|
||||
"adiw r30,2 \n\t" //Next word in FLASH
|
||||
"sbiw r24,2 \n\t" //length-2
|
||||
"breq final_write \n\t" //Finished
|
||||
"rjmp length_loop \n\t"
|
||||
"final_write: \n\t"
|
||||
"cpi r17,0 \n\t"
|
||||
"breq block_done \n\t"
|
||||
"adiw r24,2 \n\t" //length+2, fool above check on length after short page write
|
||||
"rjmp write_page \n\t"
|
||||
"block_done: \n\t"
|
||||
"clr __zero_reg__ \n\t" //restore zero register
|
||||
#if defined __AVR_ATmega168__
|
||||
: "=m" (SPMCSR) : "M" (PAGE_SIZE) : "r0","r16","r17","r24","r25","r28","r29","r30","r31"
|
||||
#else
|
||||
: "=m" (SPMCR) : "M" (PAGE_SIZE) : "r0","r16","r17","r24","r25","r28","r29","r30","r31"
|
||||
#endif
|
||||
);
|
||||
/* Should really add a wait for RWW section to be enabled, don't actually need it since we never */
|
||||
/* exit the bootloader without a power cycle anyhow */
|
||||
}
|
||||
putch(0x14);
|
||||
putch(0x10);
|
||||
} else {
|
||||
if (++error_count == MAX_ERROR_COUNT)
|
||||
app_start();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Read memory block mode, length is big endian. */
|
||||
else if(ch=='t') {
|
||||
length.byte[1] = getch();
|
||||
length.byte[0] = getch();
|
||||
#if defined __AVR_ATmega128__
|
||||
if (address.word>0x7FFF) flags.rampz = 1; // No go with m256, FIXME
|
||||
else flags.rampz = 0;
|
||||
#endif
|
||||
if (getch() == 'E') flags.eeprom = 1;
|
||||
else {
|
||||
flags.eeprom = 0;
|
||||
address.word = address.word << 1; // address * 2 -> byte location
|
||||
}
|
||||
if (getch() == ' ') { // Command terminator
|
||||
putch(0x14);
|
||||
for (w=0;w < length.word;w++) { // Can handle odd and even lengths okay
|
||||
if (flags.eeprom) { // Byte access EEPROM read
|
||||
#ifdef __AVR_ATmega168__
|
||||
while(EECR & (1<<EEPE));
|
||||
EEAR = (uint16_t)(void *)address.word;
|
||||
EECR |= (1<<EERE);
|
||||
putch(EEDR);
|
||||
#else
|
||||
putch(eeprom_read_byte((void *)address.word));
|
||||
#endif
|
||||
address.word++;
|
||||
}
|
||||
else {
|
||||
|
||||
if (!flags.rampz) putch(pgm_read_byte_near(address.word));
|
||||
#if defined __AVR_ATmega128__
|
||||
else putch(pgm_read_byte_far(address.word + 0x10000));
|
||||
// Hmmmm, yuck FIXME when m256 arrvies
|
||||
#endif
|
||||
address.word++;
|
||||
}
|
||||
}
|
||||
putch(0x10);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Get device signature bytes */
|
||||
else if(ch=='u') {
|
||||
if (getch() == ' ') {
|
||||
putch(0x14);
|
||||
putch(SIG1);
|
||||
putch(SIG2);
|
||||
putch(SIG3);
|
||||
putch(0x10);
|
||||
} else {
|
||||
if (++error_count == MAX_ERROR_COUNT)
|
||||
app_start();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Read oscillator calibration byte */
|
||||
else if(ch=='v') {
|
||||
byte_response(0x00);
|
||||
}
|
||||
|
||||
|
||||
#ifdef MONITOR
|
||||
|
||||
/* here come the extended monitor commands by Erik Lins */
|
||||
|
||||
/* check for three times exclamation mark pressed */
|
||||
else if(ch=='!') {
|
||||
ch = getch();
|
||||
if(ch=='!') {
|
||||
ch = getch();
|
||||
if(ch=='!') {
|
||||
|
||||
#ifdef __AVR_ATmega128__
|
||||
uint16_t extaddr;
|
||||
#endif
|
||||
uint8_t addrl, addrh;
|
||||
|
||||
#ifdef CRUMB128
|
||||
PGM_P welcome = {"ATmegaBOOT / Crumb128 - (C) J.P.Kyle, E.Lins - 050815\n\r"};
|
||||
#elif defined PROBOMEGA128
|
||||
PGM_P welcome = {"ATmegaBOOT / PROBOmega128 - (C) J.P.Kyle, E.Lins - 050815\n\r"};
|
||||
#elif defined SAVVY128
|
||||
PGM_P welcome = {"ATmegaBOOT / Savvy128 - (C) J.P.Kyle, E.Lins - 050815\n\r"};
|
||||
#endif
|
||||
|
||||
/* turn on LED */
|
||||
LED_DDR |= _BV(LED);
|
||||
LED_PORT &= ~_BV(LED);
|
||||
|
||||
/* print a welcome message and command overview */
|
||||
for(i=0; welcome[i] != '\0'; ++i) {
|
||||
putch(welcome[i]);
|
||||
}
|
||||
|
||||
/* test for valid commands */
|
||||
for(;;) {
|
||||
putch('\n');
|
||||
putch('\r');
|
||||
putch(':');
|
||||
putch(' ');
|
||||
|
||||
ch = getch();
|
||||
putch(ch);
|
||||
|
||||
/* toggle LED */
|
||||
if(ch == 't') {
|
||||
if(bit_is_set(LED_PIN,LED)) {
|
||||
LED_PORT &= ~_BV(LED);
|
||||
putch('1');
|
||||
} else {
|
||||
LED_PORT |= _BV(LED);
|
||||
putch('0');
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* read byte from address */
|
||||
else if(ch == 'r') {
|
||||
ch = getch(); putch(ch);
|
||||
addrh = gethex();
|
||||
addrl = gethex();
|
||||
putch('=');
|
||||
ch = *(uint8_t *)((addrh << 8) + addrl);
|
||||
puthex(ch);
|
||||
}
|
||||
|
||||
/* write a byte to address */
|
||||
else if(ch == 'w') {
|
||||
ch = getch(); putch(ch);
|
||||
addrh = gethex();
|
||||
addrl = gethex();
|
||||
ch = getch(); putch(ch);
|
||||
ch = gethex();
|
||||
*(uint8_t *)((addrh << 8) + addrl) = ch;
|
||||
|
||||
}
|
||||
|
||||
/* read from uart and echo back */
|
||||
else if(ch == 'u') {
|
||||
for(;;) {
|
||||
putch(getch());
|
||||
}
|
||||
}
|
||||
#ifdef __AVR_ATmega128__
|
||||
/* external bus loop */
|
||||
else if(ch == 'b') {
|
||||
putch('b');
|
||||
putch('u');
|
||||
putch('s');
|
||||
MCUCR = 0x80;
|
||||
XMCRA = 0;
|
||||
XMCRB = 0;
|
||||
extaddr = 0x1100;
|
||||
for(;;) {
|
||||
ch = *(volatile uint8_t *)extaddr;
|
||||
if(++extaddr == 0) {
|
||||
extaddr = 0x1100;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
else if(ch == 'j') {
|
||||
app_start();
|
||||
}
|
||||
|
||||
}
|
||||
/* end of monitor functions */
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
/* end of monitor */
|
||||
#endif
|
||||
else if (++error_count == MAX_ERROR_COUNT) {
|
||||
app_start();
|
||||
}
|
||||
}
|
||||
/* end of forever loop */
|
||||
|
||||
}
|
||||
|
||||
|
||||
char gethex(void) {
|
||||
char ah,al;
|
||||
|
||||
ah = getch(); putch(ah);
|
||||
al = getch(); putch(al);
|
||||
if(ah >= 'a') {
|
||||
ah = ah - 'a' + 0x0a;
|
||||
} else if(ah >= '0') {
|
||||
ah -= '0';
|
||||
}
|
||||
if(al >= 'a') {
|
||||
al = al - 'a' + 0x0a;
|
||||
} else if(al >= '0') {
|
||||
al -= '0';
|
||||
}
|
||||
return (ah << 4) + al;
|
||||
}
|
||||
|
||||
|
||||
void puthex(char ch) {
|
||||
char ah,al;
|
||||
|
||||
ah = (ch & 0xf0) >> 4;
|
||||
if(ah >= 0x0a) {
|
||||
ah = ah - 0x0a + 'a';
|
||||
} else {
|
||||
ah += '0';
|
||||
}
|
||||
al = (ch & 0x0f);
|
||||
if(al >= 0x0a) {
|
||||
al = al - 0x0a + 'a';
|
||||
} else {
|
||||
al += '0';
|
||||
}
|
||||
putch(ah);
|
||||
putch(al);
|
||||
}
|
||||
|
||||
|
||||
void putch(char ch)
|
||||
{
|
||||
#ifdef __AVR_ATmega128__
|
||||
if(bootuart == 1) {
|
||||
while (!(UCSR0A & _BV(UDRE0)));
|
||||
UDR0 = ch;
|
||||
}
|
||||
else if (bootuart == 2) {
|
||||
while (!(UCSR1A & _BV(UDRE1)));
|
||||
UDR1 = ch;
|
||||
}
|
||||
#elif defined __AVR_ATmega168__
|
||||
while (!(UCSR0A & _BV(UDRE0)));
|
||||
UDR0 = ch;
|
||||
#else
|
||||
/* m8,16,32,169,8515,8535,163 */
|
||||
while (!(UCSRA & _BV(UDRE)));
|
||||
UDR = ch;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
char getch(void)
|
||||
{
|
||||
#ifdef __AVR_ATmega128__
|
||||
if(bootuart == 1) {
|
||||
while(!(UCSR0A & _BV(RXC0)));
|
||||
return UDR0;
|
||||
}
|
||||
else if(bootuart == 2) {
|
||||
while(!(UCSR1A & _BV(RXC1)));
|
||||
return UDR1;
|
||||
}
|
||||
return 0;
|
||||
#elif defined __AVR_ATmega168__
|
||||
uint32_t count = 0;
|
||||
while(!(UCSR0A & _BV(RXC0))){
|
||||
/* 20060803 DojoCorp:: Addon coming from the previous Bootloader*/
|
||||
/* HACKME:: here is a good place to count times*/
|
||||
count++;
|
||||
if (count > MAX_TIME_COUNT)
|
||||
app_start();
|
||||
}
|
||||
return UDR0;
|
||||
#else
|
||||
/* m8,16,32,169,8515,8535,163 */
|
||||
uint32_t count = 0;
|
||||
while(!(UCSRA & _BV(RXC))){
|
||||
/* 20060803 DojoCorp:: Addon coming from the previous Bootloader*/
|
||||
/* HACKME:: here is a good place to count times*/
|
||||
count++;
|
||||
if (count > MAX_TIME_COUNT)
|
||||
app_start();
|
||||
}
|
||||
return UDR;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void getNch(uint8_t count)
|
||||
{
|
||||
uint8_t i;
|
||||
for(i=0;i<count;i++) {
|
||||
#ifdef __AVR_ATmega128__
|
||||
if(bootuart == 1) {
|
||||
while(!(UCSR0A & _BV(RXC0)));
|
||||
UDR0;
|
||||
}
|
||||
else if(bootuart == 2) {
|
||||
while(!(UCSR1A & _BV(RXC1)));
|
||||
UDR1;
|
||||
}
|
||||
#elif defined __AVR_ATmega168__
|
||||
while(!(UCSR0A & _BV(RXC0)));
|
||||
UDR0;
|
||||
#else
|
||||
/* m8,16,32,169,8515,8535,163 */
|
||||
/* 20060803 DojoCorp:: Addon coming from the previous Bootloader*/
|
||||
//while(!(UCSRA & _BV(RXC)));
|
||||
//UDR;
|
||||
uint8_t i;
|
||||
for(i=0;i<count;i++) {
|
||||
getch(); // need to handle time out
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void byte_response(uint8_t val)
|
||||
{
|
||||
if (getch() == ' ') {
|
||||
putch(0x14);
|
||||
putch(val);
|
||||
putch(0x10);
|
||||
} else {
|
||||
if (++error_count == MAX_ERROR_COUNT)
|
||||
app_start();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void nothing_response(void)
|
||||
{
|
||||
if (getch() == ' ') {
|
||||
putch(0x14);
|
||||
putch(0x10);
|
||||
} else {
|
||||
if (++error_count == MAX_ERROR_COUNT)
|
||||
app_start();
|
||||
}
|
||||
}
|
||||
|
||||
void flash_led(uint8_t count)
|
||||
{
|
||||
/* flash onboard LED three times to signal entering of bootloader */
|
||||
/* l needs to be volatile or the delay loops below might get
|
||||
optimized away if compiling with optimizations (DAM). */
|
||||
volatile uint32_t l;
|
||||
|
||||
if (count == 0) {
|
||||
count = 3;
|
||||
}
|
||||
|
||||
for (i = 0; i < count; ++i) {
|
||||
LED_PORT |= _BV(LED);
|
||||
for(l = 0; l < (F_CPU / 1000); ++l);
|
||||
LED_PORT &= ~_BV(LED);
|
||||
for(l = 0; l < (F_CPU / 1000); ++l);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* end of file ATmegaBOOT.c */
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
# Makefile for ATmegaBOOT
|
||||
# E.Lins, 18.7.2005
|
||||
# $Id$
|
||||
|
||||
# Instructions
|
||||
#
|
||||
# To build the bootloader for the LilyPad:
|
||||
# make lily
|
||||
|
||||
|
||||
# program name should not be changed...
|
||||
PROGRAM = ATmegaBOOT_168
|
||||
|
||||
# enter the target CPU frequency
|
||||
AVR_FREQ = 8000000L
|
||||
|
||||
# enter the parameters for the avrdude isp tool
|
||||
ISPTOOL = stk500v2
|
||||
ISPPORT = usb
|
||||
ISPSPEED = -b 115200
|
||||
|
||||
MCU_TARGET = atmega168
|
||||
LDSECTION = --section-start=.text=0x3800
|
||||
|
||||
# the efuse should really be 0xf8; since, however, only the lower
|
||||
# three bits of that byte are used on the atmega168, avrdude gets
|
||||
# confused if you specify 1's for the higher bits, see:
|
||||
# http://tinker.it/now/2007/02/24/the-tale-of-avrdude-atmega168-and-extended-bits-fuses/
|
||||
#
|
||||
# similarly, the lock bits should be 0xff instead of 0x3f (to
|
||||
# unlock the bootloader section) and 0xcf instead of 0x0f (to
|
||||
# lock it), but since the high two bits of the lock byte are
|
||||
# unused, avrdude would get confused.
|
||||
ISPFUSES = avrdude -c $(ISPTOOL) -p m168 -P $(ISPPORT) $(ISPSPEED) -e -u -U lock:w:0x3f:m -U efuse:w:0x00:m -U hfuse:w:0xdd:m -U lfuse:w:0xff:m
|
||||
ISPFLASH = avrdude -c $(ISPTOOL) -p m168 -P $(ISPPORT) $(ISPSPEED) -U flash:w:$(PROGRAM)_$(TARGET).hex -U lock:w:0x0f:m
|
||||
|
||||
|
||||
OBJ = $(PROGRAM).o
|
||||
OPTIMIZE = -O2
|
||||
|
||||
DEFS =
|
||||
LIBS =
|
||||
|
||||
CC = avr-gcc
|
||||
|
||||
|
||||
# Override is only needed by avr-lib build system.
|
||||
|
||||
override CFLAGS = -g -Wall $(OPTIMIZE) -mmcu=$(MCU_TARGET) -DF_CPU=$(AVR_FREQ) $(DEFS)
|
||||
override LDFLAGS = -Wl,$(LDSECTION)
|
||||
#override LDFLAGS = -Wl,-Map,$(PROGRAM).map,$(LDSECTION)
|
||||
|
||||
OBJCOPY = avr-objcopy
|
||||
OBJDUMP = avr-objdump
|
||||
|
||||
all:
|
||||
|
||||
lily: CFLAGS += '-DMAX_TIME_COUNT=F_CPU>>1' '-DNUM_LED_FLASHES=3'
|
||||
lily: $(PROGRAM).hex
|
||||
|
||||
$(PROGRAM).hex: $(PROGRAM).elf
|
||||
$(OBJCOPY) -j .text -j .data -O ihex $< $@
|
||||
|
||||
$(PROGRAM).elf: $(OBJ)
|
||||
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS)
|
||||
|
||||
$(OBJ):
|
||||
avr-gcc $(CFLAGS) $(LDFLAGS) -c -g -O2 -Wall -mmcu=atmega168 ATmegaBOOT.c -o ATmegaBOOT_168.o
|
||||
|
||||
%.lst: %.elf
|
||||
$(OBJDUMP) -h -S $< > $@
|
||||
|
||||
%.srec: %.elf
|
||||
$(OBJCOPY) -j .text -j .data -O srec $< $@
|
||||
|
||||
%.bin: %.elf
|
||||
$(OBJCOPY) -j .text -j .data -O binary $< $@
|
||||
|
||||
clean:
|
||||
rm -rf *.o *.elf *.lst *.map *.sym *.lss *.eep *.srec *.bin *.hex
|
||||
|
||||
install:
|
||||
avrdude -p m168 -c stk500v2 -P /dev/cu.USA19H1b1P1.1 -e -u -U lock:w:0x3f:m -U efuse:w:0x00:m -U hfuse:w:0xdd:m -U lfuse:w:0xe2:m
|
||||
avrdude -p m168 -c stk500v2 -P /dev/cu.USA19H1b1P1.1 -e -u -U flash:w:ATmegaBOOT_168.hex -U lock:w:0x0f:m
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
/*
|
||||
HardwareSerial.cpp - Hardware serial library for Wiring
|
||||
Copyright (c) 2006 Nicholas Zambetti. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
Modified 23 November 2006 by David A. Mellis
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <inttypes.h>
|
||||
#include "wiring.h"
|
||||
#include "wiring_private.h"
|
||||
|
||||
#include "HardwareSerial.h"
|
||||
|
||||
// Define constants and variables for buffering incoming serial data. We're
|
||||
// using a ring buffer (I think), in which rx_buffer_head is the index of the
|
||||
// location to which to write the next incoming character and rx_buffer_tail
|
||||
// is the index of the location from which to read.
|
||||
#define RX_BUFFER_SIZE 128
|
||||
|
||||
struct ring_buffer {
|
||||
unsigned char buffer[RX_BUFFER_SIZE];
|
||||
int head;
|
||||
int tail;
|
||||
};
|
||||
|
||||
ring_buffer rx_buffer = { { 0 }, 0, 0 };
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
ring_buffer rx_buffer1 = { { 0 }, 0, 0 };
|
||||
ring_buffer rx_buffer2 = { { 0 }, 0, 0 };
|
||||
ring_buffer rx_buffer3 = { { 0 }, 0, 0 };
|
||||
#endif
|
||||
|
||||
inline void store_char(unsigned char c, ring_buffer *rx_buffer)
|
||||
{
|
||||
int i = (rx_buffer->head + 1) % RX_BUFFER_SIZE;
|
||||
|
||||
// if we should be storing the received character into the location
|
||||
// just before the tail (meaning that the head would advance to the
|
||||
// current location of the tail), we're about to overflow the buffer
|
||||
// and so we don't write the character or advance the head.
|
||||
if (i != rx_buffer->tail) {
|
||||
rx_buffer->buffer[rx_buffer->head] = c;
|
||||
rx_buffer->head = i;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
|
||||
SIGNAL(SIG_USART0_RECV)
|
||||
{
|
||||
unsigned char c = UDR0;
|
||||
store_char(c, &rx_buffer);
|
||||
}
|
||||
|
||||
SIGNAL(SIG_USART1_RECV)
|
||||
{
|
||||
unsigned char c = UDR1;
|
||||
store_char(c, &rx_buffer1);
|
||||
}
|
||||
|
||||
SIGNAL(SIG_USART2_RECV)
|
||||
{
|
||||
unsigned char c = UDR2;
|
||||
store_char(c, &rx_buffer2);
|
||||
}
|
||||
|
||||
SIGNAL(SIG_USART3_RECV)
|
||||
{
|
||||
unsigned char c = UDR3;
|
||||
store_char(c, &rx_buffer3);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#if defined(__AVR_ATmega8__)
|
||||
SIGNAL(SIG_UART_RECV)
|
||||
#else
|
||||
SIGNAL(USART_RX_vect)
|
||||
#endif
|
||||
{
|
||||
#if defined(__AVR_ATmega8__)
|
||||
unsigned char c = UDR;
|
||||
#else
|
||||
unsigned char c = UDR0;
|
||||
#endif
|
||||
store_char(c, &rx_buffer);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
// Constructors ////////////////////////////////////////////////////////////////
|
||||
|
||||
HardwareSerial::HardwareSerial(ring_buffer *rx_buffer,
|
||||
volatile uint8_t *ubrrh, volatile uint8_t *ubrrl,
|
||||
volatile uint8_t *ucsra, volatile uint8_t *ucsrb,
|
||||
volatile uint8_t *udr,
|
||||
uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udre, uint8_t u2x)
|
||||
{
|
||||
_rx_buffer = rx_buffer;
|
||||
_ubrrh = ubrrh;
|
||||
_ubrrl = ubrrl;
|
||||
_ucsra = ucsra;
|
||||
_ucsrb = ucsrb;
|
||||
_udr = udr;
|
||||
_rxen = rxen;
|
||||
_txen = txen;
|
||||
_rxcie = rxcie;
|
||||
_udre = udre;
|
||||
_u2x = u2x;
|
||||
}
|
||||
|
||||
// Public Methods //////////////////////////////////////////////////////////////
|
||||
|
||||
void HardwareSerial::begin(long baud)
|
||||
{
|
||||
uint16_t baud_setting;
|
||||
bool use_u2x;
|
||||
|
||||
// U2X mode is needed for baud rates higher than (CPU Hz / 16)
|
||||
if (baud > F_CPU / 16) {
|
||||
use_u2x = true;
|
||||
} else {
|
||||
// figure out if U2X mode would allow for a better connection
|
||||
|
||||
// calculate the percent difference between the baud-rate specified and
|
||||
// the real baud rate for both U2X and non-U2X mode (0-255 error percent)
|
||||
uint8_t nonu2x_baud_error = abs((int)(255-((F_CPU/(16*(((F_CPU/8/baud-1)/2)+1))*255)/baud)));
|
||||
uint8_t u2x_baud_error = abs((int)(255-((F_CPU/(8*(((F_CPU/4/baud-1)/2)+1))*255)/baud)));
|
||||
|
||||
// prefer non-U2X mode because it handles clock skew better
|
||||
use_u2x = (nonu2x_baud_error > u2x_baud_error);
|
||||
}
|
||||
|
||||
if (use_u2x) {
|
||||
*_ucsra = 1 << _u2x;
|
||||
baud_setting = (F_CPU / 4 / baud - 1) / 2;
|
||||
} else {
|
||||
*_ucsra = 0;
|
||||
baud_setting = (F_CPU / 8 / baud - 1) / 2;
|
||||
}
|
||||
|
||||
// assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register)
|
||||
*_ubrrh = baud_setting >> 8;
|
||||
*_ubrrl = baud_setting;
|
||||
|
||||
sbi(*_ucsrb, _rxen);
|
||||
sbi(*_ucsrb, _txen);
|
||||
sbi(*_ucsrb, _rxcie);
|
||||
}
|
||||
|
||||
void HardwareSerial::end()
|
||||
{
|
||||
cbi(*_ucsrb, _rxen);
|
||||
cbi(*_ucsrb, _txen);
|
||||
cbi(*_ucsrb, _rxcie);
|
||||
}
|
||||
|
||||
uint8_t HardwareSerial::available(void)
|
||||
{
|
||||
return (RX_BUFFER_SIZE + _rx_buffer->head - _rx_buffer->tail) % RX_BUFFER_SIZE;
|
||||
}
|
||||
|
||||
int HardwareSerial::read(void)
|
||||
{
|
||||
// if the head isn't ahead of the tail, we don't have any characters
|
||||
if (_rx_buffer->head == _rx_buffer->tail) {
|
||||
return -1;
|
||||
} else {
|
||||
unsigned char c = _rx_buffer->buffer[_rx_buffer->tail];
|
||||
_rx_buffer->tail = (_rx_buffer->tail + 1) % RX_BUFFER_SIZE;
|
||||
return c;
|
||||
}
|
||||
}
|
||||
|
||||
void HardwareSerial::flush()
|
||||
{
|
||||
// don't reverse this or there may be problems if the RX interrupt
|
||||
// occurs after reading the value of rx_buffer_head but before writing
|
||||
// the value to rx_buffer_tail; the previous value of rx_buffer_head
|
||||
// may be written to rx_buffer_tail, making it appear as if the buffer
|
||||
// don't reverse this or there may be problems if the RX interrupt
|
||||
// occurs after reading the value of rx_buffer_head but before writing
|
||||
// the value to rx_buffer_tail; the previous value of rx_buffer_head
|
||||
// may be written to rx_buffer_tail, making it appear as if the buffer
|
||||
// were full, not empty.
|
||||
_rx_buffer->head = _rx_buffer->tail;
|
||||
}
|
||||
|
||||
void HardwareSerial::write(uint8_t c)
|
||||
{
|
||||
while (!((*_ucsra) & (1 << _udre)))
|
||||
;
|
||||
|
||||
*_udr = c;
|
||||
}
|
||||
|
||||
// Preinstantiate Objects //////////////////////////////////////////////////////
|
||||
|
||||
#if defined(__AVR_ATmega8__)
|
||||
HardwareSerial Serial(&rx_buffer, &UBRRH, &UBRRL, &UCSRA, &UCSRB, &UDR, RXEN, TXEN, RXCIE, UDRE, U2X);
|
||||
#else
|
||||
HardwareSerial Serial(&rx_buffer, &UBRR0H, &UBRR0L, &UCSR0A, &UCSR0B, &UDR0, RXEN0, TXEN0, RXCIE0, UDRE0, U2X0);
|
||||
#endif
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
HardwareSerial Serial1(&rx_buffer1, &UBRR1H, &UBRR1L, &UCSR1A, &UCSR1B, &UDR1, RXEN1, TXEN1, RXCIE1, UDRE1, U2X1);
|
||||
HardwareSerial Serial2(&rx_buffer2, &UBRR2H, &UBRR2L, &UCSR2A, &UCSR2B, &UDR2, RXEN2, TXEN2, RXCIE2, UDRE2, U2X2);
|
||||
HardwareSerial Serial3(&rx_buffer3, &UBRR3H, &UBRR3L, &UCSR3A, &UCSR3B, &UDR3, RXEN3, TXEN3, RXCIE3, UDRE3, U2X3);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
HardwareSerial.h - Hardware serial library for Wiring
|
||||
Copyright (c) 2006 Nicholas Zambetti. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef HardwareSerial_h
|
||||
#define HardwareSerial_h
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "Print.h"
|
||||
|
||||
struct ring_buffer;
|
||||
|
||||
class HardwareSerial : public Print
|
||||
{
|
||||
private:
|
||||
ring_buffer *_rx_buffer;
|
||||
volatile uint8_t *_ubrrh;
|
||||
volatile uint8_t *_ubrrl;
|
||||
volatile uint8_t *_ucsra;
|
||||
volatile uint8_t *_ucsrb;
|
||||
volatile uint8_t *_udr;
|
||||
uint8_t _rxen;
|
||||
uint8_t _txen;
|
||||
uint8_t _rxcie;
|
||||
uint8_t _udre;
|
||||
uint8_t _u2x;
|
||||
public:
|
||||
HardwareSerial(ring_buffer *rx_buffer,
|
||||
volatile uint8_t *ubrrh, volatile uint8_t *ubrrl,
|
||||
volatile uint8_t *ucsra, volatile uint8_t *ucsrb,
|
||||
volatile uint8_t *udr,
|
||||
uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udre, uint8_t u2x);
|
||||
void begin(long);
|
||||
void end();
|
||||
uint8_t available(void);
|
||||
int read(void);
|
||||
void flush(void);
|
||||
virtual void write(uint8_t);
|
||||
using Print::write; // pull in write(str) and write(buf, size) from Print
|
||||
};
|
||||
|
||||
extern HardwareSerial Serial;
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
extern HardwareSerial Serial1;
|
||||
extern HardwareSerial Serial2;
|
||||
extern HardwareSerial Serial3;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
206
arduino-0018-windows/hardware/arduino/cores/arduino/Print.cpp
Normal file
206
arduino-0018-windows/hardware/arduino/cores/arduino/Print.cpp
Normal file
|
|
@ -0,0 +1,206 @@
|
|||
/*
|
||||
Print.cpp - Base class that provides print() and println()
|
||||
Copyright (c) 2008 David A. Mellis. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
Modified 23 November 2006 by David A. Mellis
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#include "wiring.h"
|
||||
|
||||
#include "Print.h"
|
||||
|
||||
// Public Methods //////////////////////////////////////////////////////////////
|
||||
|
||||
/* default implementation: may be overridden */
|
||||
void Print::write(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
write(*str++);
|
||||
}
|
||||
|
||||
/* default implementation: may be overridden */
|
||||
void Print::write(const uint8_t *buffer, size_t size)
|
||||
{
|
||||
while (size--)
|
||||
write(*buffer++);
|
||||
}
|
||||
|
||||
void Print::print(const char str[])
|
||||
{
|
||||
write(str);
|
||||
}
|
||||
|
||||
void Print::print(char c, int base)
|
||||
{
|
||||
print((long) c, base);
|
||||
}
|
||||
|
||||
void Print::print(unsigned char b, int base)
|
||||
{
|
||||
print((unsigned long) b, base);
|
||||
}
|
||||
|
||||
void Print::print(int n, int base)
|
||||
{
|
||||
print((long) n, base);
|
||||
}
|
||||
|
||||
void Print::print(unsigned int n, int base)
|
||||
{
|
||||
print((unsigned long) n, base);
|
||||
}
|
||||
|
||||
void Print::print(long n, int base)
|
||||
{
|
||||
if (base == 0) {
|
||||
write(n);
|
||||
} else if (base == 10) {
|
||||
if (n < 0) {
|
||||
print('-');
|
||||
n = -n;
|
||||
}
|
||||
printNumber(n, 10);
|
||||
} else {
|
||||
printNumber(n, base);
|
||||
}
|
||||
}
|
||||
|
||||
void Print::print(unsigned long n, int base)
|
||||
{
|
||||
if (base == 0) write(n);
|
||||
else printNumber(n, base);
|
||||
}
|
||||
|
||||
void Print::print(double n, int digits)
|
||||
{
|
||||
printFloat(n, digits);
|
||||
}
|
||||
|
||||
void Print::println(void)
|
||||
{
|
||||
print('\r');
|
||||
print('\n');
|
||||
}
|
||||
|
||||
void Print::println(const char c[])
|
||||
{
|
||||
print(c);
|
||||
println();
|
||||
}
|
||||
|
||||
void Print::println(char c, int base)
|
||||
{
|
||||
print(c, base);
|
||||
println();
|
||||
}
|
||||
|
||||
void Print::println(unsigned char b, int base)
|
||||
{
|
||||
print(b, base);
|
||||
println();
|
||||
}
|
||||
|
||||
void Print::println(int n, int base)
|
||||
{
|
||||
print(n, base);
|
||||
println();
|
||||
}
|
||||
|
||||
void Print::println(unsigned int n, int base)
|
||||
{
|
||||
print(n, base);
|
||||
println();
|
||||
}
|
||||
|
||||
void Print::println(long n, int base)
|
||||
{
|
||||
print(n, base);
|
||||
println();
|
||||
}
|
||||
|
||||
void Print::println(unsigned long n, int base)
|
||||
{
|
||||
print(n, base);
|
||||
println();
|
||||
}
|
||||
|
||||
void Print::println(double n, int digits)
|
||||
{
|
||||
print(n, digits);
|
||||
println();
|
||||
}
|
||||
|
||||
// Private Methods /////////////////////////////////////////////////////////////
|
||||
|
||||
void Print::printNumber(unsigned long n, uint8_t base)
|
||||
{
|
||||
unsigned char buf[8 * sizeof(long)]; // Assumes 8-bit chars.
|
||||
unsigned long i = 0;
|
||||
|
||||
if (n == 0) {
|
||||
print('0');
|
||||
return;
|
||||
}
|
||||
|
||||
while (n > 0) {
|
||||
buf[i++] = n % base;
|
||||
n /= base;
|
||||
}
|
||||
|
||||
for (; i > 0; i--)
|
||||
print((char) (buf[i - 1] < 10 ?
|
||||
'0' + buf[i - 1] :
|
||||
'A' + buf[i - 1] - 10));
|
||||
}
|
||||
|
||||
void Print::printFloat(double number, uint8_t digits)
|
||||
{
|
||||
// Handle negative numbers
|
||||
if (number < 0.0)
|
||||
{
|
||||
print('-');
|
||||
number = -number;
|
||||
}
|
||||
|
||||
// Round correctly so that print(1.999, 2) prints as "2.00"
|
||||
double rounding = 0.5;
|
||||
for (uint8_t i=0; i<digits; ++i)
|
||||
rounding /= 10.0;
|
||||
|
||||
number += rounding;
|
||||
|
||||
// Extract the integer part of the number and print it
|
||||
unsigned long int_part = (unsigned long)number;
|
||||
double remainder = number - (double)int_part;
|
||||
print(int_part);
|
||||
|
||||
// Print the decimal point, but only if there are digits beyond
|
||||
if (digits > 0)
|
||||
print(".");
|
||||
|
||||
// Extract digits from the remainder one at a time
|
||||
while (digits-- > 0)
|
||||
{
|
||||
remainder *= 10.0;
|
||||
int toPrint = int(remainder);
|
||||
print(toPrint);
|
||||
remainder -= toPrint;
|
||||
}
|
||||
}
|
||||
62
arduino-0018-windows/hardware/arduino/cores/arduino/Print.h
Normal file
62
arduino-0018-windows/hardware/arduino/cores/arduino/Print.h
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
Print.h - Base class that provides print() and println()
|
||||
Copyright (c) 2008 David A. Mellis. All right reserved.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef Print_h
|
||||
#define Print_h
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stdio.h> // for size_t
|
||||
|
||||
#define DEC 10
|
||||
#define HEX 16
|
||||
#define OCT 8
|
||||
#define BIN 2
|
||||
#define BYTE 0
|
||||
|
||||
class Print
|
||||
{
|
||||
private:
|
||||
void printNumber(unsigned long, uint8_t);
|
||||
void printFloat(double, uint8_t);
|
||||
public:
|
||||
virtual void write(uint8_t) = 0;
|
||||
virtual void write(const char *str);
|
||||
virtual void write(const uint8_t *buffer, size_t size);
|
||||
|
||||
void print(const char[]);
|
||||
void print(char, int = BYTE);
|
||||
void print(unsigned char, int = BYTE);
|
||||
void print(int, int = DEC);
|
||||
void print(unsigned int, int = DEC);
|
||||
void print(long, int = DEC);
|
||||
void print(unsigned long, int = DEC);
|
||||
void print(double, int = 2);
|
||||
|
||||
void println(const char[]);
|
||||
void println(char, int = BYTE);
|
||||
void println(unsigned char, int = BYTE);
|
||||
void println(int, int = DEC);
|
||||
void println(unsigned int, int = DEC);
|
||||
void println(long, int = DEC);
|
||||
void println(unsigned long, int = DEC);
|
||||
void println(double, int = 2);
|
||||
void println(void);
|
||||
};
|
||||
|
||||
#endif
|
||||
515
arduino-0018-windows/hardware/arduino/cores/arduino/Tone.cpp
Normal file
515
arduino-0018-windows/hardware/arduino/cores/arduino/Tone.cpp
Normal file
|
|
@ -0,0 +1,515 @@
|
|||
/* Tone.cpp
|
||||
|
||||
A Tone Generator Library
|
||||
|
||||
Written by Brett Hagman
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
Version Modified By Date Comments
|
||||
------- ----------- -------- --------
|
||||
0001 B Hagman 09/08/02 Initial coding
|
||||
0002 B Hagman 09/08/18 Multiple pins
|
||||
0003 B Hagman 09/08/18 Moved initialization from constructor to begin()
|
||||
0004 B Hagman 09/09/26 Fixed problems with ATmega8
|
||||
0005 B Hagman 09/11/23 Scanned prescalars for best fit on 8 bit timers
|
||||
09/11/25 Changed pin toggle method to XOR
|
||||
09/11/25 Fixed timer0 from being excluded
|
||||
0006 D Mellis 09/12/29 Replaced objects with functions
|
||||
|
||||
*************************************************/
|
||||
|
||||
#include <avr/interrupt.h>
|
||||
#include <avr/pgmspace.h>
|
||||
#include <wiring.h>
|
||||
#include <pins_arduino.h>
|
||||
|
||||
#if defined(__AVR_ATmega8__)
|
||||
#define TCCR2A TCCR2
|
||||
#define TCCR2B TCCR2
|
||||
#define COM2A1 COM21
|
||||
#define COM2A0 COM20
|
||||
#define OCR2A OCR2
|
||||
#define TIMSK2 TIMSK
|
||||
#define OCIE2A OCIE2
|
||||
#define TIMER2_COMPA_vect TIMER2_COMP_vect
|
||||
#define TIMSK1 TIMSK
|
||||
#endif
|
||||
|
||||
// timerx_toggle_count:
|
||||
// > 0 - duration specified
|
||||
// = 0 - stopped
|
||||
// < 0 - infinitely (until stop() method called, or new play() called)
|
||||
|
||||
#if !defined(__AVR_ATmega8__)
|
||||
volatile long timer0_toggle_count;
|
||||
volatile uint8_t *timer0_pin_port;
|
||||
volatile uint8_t timer0_pin_mask;
|
||||
#endif
|
||||
|
||||
volatile long timer1_toggle_count;
|
||||
volatile uint8_t *timer1_pin_port;
|
||||
volatile uint8_t timer1_pin_mask;
|
||||
volatile long timer2_toggle_count;
|
||||
volatile uint8_t *timer2_pin_port;
|
||||
volatile uint8_t timer2_pin_mask;
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
volatile long timer3_toggle_count;
|
||||
volatile uint8_t *timer3_pin_port;
|
||||
volatile uint8_t timer3_pin_mask;
|
||||
volatile long timer4_toggle_count;
|
||||
volatile uint8_t *timer4_pin_port;
|
||||
volatile uint8_t timer4_pin_mask;
|
||||
volatile long timer5_toggle_count;
|
||||
volatile uint8_t *timer5_pin_port;
|
||||
volatile uint8_t timer5_pin_mask;
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
|
||||
#define AVAILABLE_TONE_PINS 1
|
||||
|
||||
const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 3, 4, 5, 1, 0 */ };
|
||||
static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255, 255, 255, 255, 255 */ };
|
||||
|
||||
#elif defined(__AVR_ATmega8__)
|
||||
|
||||
#define AVAILABLE_TONE_PINS 1
|
||||
|
||||
const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 1 */ };
|
||||
static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255 */ };
|
||||
|
||||
#else
|
||||
|
||||
#define AVAILABLE_TONE_PINS 1
|
||||
|
||||
// Leave timer 0 to last.
|
||||
const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 1, 0 */ };
|
||||
static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255, 255 */ };
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
static int8_t toneBegin(uint8_t _pin)
|
||||
{
|
||||
int8_t _timer = -1;
|
||||
|
||||
// if we're already using the pin, the timer should be configured.
|
||||
for (int i = 0; i < AVAILABLE_TONE_PINS; i++) {
|
||||
if (tone_pins[i] == _pin) {
|
||||
return pgm_read_byte(tone_pin_to_timer_PGM + i);
|
||||
}
|
||||
}
|
||||
|
||||
// search for an unused timer.
|
||||
for (int i = 0; i < AVAILABLE_TONE_PINS; i++) {
|
||||
if (tone_pins[i] == 255) {
|
||||
tone_pins[i] = _pin;
|
||||
_timer = pgm_read_byte(tone_pin_to_timer_PGM + i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (_timer != -1)
|
||||
{
|
||||
// Set timer specific stuff
|
||||
// All timers in CTC mode
|
||||
// 8 bit timers will require changing prescalar values,
|
||||
// whereas 16 bit timers are set to either ck/1 or ck/64 prescalar
|
||||
switch (_timer)
|
||||
{
|
||||
#if !defined(__AVR_ATmega8__)
|
||||
case 0:
|
||||
// 8 bit timer
|
||||
TCCR0A = 0;
|
||||
TCCR0B = 0;
|
||||
bitWrite(TCCR0A, WGM01, 1);
|
||||
bitWrite(TCCR0B, CS00, 1);
|
||||
timer0_pin_port = portOutputRegister(digitalPinToPort(_pin));
|
||||
timer0_pin_mask = digitalPinToBitMask(_pin);
|
||||
break;
|
||||
#endif
|
||||
|
||||
case 1:
|
||||
// 16 bit timer
|
||||
TCCR1A = 0;
|
||||
TCCR1B = 0;
|
||||
bitWrite(TCCR1B, WGM12, 1);
|
||||
bitWrite(TCCR1B, CS10, 1);
|
||||
timer1_pin_port = portOutputRegister(digitalPinToPort(_pin));
|
||||
timer1_pin_mask = digitalPinToBitMask(_pin);
|
||||
break;
|
||||
case 2:
|
||||
// 8 bit timer
|
||||
TCCR2A = 0;
|
||||
TCCR2B = 0;
|
||||
bitWrite(TCCR2A, WGM21, 1);
|
||||
bitWrite(TCCR2B, CS20, 1);
|
||||
timer2_pin_port = portOutputRegister(digitalPinToPort(_pin));
|
||||
timer2_pin_mask = digitalPinToBitMask(_pin);
|
||||
break;
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
case 3:
|
||||
// 16 bit timer
|
||||
TCCR3A = 0;
|
||||
TCCR3B = 0;
|
||||
bitWrite(TCCR3B, WGM32, 1);
|
||||
bitWrite(TCCR3B, CS30, 1);
|
||||
timer3_pin_port = portOutputRegister(digitalPinToPort(_pin));
|
||||
timer3_pin_mask = digitalPinToBitMask(_pin);
|
||||
break;
|
||||
case 4:
|
||||
// 16 bit timer
|
||||
TCCR4A = 0;
|
||||
TCCR4B = 0;
|
||||
bitWrite(TCCR4B, WGM42, 1);
|
||||
bitWrite(TCCR4B, CS40, 1);
|
||||
timer4_pin_port = portOutputRegister(digitalPinToPort(_pin));
|
||||
timer4_pin_mask = digitalPinToBitMask(_pin);
|
||||
break;
|
||||
case 5:
|
||||
// 16 bit timer
|
||||
TCCR5A = 0;
|
||||
TCCR5B = 0;
|
||||
bitWrite(TCCR5B, WGM52, 1);
|
||||
bitWrite(TCCR5B, CS50, 1);
|
||||
timer5_pin_port = portOutputRegister(digitalPinToPort(_pin));
|
||||
timer5_pin_mask = digitalPinToBitMask(_pin);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
return _timer;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// frequency (in hertz) and duration (in milliseconds).
|
||||
|
||||
void tone(uint8_t _pin, unsigned int frequency, unsigned long duration)
|
||||
{
|
||||
uint8_t prescalarbits = 0b001;
|
||||
long toggle_count = 0;
|
||||
uint32_t ocr = 0;
|
||||
int8_t _timer;
|
||||
|
||||
_timer = toneBegin(_pin);
|
||||
|
||||
if (_timer >= 0)
|
||||
{
|
||||
// Set the pinMode as OUTPUT
|
||||
pinMode(_pin, OUTPUT);
|
||||
|
||||
// if we are using an 8 bit timer, scan through prescalars to find the best fit
|
||||
if (_timer == 0 || _timer == 2)
|
||||
{
|
||||
ocr = F_CPU / frequency / 2 - 1;
|
||||
prescalarbits = 0b001; // ck/1: same for both timers
|
||||
if (ocr > 255)
|
||||
{
|
||||
ocr = F_CPU / frequency / 2 / 8 - 1;
|
||||
prescalarbits = 0b010; // ck/8: same for both timers
|
||||
|
||||
if (_timer == 2 && ocr > 255)
|
||||
{
|
||||
ocr = F_CPU / frequency / 2 / 32 - 1;
|
||||
prescalarbits = 0b011;
|
||||
}
|
||||
|
||||
if (ocr > 255)
|
||||
{
|
||||
ocr = F_CPU / frequency / 2 / 64 - 1;
|
||||
prescalarbits = _timer == 0 ? 0b011 : 0b100;
|
||||
|
||||
if (_timer == 2 && ocr > 255)
|
||||
{
|
||||
ocr = F_CPU / frequency / 2 / 128 - 1;
|
||||
prescalarbits = 0b101;
|
||||
}
|
||||
|
||||
if (ocr > 255)
|
||||
{
|
||||
ocr = F_CPU / frequency / 2 / 256 - 1;
|
||||
prescalarbits = _timer == 0 ? 0b100 : 0b110;
|
||||
if (ocr > 255)
|
||||
{
|
||||
// can't do any better than /1024
|
||||
ocr = F_CPU / frequency / 2 / 1024 - 1;
|
||||
prescalarbits = _timer == 0 ? 0b101 : 0b111;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if !defined(__AVR_ATmega8__)
|
||||
if (_timer == 0)
|
||||
TCCR0B = prescalarbits;
|
||||
else
|
||||
#endif
|
||||
TCCR2B = prescalarbits;
|
||||
}
|
||||
else
|
||||
{
|
||||
// two choices for the 16 bit timers: ck/1 or ck/64
|
||||
ocr = F_CPU / frequency / 2 - 1;
|
||||
|
||||
prescalarbits = 0b001;
|
||||
if (ocr > 0xffff)
|
||||
{
|
||||
ocr = F_CPU / frequency / 2 / 64 - 1;
|
||||
prescalarbits = 0b011;
|
||||
}
|
||||
|
||||
if (_timer == 1)
|
||||
TCCR1B = (TCCR1B & 0b11111000) | prescalarbits;
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
else if (_timer == 3)
|
||||
TCCR3B = (TCCR3B & 0b11111000) | prescalarbits;
|
||||
else if (_timer == 4)
|
||||
TCCR4B = (TCCR4B & 0b11111000) | prescalarbits;
|
||||
else if (_timer == 5)
|
||||
TCCR5B = (TCCR5B & 0b11111000) | prescalarbits;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
// Calculate the toggle count
|
||||
if (duration > 0)
|
||||
{
|
||||
toggle_count = 2 * frequency * duration / 1000;
|
||||
}
|
||||
else
|
||||
{
|
||||
toggle_count = -1;
|
||||
}
|
||||
|
||||
// Set the OCR for the given timer,
|
||||
// set the toggle count,
|
||||
// then turn on the interrupts
|
||||
switch (_timer)
|
||||
{
|
||||
|
||||
#if !defined(__AVR_ATmega8__)
|
||||
case 0:
|
||||
OCR0A = ocr;
|
||||
timer0_toggle_count = toggle_count;
|
||||
bitWrite(TIMSK0, OCIE0A, 1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
case 1:
|
||||
OCR1A = ocr;
|
||||
timer1_toggle_count = toggle_count;
|
||||
bitWrite(TIMSK1, OCIE1A, 1);
|
||||
break;
|
||||
case 2:
|
||||
OCR2A = ocr;
|
||||
timer2_toggle_count = toggle_count;
|
||||
bitWrite(TIMSK2, OCIE2A, 1);
|
||||
break;
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
case 3:
|
||||
OCR3A = ocr;
|
||||
timer3_toggle_count = toggle_count;
|
||||
bitWrite(TIMSK3, OCIE3A, 1);
|
||||
break;
|
||||
case 4:
|
||||
OCR4A = ocr;
|
||||
timer4_toggle_count = toggle_count;
|
||||
bitWrite(TIMSK4, OCIE4A, 1);
|
||||
break;
|
||||
case 5:
|
||||
OCR5A = ocr;
|
||||
timer5_toggle_count = toggle_count;
|
||||
bitWrite(TIMSK5, OCIE5A, 1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void noTone(uint8_t _pin)
|
||||
{
|
||||
int8_t _timer = -1;
|
||||
|
||||
for (int i = 0; i < AVAILABLE_TONE_PINS; i++) {
|
||||
if (tone_pins[i] == _pin) {
|
||||
_timer = pgm_read_byte(tone_pin_to_timer_PGM + i);
|
||||
tone_pins[i] = 255;
|
||||
}
|
||||
}
|
||||
|
||||
switch (_timer)
|
||||
{
|
||||
#if defined(__AVR_ATmega8__)
|
||||
case 1:
|
||||
bitWrite(TIMSK1, OCIE1A, 0);
|
||||
break;
|
||||
case 2:
|
||||
bitWrite(TIMSK2, OCIE2A, 0);
|
||||
break;
|
||||
|
||||
#else
|
||||
case 0:
|
||||
TIMSK0 = 0;
|
||||
break;
|
||||
case 1:
|
||||
TIMSK1 = 0;
|
||||
break;
|
||||
case 2:
|
||||
TIMSK2 = 0;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
case 3:
|
||||
TIMSK3 = 0;
|
||||
break;
|
||||
case 4:
|
||||
TIMSK4 = 0;
|
||||
break;
|
||||
case 5:
|
||||
TIMSK5 = 0;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
digitalWrite(_pin, 0);
|
||||
}
|
||||
|
||||
#if 0
|
||||
#if !defined(__AVR_ATmega8__)
|
||||
ISR(TIMER0_COMPA_vect)
|
||||
{
|
||||
if (timer0_toggle_count != 0)
|
||||
{
|
||||
// toggle the pin
|
||||
*timer0_pin_port ^= timer0_pin_mask;
|
||||
|
||||
if (timer0_toggle_count > 0)
|
||||
timer0_toggle_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMSK0 = 0; // disable the interrupt
|
||||
*timer0_pin_port &= ~(timer0_pin_mask); // keep pin low after stop
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
ISR(TIMER1_COMPA_vect)
|
||||
{
|
||||
if (timer1_toggle_count != 0)
|
||||
{
|
||||
// toggle the pin
|
||||
*timer1_pin_port ^= timer1_pin_mask;
|
||||
|
||||
if (timer1_toggle_count > 0)
|
||||
timer1_toggle_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMSK1 = 0; // disable the interrupt
|
||||
*timer1_pin_port &= ~(timer1_pin_mask); // keep pin low after stop
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
ISR(TIMER2_COMPA_vect)
|
||||
{
|
||||
|
||||
if (timer2_toggle_count != 0)
|
||||
{
|
||||
// toggle the pin
|
||||
*timer2_pin_port ^= timer2_pin_mask;
|
||||
|
||||
if (timer2_toggle_count > 0)
|
||||
timer2_toggle_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMSK2 = 0; // disable the interrupt
|
||||
*timer2_pin_port &= ~(timer2_pin_mask); // keep pin low after stop
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
//#if defined(__AVR_ATmega1280__)
|
||||
#if 0
|
||||
|
||||
ISR(TIMER3_COMPA_vect)
|
||||
{
|
||||
if (timer3_toggle_count != 0)
|
||||
{
|
||||
// toggle the pin
|
||||
*timer3_pin_port ^= timer3_pin_mask;
|
||||
|
||||
if (timer3_toggle_count > 0)
|
||||
timer3_toggle_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMSK3 = 0; // disable the interrupt
|
||||
*timer3_pin_port &= ~(timer3_pin_mask); // keep pin low after stop
|
||||
}
|
||||
}
|
||||
|
||||
ISR(TIMER4_COMPA_vect)
|
||||
{
|
||||
if (timer4_toggle_count != 0)
|
||||
{
|
||||
// toggle the pin
|
||||
*timer4_pin_port ^= timer4_pin_mask;
|
||||
|
||||
if (timer4_toggle_count > 0)
|
||||
timer4_toggle_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMSK4 = 0; // disable the interrupt
|
||||
*timer4_pin_port &= ~(timer4_pin_mask); // keep pin low after stop
|
||||
}
|
||||
}
|
||||
|
||||
ISR(TIMER5_COMPA_vect)
|
||||
{
|
||||
if (timer5_toggle_count != 0)
|
||||
{
|
||||
// toggle the pin
|
||||
*timer5_pin_port ^= timer5_pin_mask;
|
||||
|
||||
if (timer5_toggle_count > 0)
|
||||
timer5_toggle_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMSK5 = 0; // disable the interrupt
|
||||
*timer5_pin_port &= ~(timer5_pin_mask); // keep pin low after stop
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "wiring.h"
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */
|
||||
|
||||
/*
|
||||
Part of the Wiring project - http://wiring.uniandes.edu.co
|
||||
|
||||
Copyright (c) 2004-05 Hernando Barragan
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
Modified 24 November 2006 by David A. Mellis
|
||||
*/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <avr/io.h>
|
||||
#include <avr/interrupt.h>
|
||||
#include <avr/pgmspace.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "WConstants.h"
|
||||
#include "wiring_private.h"
|
||||
|
||||
volatile static voidFuncPtr intFunc[EXTERNAL_NUM_INTERRUPTS];
|
||||
// volatile static voidFuncPtr twiIntFunc;
|
||||
|
||||
#if defined(__AVR_ATmega8__)
|
||||
#define EICRA MCUCR
|
||||
#define EIMSK GICR
|
||||
#endif
|
||||
|
||||
void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) {
|
||||
if(interruptNum < EXTERNAL_NUM_INTERRUPTS) {
|
||||
intFunc[interruptNum] = userFunc;
|
||||
|
||||
// Configure the interrupt mode (trigger on low input, any change, rising
|
||||
// edge, or falling edge). The mode constants were chosen to correspond
|
||||
// to the configuration bits in the hardware register, so we simply shift
|
||||
// the mode into place.
|
||||
|
||||
// Enable the interrupt.
|
||||
|
||||
switch (interruptNum) {
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
case 2:
|
||||
EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
|
||||
EIMSK |= (1 << INT0);
|
||||
break;
|
||||
case 3:
|
||||
EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
|
||||
EIMSK |= (1 << INT1);
|
||||
break;
|
||||
case 4:
|
||||
EICRA = (EICRA & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
|
||||
EIMSK |= (1 << INT2);
|
||||
break;
|
||||
case 5:
|
||||
EICRA = (EICRA & ~((1 << ISC30) | (1 << ISC31))) | (mode << ISC30);
|
||||
EIMSK |= (1 << INT3);
|
||||
break;
|
||||
case 0:
|
||||
EICRB = (EICRB & ~((1 << ISC40) | (1 << ISC41))) | (mode << ISC40);
|
||||
EIMSK |= (1 << INT4);
|
||||
break;
|
||||
case 1:
|
||||
EICRB = (EICRB & ~((1 << ISC50) | (1 << ISC51))) | (mode << ISC50);
|
||||
EIMSK |= (1 << INT5);
|
||||
break;
|
||||
case 6:
|
||||
EICRB = (EICRB & ~((1 << ISC60) | (1 << ISC61))) | (mode << ISC60);
|
||||
EIMSK |= (1 << INT6);
|
||||
break;
|
||||
case 7:
|
||||
EICRB = (EICRB & ~((1 << ISC70) | (1 << ISC71))) | (mode << ISC70);
|
||||
EIMSK |= (1 << INT7);
|
||||
break;
|
||||
#else
|
||||
case 0:
|
||||
EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
|
||||
EIMSK |= (1 << INT0);
|
||||
break;
|
||||
case 1:
|
||||
EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
|
||||
EIMSK |= (1 << INT1);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void detachInterrupt(uint8_t interruptNum) {
|
||||
if(interruptNum < EXTERNAL_NUM_INTERRUPTS) {
|
||||
// Disable the interrupt. (We can't assume that interruptNum is equal
|
||||
// to the number of the EIMSK bit to clear, as this isn't true on the
|
||||
// ATmega8. There, INT0 is 6 and INT1 is 7.)
|
||||
switch (interruptNum) {
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
case 2:
|
||||
EIMSK &= ~(1 << INT0);
|
||||
break;
|
||||
case 3:
|
||||
EIMSK &= ~(1 << INT1);
|
||||
break;
|
||||
case 4:
|
||||
EIMSK &= ~(1 << INT2);
|
||||
break;
|
||||
case 5:
|
||||
EIMSK &= ~(1 << INT3);
|
||||
break;
|
||||
case 0:
|
||||
EIMSK &= ~(1 << INT4);
|
||||
break;
|
||||
case 1:
|
||||
EIMSK &= ~(1 << INT5);
|
||||
break;
|
||||
case 6:
|
||||
EIMSK &= ~(1 << INT6);
|
||||
break;
|
||||
case 7:
|
||||
EIMSK &= ~(1 << INT7);
|
||||
break;
|
||||
#else
|
||||
case 0:
|
||||
EIMSK &= ~(1 << INT0);
|
||||
break;
|
||||
case 1:
|
||||
EIMSK &= ~(1 << INT1);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
intFunc[interruptNum] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
void attachInterruptTwi(void (*userFunc)(void) ) {
|
||||
twiIntFunc = userFunc;
|
||||
}
|
||||
*/
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
|
||||
SIGNAL(INT0_vect) {
|
||||
if(intFunc[EXTERNAL_INT_2])
|
||||
intFunc[EXTERNAL_INT_2]();
|
||||
}
|
||||
|
||||
SIGNAL(INT1_vect) {
|
||||
if(intFunc[EXTERNAL_INT_3])
|
||||
intFunc[EXTERNAL_INT_3]();
|
||||
}
|
||||
|
||||
SIGNAL(INT2_vect) {
|
||||
if(intFunc[EXTERNAL_INT_4])
|
||||
intFunc[EXTERNAL_INT_4]();
|
||||
}
|
||||
|
||||
SIGNAL(INT3_vect) {
|
||||
if(intFunc[EXTERNAL_INT_5])
|
||||
intFunc[EXTERNAL_INT_5]();
|
||||
}
|
||||
|
||||
SIGNAL(INT4_vect) {
|
||||
if(intFunc[EXTERNAL_INT_0])
|
||||
intFunc[EXTERNAL_INT_0]();
|
||||
}
|
||||
|
||||
SIGNAL(INT5_vect) {
|
||||
if(intFunc[EXTERNAL_INT_1])
|
||||
intFunc[EXTERNAL_INT_1]();
|
||||
}
|
||||
|
||||
SIGNAL(INT6_vect) {
|
||||
if(intFunc[EXTERNAL_INT_6])
|
||||
intFunc[EXTERNAL_INT_6]();
|
||||
}
|
||||
|
||||
SIGNAL(INT7_vect) {
|
||||
if(intFunc[EXTERNAL_INT_7])
|
||||
intFunc[EXTERNAL_INT_7]();
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
SIGNAL(INT0_vect) {
|
||||
if(intFunc[EXTERNAL_INT_0])
|
||||
intFunc[EXTERNAL_INT_0]();
|
||||
}
|
||||
|
||||
SIGNAL(INT1_vect) {
|
||||
if(intFunc[EXTERNAL_INT_1])
|
||||
intFunc[EXTERNAL_INT_1]();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
SIGNAL(SIG_2WIRE_SERIAL) {
|
||||
if(twiIntFunc)
|
||||
twiIntFunc();
|
||||
}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */
|
||||
|
||||
/*
|
||||
Part of the Wiring project - http://wiring.org.co
|
||||
Copyright (c) 2004-06 Hernando Barragan
|
||||
Modified 13 August 2006, David A. Mellis for Arduino - http://www.arduino.cc/
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id$
|
||||
*/
|
||||
|
||||
extern "C" {
|
||||
#include "stdlib.h"
|
||||
}
|
||||
|
||||
void randomSeed(unsigned int seed)
|
||||
{
|
||||
if (seed != 0) {
|
||||
srandom(seed);
|
||||
}
|
||||
}
|
||||
|
||||
long random(long howbig)
|
||||
{
|
||||
if (howbig == 0) {
|
||||
return 0;
|
||||
}
|
||||
return random() % howbig;
|
||||
}
|
||||
|
||||
long random(long howsmall, long howbig)
|
||||
{
|
||||
if (howsmall >= howbig) {
|
||||
return howsmall;
|
||||
}
|
||||
long diff = howbig - howsmall;
|
||||
return random(diff) + howsmall;
|
||||
}
|
||||
|
||||
long map(long x, long in_min, long in_max, long out_min, long out_max)
|
||||
{
|
||||
return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min;
|
||||
}
|
||||
|
||||
unsigned int makeWord(unsigned int w) { return w; }
|
||||
unsigned int makeWord(unsigned char h, unsigned char l) { return (h << 8) | l; }
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#ifndef WProgram_h
|
||||
#define WProgram_h
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#include <avr/interrupt.h>
|
||||
|
||||
#include "wiring.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#include "HardwareSerial.h"
|
||||
|
||||
uint16_t makeWord(uint16_t w);
|
||||
uint16_t makeWord(byte h, byte l);
|
||||
|
||||
#define word(...) makeWord(__VA_ARGS__)
|
||||
|
||||
unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout = 1000000L);
|
||||
|
||||
void tone(uint8_t _pin, unsigned int frequency, unsigned long duration = 0);
|
||||
void noTone(uint8_t _pin);
|
||||
|
||||
// WMath prototypes
|
||||
long random(long);
|
||||
long random(long, long);
|
||||
void randomSeed(unsigned int);
|
||||
long map(long, long, long, long, long);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
515
arduino-0018-windows/hardware/arduino/cores/arduino/binary.h
Normal file
515
arduino-0018-windows/hardware/arduino/cores/arduino/binary.h
Normal file
|
|
@ -0,0 +1,515 @@
|
|||
#ifndef Binary_h
|
||||
#define Binary_h
|
||||
|
||||
#define B0 0
|
||||
#define B00 0
|
||||
#define B000 0
|
||||
#define B0000 0
|
||||
#define B00000 0
|
||||
#define B000000 0
|
||||
#define B0000000 0
|
||||
#define B00000000 0
|
||||
#define B1 1
|
||||
#define B01 1
|
||||
#define B001 1
|
||||
#define B0001 1
|
||||
#define B00001 1
|
||||
#define B000001 1
|
||||
#define B0000001 1
|
||||
#define B00000001 1
|
||||
#define B10 2
|
||||
#define B010 2
|
||||
#define B0010 2
|
||||
#define B00010 2
|
||||
#define B000010 2
|
||||
#define B0000010 2
|
||||
#define B00000010 2
|
||||
#define B11 3
|
||||
#define B011 3
|
||||
#define B0011 3
|
||||
#define B00011 3
|
||||
#define B000011 3
|
||||
#define B0000011 3
|
||||
#define B00000011 3
|
||||
#define B100 4
|
||||
#define B0100 4
|
||||
#define B00100 4
|
||||
#define B000100 4
|
||||
#define B0000100 4
|
||||
#define B00000100 4
|
||||
#define B101 5
|
||||
#define B0101 5
|
||||
#define B00101 5
|
||||
#define B000101 5
|
||||
#define B0000101 5
|
||||
#define B00000101 5
|
||||
#define B110 6
|
||||
#define B0110 6
|
||||
#define B00110 6
|
||||
#define B000110 6
|
||||
#define B0000110 6
|
||||
#define B00000110 6
|
||||
#define B111 7
|
||||
#define B0111 7
|
||||
#define B00111 7
|
||||
#define B000111 7
|
||||
#define B0000111 7
|
||||
#define B00000111 7
|
||||
#define B1000 8
|
||||
#define B01000 8
|
||||
#define B001000 8
|
||||
#define B0001000 8
|
||||
#define B00001000 8
|
||||
#define B1001 9
|
||||
#define B01001 9
|
||||
#define B001001 9
|
||||
#define B0001001 9
|
||||
#define B00001001 9
|
||||
#define B1010 10
|
||||
#define B01010 10
|
||||
#define B001010 10
|
||||
#define B0001010 10
|
||||
#define B00001010 10
|
||||
#define B1011 11
|
||||
#define B01011 11
|
||||
#define B001011 11
|
||||
#define B0001011 11
|
||||
#define B00001011 11
|
||||
#define B1100 12
|
||||
#define B01100 12
|
||||
#define B001100 12
|
||||
#define B0001100 12
|
||||
#define B00001100 12
|
||||
#define B1101 13
|
||||
#define B01101 13
|
||||
#define B001101 13
|
||||
#define B0001101 13
|
||||
#define B00001101 13
|
||||
#define B1110 14
|
||||
#define B01110 14
|
||||
#define B001110 14
|
||||
#define B0001110 14
|
||||
#define B00001110 14
|
||||
#define B1111 15
|
||||
#define B01111 15
|
||||
#define B001111 15
|
||||
#define B0001111 15
|
||||
#define B00001111 15
|
||||
#define B10000 16
|
||||
#define B010000 16
|
||||
#define B0010000 16
|
||||
#define B00010000 16
|
||||
#define B10001 17
|
||||
#define B010001 17
|
||||
#define B0010001 17
|
||||
#define B00010001 17
|
||||
#define B10010 18
|
||||
#define B010010 18
|
||||
#define B0010010 18
|
||||
#define B00010010 18
|
||||
#define B10011 19
|
||||
#define B010011 19
|
||||
#define B0010011 19
|
||||
#define B00010011 19
|
||||
#define B10100 20
|
||||
#define B010100 20
|
||||
#define B0010100 20
|
||||
#define B00010100 20
|
||||
#define B10101 21
|
||||
#define B010101 21
|
||||
#define B0010101 21
|
||||
#define B00010101 21
|
||||
#define B10110 22
|
||||
#define B010110 22
|
||||
#define B0010110 22
|
||||
#define B00010110 22
|
||||
#define B10111 23
|
||||
#define B010111 23
|
||||
#define B0010111 23
|
||||
#define B00010111 23
|
||||
#define B11000 24
|
||||
#define B011000 24
|
||||
#define B0011000 24
|
||||
#define B00011000 24
|
||||
#define B11001 25
|
||||
#define B011001 25
|
||||
#define B0011001 25
|
||||
#define B00011001 25
|
||||
#define B11010 26
|
||||
#define B011010 26
|
||||
#define B0011010 26
|
||||
#define B00011010 26
|
||||
#define B11011 27
|
||||
#define B011011 27
|
||||
#define B0011011 27
|
||||
#define B00011011 27
|
||||
#define B11100 28
|
||||
#define B011100 28
|
||||
#define B0011100 28
|
||||
#define B00011100 28
|
||||
#define B11101 29
|
||||
#define B011101 29
|
||||
#define B0011101 29
|
||||
#define B00011101 29
|
||||
#define B11110 30
|
||||
#define B011110 30
|
||||
#define B0011110 30
|
||||
#define B00011110 30
|
||||
#define B11111 31
|
||||
#define B011111 31
|
||||
#define B0011111 31
|
||||
#define B00011111 31
|
||||
#define B100000 32
|
||||
#define B0100000 32
|
||||
#define B00100000 32
|
||||
#define B100001 33
|
||||
#define B0100001 33
|
||||
#define B00100001 33
|
||||
#define B100010 34
|
||||
#define B0100010 34
|
||||
#define B00100010 34
|
||||
#define B100011 35
|
||||
#define B0100011 35
|
||||
#define B00100011 35
|
||||
#define B100100 36
|
||||
#define B0100100 36
|
||||
#define B00100100 36
|
||||
#define B100101 37
|
||||
#define B0100101 37
|
||||
#define B00100101 37
|
||||
#define B100110 38
|
||||
#define B0100110 38
|
||||
#define B00100110 38
|
||||
#define B100111 39
|
||||
#define B0100111 39
|
||||
#define B00100111 39
|
||||
#define B101000 40
|
||||
#define B0101000 40
|
||||
#define B00101000 40
|
||||
#define B101001 41
|
||||
#define B0101001 41
|
||||
#define B00101001 41
|
||||
#define B101010 42
|
||||
#define B0101010 42
|
||||
#define B00101010 42
|
||||
#define B101011 43
|
||||
#define B0101011 43
|
||||
#define B00101011 43
|
||||
#define B101100 44
|
||||
#define B0101100 44
|
||||
#define B00101100 44
|
||||
#define B101101 45
|
||||
#define B0101101 45
|
||||
#define B00101101 45
|
||||
#define B101110 46
|
||||
#define B0101110 46
|
||||
#define B00101110 46
|
||||
#define B101111 47
|
||||
#define B0101111 47
|
||||
#define B00101111 47
|
||||
#define B110000 48
|
||||
#define B0110000 48
|
||||
#define B00110000 48
|
||||
#define B110001 49
|
||||
#define B0110001 49
|
||||
#define B00110001 49
|
||||
#define B110010 50
|
||||
#define B0110010 50
|
||||
#define B00110010 50
|
||||
#define B110011 51
|
||||
#define B0110011 51
|
||||
#define B00110011 51
|
||||
#define B110100 52
|
||||
#define B0110100 52
|
||||
#define B00110100 52
|
||||
#define B110101 53
|
||||
#define B0110101 53
|
||||
#define B00110101 53
|
||||
#define B110110 54
|
||||
#define B0110110 54
|
||||
#define B00110110 54
|
||||
#define B110111 55
|
||||
#define B0110111 55
|
||||
#define B00110111 55
|
||||
#define B111000 56
|
||||
#define B0111000 56
|
||||
#define B00111000 56
|
||||
#define B111001 57
|
||||
#define B0111001 57
|
||||
#define B00111001 57
|
||||
#define B111010 58
|
||||
#define B0111010 58
|
||||
#define B00111010 58
|
||||
#define B111011 59
|
||||
#define B0111011 59
|
||||
#define B00111011 59
|
||||
#define B111100 60
|
||||
#define B0111100 60
|
||||
#define B00111100 60
|
||||
#define B111101 61
|
||||
#define B0111101 61
|
||||
#define B00111101 61
|
||||
#define B111110 62
|
||||
#define B0111110 62
|
||||
#define B00111110 62
|
||||
#define B111111 63
|
||||
#define B0111111 63
|
||||
#define B00111111 63
|
||||
#define B1000000 64
|
||||
#define B01000000 64
|
||||
#define B1000001 65
|
||||
#define B01000001 65
|
||||
#define B1000010 66
|
||||
#define B01000010 66
|
||||
#define B1000011 67
|
||||
#define B01000011 67
|
||||
#define B1000100 68
|
||||
#define B01000100 68
|
||||
#define B1000101 69
|
||||
#define B01000101 69
|
||||
#define B1000110 70
|
||||
#define B01000110 70
|
||||
#define B1000111 71
|
||||
#define B01000111 71
|
||||
#define B1001000 72
|
||||
#define B01001000 72
|
||||
#define B1001001 73
|
||||
#define B01001001 73
|
||||
#define B1001010 74
|
||||
#define B01001010 74
|
||||
#define B1001011 75
|
||||
#define B01001011 75
|
||||
#define B1001100 76
|
||||
#define B01001100 76
|
||||
#define B1001101 77
|
||||
#define B01001101 77
|
||||
#define B1001110 78
|
||||
#define B01001110 78
|
||||
#define B1001111 79
|
||||
#define B01001111 79
|
||||
#define B1010000 80
|
||||
#define B01010000 80
|
||||
#define B1010001 81
|
||||
#define B01010001 81
|
||||
#define B1010010 82
|
||||
#define B01010010 82
|
||||
#define B1010011 83
|
||||
#define B01010011 83
|
||||
#define B1010100 84
|
||||
#define B01010100 84
|
||||
#define B1010101 85
|
||||
#define B01010101 85
|
||||
#define B1010110 86
|
||||
#define B01010110 86
|
||||
#define B1010111 87
|
||||
#define B01010111 87
|
||||
#define B1011000 88
|
||||
#define B01011000 88
|
||||
#define B1011001 89
|
||||
#define B01011001 89
|
||||
#define B1011010 90
|
||||
#define B01011010 90
|
||||
#define B1011011 91
|
||||
#define B01011011 91
|
||||
#define B1011100 92
|
||||
#define B01011100 92
|
||||
#define B1011101 93
|
||||
#define B01011101 93
|
||||
#define B1011110 94
|
||||
#define B01011110 94
|
||||
#define B1011111 95
|
||||
#define B01011111 95
|
||||
#define B1100000 96
|
||||
#define B01100000 96
|
||||
#define B1100001 97
|
||||
#define B01100001 97
|
||||
#define B1100010 98
|
||||
#define B01100010 98
|
||||
#define B1100011 99
|
||||
#define B01100011 99
|
||||
#define B1100100 100
|
||||
#define B01100100 100
|
||||
#define B1100101 101
|
||||
#define B01100101 101
|
||||
#define B1100110 102
|
||||
#define B01100110 102
|
||||
#define B1100111 103
|
||||
#define B01100111 103
|
||||
#define B1101000 104
|
||||
#define B01101000 104
|
||||
#define B1101001 105
|
||||
#define B01101001 105
|
||||
#define B1101010 106
|
||||
#define B01101010 106
|
||||
#define B1101011 107
|
||||
#define B01101011 107
|
||||
#define B1101100 108
|
||||
#define B01101100 108
|
||||
#define B1101101 109
|
||||
#define B01101101 109
|
||||
#define B1101110 110
|
||||
#define B01101110 110
|
||||
#define B1101111 111
|
||||
#define B01101111 111
|
||||
#define B1110000 112
|
||||
#define B01110000 112
|
||||
#define B1110001 113
|
||||
#define B01110001 113
|
||||
#define B1110010 114
|
||||
#define B01110010 114
|
||||
#define B1110011 115
|
||||
#define B01110011 115
|
||||
#define B1110100 116
|
||||
#define B01110100 116
|
||||
#define B1110101 117
|
||||
#define B01110101 117
|
||||
#define B1110110 118
|
||||
#define B01110110 118
|
||||
#define B1110111 119
|
||||
#define B01110111 119
|
||||
#define B1111000 120
|
||||
#define B01111000 120
|
||||
#define B1111001 121
|
||||
#define B01111001 121
|
||||
#define B1111010 122
|
||||
#define B01111010 122
|
||||
#define B1111011 123
|
||||
#define B01111011 123
|
||||
#define B1111100 124
|
||||
#define B01111100 124
|
||||
#define B1111101 125
|
||||
#define B01111101 125
|
||||
#define B1111110 126
|
||||
#define B01111110 126
|
||||
#define B1111111 127
|
||||
#define B01111111 127
|
||||
#define B10000000 128
|
||||
#define B10000001 129
|
||||
#define B10000010 130
|
||||
#define B10000011 131
|
||||
#define B10000100 132
|
||||
#define B10000101 133
|
||||
#define B10000110 134
|
||||
#define B10000111 135
|
||||
#define B10001000 136
|
||||
#define B10001001 137
|
||||
#define B10001010 138
|
||||
#define B10001011 139
|
||||
#define B10001100 140
|
||||
#define B10001101 141
|
||||
#define B10001110 142
|
||||
#define B10001111 143
|
||||
#define B10010000 144
|
||||
#define B10010001 145
|
||||
#define B10010010 146
|
||||
#define B10010011 147
|
||||
#define B10010100 148
|
||||
#define B10010101 149
|
||||
#define B10010110 150
|
||||
#define B10010111 151
|
||||
#define B10011000 152
|
||||
#define B10011001 153
|
||||
#define B10011010 154
|
||||
#define B10011011 155
|
||||
#define B10011100 156
|
||||
#define B10011101 157
|
||||
#define B10011110 158
|
||||
#define B10011111 159
|
||||
#define B10100000 160
|
||||
#define B10100001 161
|
||||
#define B10100010 162
|
||||
#define B10100011 163
|
||||
#define B10100100 164
|
||||
#define B10100101 165
|
||||
#define B10100110 166
|
||||
#define B10100111 167
|
||||
#define B10101000 168
|
||||
#define B10101001 169
|
||||
#define B10101010 170
|
||||
#define B10101011 171
|
||||
#define B10101100 172
|
||||
#define B10101101 173
|
||||
#define B10101110 174
|
||||
#define B10101111 175
|
||||
#define B10110000 176
|
||||
#define B10110001 177
|
||||
#define B10110010 178
|
||||
#define B10110011 179
|
||||
#define B10110100 180
|
||||
#define B10110101 181
|
||||
#define B10110110 182
|
||||
#define B10110111 183
|
||||
#define B10111000 184
|
||||
#define B10111001 185
|
||||
#define B10111010 186
|
||||
#define B10111011 187
|
||||
#define B10111100 188
|
||||
#define B10111101 189
|
||||
#define B10111110 190
|
||||
#define B10111111 191
|
||||
#define B11000000 192
|
||||
#define B11000001 193
|
||||
#define B11000010 194
|
||||
#define B11000011 195
|
||||
#define B11000100 196
|
||||
#define B11000101 197
|
||||
#define B11000110 198
|
||||
#define B11000111 199
|
||||
#define B11001000 200
|
||||
#define B11001001 201
|
||||
#define B11001010 202
|
||||
#define B11001011 203
|
||||
#define B11001100 204
|
||||
#define B11001101 205
|
||||
#define B11001110 206
|
||||
#define B11001111 207
|
||||
#define B11010000 208
|
||||
#define B11010001 209
|
||||
#define B11010010 210
|
||||
#define B11010011 211
|
||||
#define B11010100 212
|
||||
#define B11010101 213
|
||||
#define B11010110 214
|
||||
#define B11010111 215
|
||||
#define B11011000 216
|
||||
#define B11011001 217
|
||||
#define B11011010 218
|
||||
#define B11011011 219
|
||||
#define B11011100 220
|
||||
#define B11011101 221
|
||||
#define B11011110 222
|
||||
#define B11011111 223
|
||||
#define B11100000 224
|
||||
#define B11100001 225
|
||||
#define B11100010 226
|
||||
#define B11100011 227
|
||||
#define B11100100 228
|
||||
#define B11100101 229
|
||||
#define B11100110 230
|
||||
#define B11100111 231
|
||||
#define B11101000 232
|
||||
#define B11101001 233
|
||||
#define B11101010 234
|
||||
#define B11101011 235
|
||||
#define B11101100 236
|
||||
#define B11101101 237
|
||||
#define B11101110 238
|
||||
#define B11101111 239
|
||||
#define B11110000 240
|
||||
#define B11110001 241
|
||||
#define B11110010 242
|
||||
#define B11110011 243
|
||||
#define B11110100 244
|
||||
#define B11110101 245
|
||||
#define B11110110 246
|
||||
#define B11110111 247
|
||||
#define B11111000 248
|
||||
#define B11111001 249
|
||||
#define B11111010 250
|
||||
#define B11111011 251
|
||||
#define B11111100 252
|
||||
#define B11111101 253
|
||||
#define B11111110 254
|
||||
#define B11111111 255
|
||||
|
||||
#endif
|
||||
14
arduino-0018-windows/hardware/arduino/cores/arduino/main.cpp
Normal file
14
arduino-0018-windows/hardware/arduino/cores/arduino/main.cpp
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#include <WProgram.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
init();
|
||||
|
||||
setup();
|
||||
|
||||
for (;;)
|
||||
loop();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,469 @@
|
|||
/*
|
||||
pins_arduino.c - pin definitions for the Arduino board
|
||||
Part of Arduino / Wiring Lite
|
||||
|
||||
Copyright (c) 2005 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: pins_arduino.c 804 2009-12-18 16:05:52Z dmellis $
|
||||
*/
|
||||
|
||||
#include <avr/io.h>
|
||||
#include "wiring_private.h"
|
||||
#include "pins_arduino.h"
|
||||
|
||||
// On the Arduino board, digital pins are also used
|
||||
// for the analog output (software PWM). Analog input
|
||||
// pins are a separate set.
|
||||
|
||||
// ATMEL ATMEGA8 & 168 / ARDUINO
|
||||
//
|
||||
// +-\/-+
|
||||
// PC6 1| |28 PC5 (AI 5)
|
||||
// (D 0) PD0 2| |27 PC4 (AI 4)
|
||||
// (D 1) PD1 3| |26 PC3 (AI 3)
|
||||
// (D 2) PD2 4| |25 PC2 (AI 2)
|
||||
// PWM+ (D 3) PD3 5| |24 PC1 (AI 1)
|
||||
// (D 4) PD4 6| |23 PC0 (AI 0)
|
||||
// VCC 7| |22 GND
|
||||
// GND 8| |21 AREF
|
||||
// PB6 9| |20 AVCC
|
||||
// PB7 10| |19 PB5 (D 13)
|
||||
// PWM+ (D 5) PD5 11| |18 PB4 (D 12)
|
||||
// PWM+ (D 6) PD6 12| |17 PB3 (D 11) PWM
|
||||
// (D 7) PD7 13| |16 PB2 (D 10) PWM
|
||||
// (D 8) PB0 14| |15 PB1 (D 9) PWM
|
||||
// +----+
|
||||
//
|
||||
// (PWM+ indicates the additional PWM pins on the ATmega168.)
|
||||
|
||||
// ATMEL ATMEGA1280 / ARDUINO
|
||||
//
|
||||
// 0-7 PE0-PE7 works
|
||||
// 8-13 PB0-PB5 works
|
||||
// 14-21 PA0-PA7 works
|
||||
// 22-29 PH0-PH7 works
|
||||
// 30-35 PG5-PG0 works
|
||||
// 36-43 PC7-PC0 works
|
||||
// 44-51 PJ7-PJ0 works
|
||||
// 52-59 PL7-PL0 works
|
||||
// 60-67 PD7-PD0 works
|
||||
// A0-A7 PF0-PF7
|
||||
// A8-A15 PK0-PK7
|
||||
|
||||
#define PA 1
|
||||
#define PB 2
|
||||
#define PC 3
|
||||
#define PD 4
|
||||
#define PE 5
|
||||
#define PF 6
|
||||
#define PG 7
|
||||
#define PH 8
|
||||
#define PJ 10
|
||||
#define PK 11
|
||||
#define PL 12
|
||||
|
||||
#define REPEAT8(x) x, x, x, x, x, x, x, x
|
||||
#define BV0TO7 _BV(0), _BV(1), _BV(2), _BV(3), _BV(4), _BV(5), _BV(6), _BV(7)
|
||||
#define BV7TO0 _BV(7), _BV(6), _BV(5), _BV(4), _BV(3), _BV(2), _BV(1), _BV(0)
|
||||
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
const uint16_t PROGMEM port_to_mode_PGM[] = {
|
||||
NOT_A_PORT,
|
||||
&DDRA,
|
||||
&DDRB,
|
||||
&DDRC,
|
||||
&DDRD,
|
||||
&DDRE,
|
||||
&DDRF,
|
||||
&DDRG,
|
||||
&DDRH,
|
||||
NOT_A_PORT,
|
||||
&DDRJ,
|
||||
&DDRK,
|
||||
&DDRL,
|
||||
};
|
||||
|
||||
const uint16_t PROGMEM port_to_output_PGM[] = {
|
||||
NOT_A_PORT,
|
||||
&PORTA,
|
||||
&PORTB,
|
||||
&PORTC,
|
||||
&PORTD,
|
||||
&PORTE,
|
||||
&PORTF,
|
||||
&PORTG,
|
||||
&PORTH,
|
||||
NOT_A_PORT,
|
||||
&PORTJ,
|
||||
&PORTK,
|
||||
&PORTL,
|
||||
};
|
||||
|
||||
const uint16_t PROGMEM port_to_input_PGM[] = {
|
||||
NOT_A_PIN,
|
||||
&PINA,
|
||||
&PINB,
|
||||
&PINC,
|
||||
&PIND,
|
||||
&PINE,
|
||||
&PINF,
|
||||
&PING,
|
||||
&PINH,
|
||||
NOT_A_PIN,
|
||||
&PINJ,
|
||||
&PINK,
|
||||
&PINL,
|
||||
};
|
||||
|
||||
const uint8_t PROGMEM digital_pin_to_port_PGM[] = {
|
||||
// PORTLIST
|
||||
// -------------------------------------------
|
||||
PE , // PE 0 ** 0 ** USART0_RX
|
||||
PE , // PE 1 ** 1 ** USART0_TX
|
||||
PE , // PE 4 ** 2 ** PWM2
|
||||
PE , // PE 5 ** 3 ** PWM3
|
||||
PG , // PG 5 ** 4 ** PWM4
|
||||
PE , // PE 3 ** 5 ** PWM5
|
||||
PH , // PH 3 ** 6 ** PWM6
|
||||
PH , // PH 4 ** 7 ** PWM7
|
||||
PH , // PH 5 ** 8 ** PWM8
|
||||
PH , // PH 6 ** 9 ** PWM9
|
||||
PB , // PB 4 ** 10 ** PWM10
|
||||
PB , // PB 5 ** 11 ** PWM11
|
||||
PB , // PB 6 ** 12 ** PWM12
|
||||
PB , // PB 7 ** 13 ** PWM13
|
||||
PJ , // PJ 1 ** 14 ** USART3_TX
|
||||
PJ , // PJ 0 ** 15 ** USART3_RX
|
||||
PH , // PH 1 ** 16 ** USART2_TX
|
||||
PH , // PH 0 ** 17 ** USART2_RX
|
||||
PD , // PD 3 ** 18 ** USART1_TX
|
||||
PD , // PD 2 ** 19 ** USART1_RX
|
||||
PD , // PD 1 ** 20 ** I2C_SDA
|
||||
PD , // PD 0 ** 21 ** I2C_SCL
|
||||
PA , // PA 0 ** 22 ** D22
|
||||
PA , // PA 1 ** 23 ** D23
|
||||
PA , // PA 2 ** 24 ** D24
|
||||
PA , // PA 3 ** 25 ** D25
|
||||
PA , // PA 4 ** 26 ** D26
|
||||
PA , // PA 5 ** 27 ** D27
|
||||
PA , // PA 6 ** 28 ** D28
|
||||
PA , // PA 7 ** 29 ** D29
|
||||
PC , // PC 7 ** 30 ** D30
|
||||
PC , // PC 6 ** 31 ** D31
|
||||
PC , // PC 5 ** 32 ** D32
|
||||
PC , // PC 4 ** 33 ** D33
|
||||
PC , // PC 3 ** 34 ** D34
|
||||
PC , // PC 2 ** 35 ** D35
|
||||
PC , // PC 1 ** 36 ** D36
|
||||
PC , // PC 0 ** 37 ** D37
|
||||
PD , // PD 7 ** 38 ** D38
|
||||
PG , // PG 2 ** 39 ** D39
|
||||
PG , // PG 1 ** 40 ** D40
|
||||
PG , // PG 0 ** 41 ** D41
|
||||
PL , // PL 7 ** 42 ** D42
|
||||
PL , // PL 6 ** 43 ** D43
|
||||
PL , // PL 5 ** 44 ** D44
|
||||
PL , // PL 4 ** 45 ** D45
|
||||
PL , // PL 3 ** 46 ** D46
|
||||
PL , // PL 2 ** 47 ** D47
|
||||
PL , // PL 1 ** 48 ** D48
|
||||
PL , // PL 0 ** 49 ** D49
|
||||
PB , // PB 3 ** 50 ** SPI_MISO
|
||||
PB , // PB 2 ** 51 ** SPI_MOSI
|
||||
PB , // PB 1 ** 52 ** SPI_SCK
|
||||
PB , // PB 0 ** 53 ** SPI_SS
|
||||
PF , // PF 0 ** 54 ** A0
|
||||
PF , // PF 1 ** 55 ** A1
|
||||
PF , // PF 2 ** 56 ** A2
|
||||
PF , // PF 3 ** 57 ** A3
|
||||
PF , // PF 4 ** 58 ** A4
|
||||
PF , // PF 5 ** 59 ** A5
|
||||
PF , // PF 6 ** 60 ** A6
|
||||
PF , // PF 7 ** 61 ** A7
|
||||
PK , // PK 0 ** 62 ** A8
|
||||
PK , // PK 1 ** 63 ** A9
|
||||
PK , // PK 2 ** 64 ** A10
|
||||
PK , // PK 3 ** 65 ** A11
|
||||
PK , // PK 4 ** 66 ** A12
|
||||
PK , // PK 5 ** 67 ** A13
|
||||
PK , // PK 6 ** 68 ** A14
|
||||
PK , // PK 7 ** 69 ** A15
|
||||
};
|
||||
|
||||
const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = {
|
||||
// PIN IN PORT
|
||||
// -------------------------------------------
|
||||
_BV( 0 ) , // PE 0 ** 0 ** USART0_RX
|
||||
_BV( 1 ) , // PE 1 ** 1 ** USART0_TX
|
||||
_BV( 4 ) , // PE 4 ** 2 ** PWM2
|
||||
_BV( 5 ) , // PE 5 ** 3 ** PWM3
|
||||
_BV( 5 ) , // PG 5 ** 4 ** PWM4
|
||||
_BV( 3 ) , // PE 3 ** 5 ** PWM5
|
||||
_BV( 3 ) , // PH 3 ** 6 ** PWM6
|
||||
_BV( 4 ) , // PH 4 ** 7 ** PWM7
|
||||
_BV( 5 ) , // PH 5 ** 8 ** PWM8
|
||||
_BV( 6 ) , // PH 6 ** 9 ** PWM9
|
||||
_BV( 4 ) , // PB 4 ** 10 ** PWM10
|
||||
_BV( 5 ) , // PB 5 ** 11 ** PWM11
|
||||
_BV( 6 ) , // PB 6 ** 12 ** PWM12
|
||||
_BV( 7 ) , // PB 7 ** 13 ** PWM13
|
||||
_BV( 1 ) , // PJ 1 ** 14 ** USART3_TX
|
||||
_BV( 0 ) , // PJ 0 ** 15 ** USART3_RX
|
||||
_BV( 1 ) , // PH 1 ** 16 ** USART2_TX
|
||||
_BV( 0 ) , // PH 0 ** 17 ** USART2_RX
|
||||
_BV( 3 ) , // PD 3 ** 18 ** USART1_TX
|
||||
_BV( 2 ) , // PD 2 ** 19 ** USART1_RX
|
||||
_BV( 1 ) , // PD 1 ** 20 ** I2C_SDA
|
||||
_BV( 0 ) , // PD 0 ** 21 ** I2C_SCL
|
||||
_BV( 0 ) , // PA 0 ** 22 ** D22
|
||||
_BV( 1 ) , // PA 1 ** 23 ** D23
|
||||
_BV( 2 ) , // PA 2 ** 24 ** D24
|
||||
_BV( 3 ) , // PA 3 ** 25 ** D25
|
||||
_BV( 4 ) , // PA 4 ** 26 ** D26
|
||||
_BV( 5 ) , // PA 5 ** 27 ** D27
|
||||
_BV( 6 ) , // PA 6 ** 28 ** D28
|
||||
_BV( 7 ) , // PA 7 ** 29 ** D29
|
||||
_BV( 7 ) , // PC 7 ** 30 ** D30
|
||||
_BV( 6 ) , // PC 6 ** 31 ** D31
|
||||
_BV( 5 ) , // PC 5 ** 32 ** D32
|
||||
_BV( 4 ) , // PC 4 ** 33 ** D33
|
||||
_BV( 3 ) , // PC 3 ** 34 ** D34
|
||||
_BV( 2 ) , // PC 2 ** 35 ** D35
|
||||
_BV( 1 ) , // PC 1 ** 36 ** D36
|
||||
_BV( 0 ) , // PC 0 ** 37 ** D37
|
||||
_BV( 7 ) , // PD 7 ** 38 ** D38
|
||||
_BV( 2 ) , // PG 2 ** 39 ** D39
|
||||
_BV( 1 ) , // PG 1 ** 40 ** D40
|
||||
_BV( 0 ) , // PG 0 ** 41 ** D41
|
||||
_BV( 7 ) , // PL 7 ** 42 ** D42
|
||||
_BV( 6 ) , // PL 6 ** 43 ** D43
|
||||
_BV( 5 ) , // PL 5 ** 44 ** D44
|
||||
_BV( 4 ) , // PL 4 ** 45 ** D45
|
||||
_BV( 3 ) , // PL 3 ** 46 ** D46
|
||||
_BV( 2 ) , // PL 2 ** 47 ** D47
|
||||
_BV( 1 ) , // PL 1 ** 48 ** D48
|
||||
_BV( 0 ) , // PL 0 ** 49 ** D49
|
||||
_BV( 3 ) , // PB 3 ** 50 ** SPI_MISO
|
||||
_BV( 2 ) , // PB 2 ** 51 ** SPI_MOSI
|
||||
_BV( 1 ) , // PB 1 ** 52 ** SPI_SCK
|
||||
_BV( 0 ) , // PB 0 ** 53 ** SPI_SS
|
||||
_BV( 0 ) , // PF 0 ** 54 ** A0
|
||||
_BV( 1 ) , // PF 1 ** 55 ** A1
|
||||
_BV( 2 ) , // PF 2 ** 56 ** A2
|
||||
_BV( 3 ) , // PF 3 ** 57 ** A3
|
||||
_BV( 4 ) , // PF 4 ** 58 ** A4
|
||||
_BV( 5 ) , // PF 5 ** 59 ** A5
|
||||
_BV( 6 ) , // PF 6 ** 60 ** A6
|
||||
_BV( 7 ) , // PF 7 ** 61 ** A7
|
||||
_BV( 0 ) , // PK 0 ** 62 ** A8
|
||||
_BV( 1 ) , // PK 1 ** 63 ** A9
|
||||
_BV( 2 ) , // PK 2 ** 64 ** A10
|
||||
_BV( 3 ) , // PK 3 ** 65 ** A11
|
||||
_BV( 4 ) , // PK 4 ** 66 ** A12
|
||||
_BV( 5 ) , // PK 5 ** 67 ** A13
|
||||
_BV( 6 ) , // PK 6 ** 68 ** A14
|
||||
_BV( 7 ) , // PK 7 ** 69 ** A15
|
||||
};
|
||||
|
||||
const uint8_t PROGMEM digital_pin_to_timer_PGM[] = {
|
||||
// TIMERS
|
||||
// -------------------------------------------
|
||||
NOT_ON_TIMER , // PE 0 ** 0 ** USART0_RX
|
||||
NOT_ON_TIMER , // PE 1 ** 1 ** USART0_TX
|
||||
TIMER3B , // PE 4 ** 2 ** PWM2
|
||||
TIMER3C , // PE 5 ** 3 ** PWM3
|
||||
TIMER0B , // PG 5 ** 4 ** PWM4
|
||||
TIMER3A , // PE 3 ** 5 ** PWM5
|
||||
TIMER4A , // PH 3 ** 6 ** PWM6
|
||||
TIMER4B , // PH 4 ** 7 ** PWM7
|
||||
TIMER4C , // PH 5 ** 8 ** PWM8
|
||||
TIMER2B , // PH 6 ** 9 ** PWM9
|
||||
TIMER2A , // PB 4 ** 10 ** PWM10
|
||||
TIMER1A , // PB 5 ** 11 ** PWM11
|
||||
TIMER1B , // PB 6 ** 12 ** PWM12
|
||||
TIMER0A , // PB 7 ** 13 ** PWM13
|
||||
NOT_ON_TIMER , // PJ 1 ** 14 ** USART3_TX
|
||||
NOT_ON_TIMER , // PJ 0 ** 15 ** USART3_RX
|
||||
NOT_ON_TIMER , // PH 1 ** 16 ** USART2_TX
|
||||
NOT_ON_TIMER , // PH 0 ** 17 ** USART2_RX
|
||||
NOT_ON_TIMER , // PD 3 ** 18 ** USART1_TX
|
||||
NOT_ON_TIMER , // PD 2 ** 19 ** USART1_RX
|
||||
NOT_ON_TIMER , // PD 1 ** 20 ** I2C_SDA
|
||||
NOT_ON_TIMER , // PD 0 ** 21 ** I2C_SCL
|
||||
NOT_ON_TIMER , // PA 0 ** 22 ** D22
|
||||
NOT_ON_TIMER , // PA 1 ** 23 ** D23
|
||||
NOT_ON_TIMER , // PA 2 ** 24 ** D24
|
||||
NOT_ON_TIMER , // PA 3 ** 25 ** D25
|
||||
NOT_ON_TIMER , // PA 4 ** 26 ** D26
|
||||
NOT_ON_TIMER , // PA 5 ** 27 ** D27
|
||||
NOT_ON_TIMER , // PA 6 ** 28 ** D28
|
||||
NOT_ON_TIMER , // PA 7 ** 29 ** D29
|
||||
NOT_ON_TIMER , // PC 7 ** 30 ** D30
|
||||
NOT_ON_TIMER , // PC 6 ** 31 ** D31
|
||||
NOT_ON_TIMER , // PC 5 ** 32 ** D32
|
||||
NOT_ON_TIMER , // PC 4 ** 33 ** D33
|
||||
NOT_ON_TIMER , // PC 3 ** 34 ** D34
|
||||
NOT_ON_TIMER , // PC 2 ** 35 ** D35
|
||||
NOT_ON_TIMER , // PC 1 ** 36 ** D36
|
||||
NOT_ON_TIMER , // PC 0 ** 37 ** D37
|
||||
NOT_ON_TIMER , // PD 7 ** 38 ** D38
|
||||
NOT_ON_TIMER , // PG 2 ** 39 ** D39
|
||||
NOT_ON_TIMER , // PG 1 ** 40 ** D40
|
||||
NOT_ON_TIMER , // PG 0 ** 41 ** D41
|
||||
NOT_ON_TIMER , // PL 7 ** 42 ** D42
|
||||
NOT_ON_TIMER , // PL 6 ** 43 ** D43
|
||||
TIMER5C , // PL 5 ** 44 ** D44
|
||||
TIMER5B , // PL 4 ** 45 ** D45
|
||||
TIMER5A , // PL 3 ** 46 ** D46
|
||||
NOT_ON_TIMER , // PL 2 ** 47 ** D47
|
||||
NOT_ON_TIMER , // PL 1 ** 48 ** D48
|
||||
NOT_ON_TIMER , // PL 0 ** 49 ** D49
|
||||
NOT_ON_TIMER , // PB 3 ** 50 ** SPI_MISO
|
||||
NOT_ON_TIMER , // PB 2 ** 51 ** SPI_MOSI
|
||||
NOT_ON_TIMER , // PB 1 ** 52 ** SPI_SCK
|
||||
NOT_ON_TIMER , // PB 0 ** 53 ** SPI_SS
|
||||
NOT_ON_TIMER , // PF 0 ** 54 ** A0
|
||||
NOT_ON_TIMER , // PF 1 ** 55 ** A1
|
||||
NOT_ON_TIMER , // PF 2 ** 56 ** A2
|
||||
NOT_ON_TIMER , // PF 3 ** 57 ** A3
|
||||
NOT_ON_TIMER , // PF 4 ** 58 ** A4
|
||||
NOT_ON_TIMER , // PF 5 ** 59 ** A5
|
||||
NOT_ON_TIMER , // PF 6 ** 60 ** A6
|
||||
NOT_ON_TIMER , // PF 7 ** 61 ** A7
|
||||
NOT_ON_TIMER , // PK 0 ** 62 ** A8
|
||||
NOT_ON_TIMER , // PK 1 ** 63 ** A9
|
||||
NOT_ON_TIMER , // PK 2 ** 64 ** A10
|
||||
NOT_ON_TIMER , // PK 3 ** 65 ** A11
|
||||
NOT_ON_TIMER , // PK 4 ** 66 ** A12
|
||||
NOT_ON_TIMER , // PK 5 ** 67 ** A13
|
||||
NOT_ON_TIMER , // PK 6 ** 68 ** A14
|
||||
NOT_ON_TIMER , // PK 7 ** 69 ** A15
|
||||
};
|
||||
#else
|
||||
// these arrays map port names (e.g. port B) to the
|
||||
// appropriate addresses for various functions (e.g. reading
|
||||
// and writing)
|
||||
const uint16_t PROGMEM port_to_mode_PGM[] = {
|
||||
NOT_A_PORT,
|
||||
NOT_A_PORT,
|
||||
&DDRB,
|
||||
&DDRC,
|
||||
&DDRD,
|
||||
};
|
||||
|
||||
const uint16_t PROGMEM port_to_output_PGM[] = {
|
||||
NOT_A_PORT,
|
||||
NOT_A_PORT,
|
||||
&PORTB,
|
||||
&PORTC,
|
||||
&PORTD,
|
||||
};
|
||||
|
||||
const uint16_t PROGMEM port_to_input_PGM[] = {
|
||||
NOT_A_PORT,
|
||||
NOT_A_PORT,
|
||||
&PINB,
|
||||
&PINC,
|
||||
&PIND,
|
||||
};
|
||||
|
||||
const uint8_t PROGMEM digital_pin_to_port_PGM[] = {
|
||||
PD, /* 0 */
|
||||
PD,
|
||||
PD,
|
||||
PD,
|
||||
PD,
|
||||
PD,
|
||||
PD,
|
||||
PD,
|
||||
PB, /* 8 */
|
||||
PB,
|
||||
PB,
|
||||
PB,
|
||||
PB,
|
||||
PB,
|
||||
PC, /* 14 */
|
||||
PC,
|
||||
PC,
|
||||
PC,
|
||||
PC,
|
||||
PC,
|
||||
};
|
||||
|
||||
const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = {
|
||||
_BV(0), /* 0, port D */
|
||||
_BV(1),
|
||||
_BV(2),
|
||||
_BV(3),
|
||||
_BV(4),
|
||||
_BV(5),
|
||||
_BV(6),
|
||||
_BV(7),
|
||||
_BV(0), /* 8, port B */
|
||||
_BV(1),
|
||||
_BV(2),
|
||||
_BV(3),
|
||||
_BV(4),
|
||||
_BV(5),
|
||||
_BV(0), /* 14, port C */
|
||||
_BV(1),
|
||||
_BV(2),
|
||||
_BV(3),
|
||||
_BV(4),
|
||||
_BV(5),
|
||||
};
|
||||
|
||||
const uint8_t PROGMEM digital_pin_to_timer_PGM[] = {
|
||||
NOT_ON_TIMER, /* 0 - port D */
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER,
|
||||
// on the ATmega168, digital pin 3 has hardware pwm
|
||||
#if defined(__AVR_ATmega8__)
|
||||
NOT_ON_TIMER,
|
||||
#else
|
||||
TIMER2B,
|
||||
#endif
|
||||
NOT_ON_TIMER,
|
||||
// on the ATmega168, digital pins 5 and 6 have hardware pwm
|
||||
#if defined(__AVR_ATmega8__)
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER,
|
||||
#else
|
||||
TIMER0B,
|
||||
TIMER0A,
|
||||
#endif
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER, /* 8 - port B */
|
||||
TIMER1A,
|
||||
TIMER1B,
|
||||
#if defined(__AVR_ATmega8__)
|
||||
TIMER2,
|
||||
#else
|
||||
TIMER2A,
|
||||
#endif
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER, /* 14 - port C */
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER,
|
||||
NOT_ON_TIMER,
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
pins_arduino.h - Pin definition functions for Arduino
|
||||
Part of Arduino - http://www.arduino.cc/
|
||||
|
||||
Copyright (c) 2007 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: wiring.h 249 2007-02-03 16:52:51Z mellis $
|
||||
*/
|
||||
|
||||
#ifndef Pins_Arduino_h
|
||||
#define Pins_Arduino_h
|
||||
|
||||
#include <avr/pgmspace.h>
|
||||
|
||||
#define NOT_A_PIN 0
|
||||
#define NOT_A_PORT 0
|
||||
|
||||
#define NOT_ON_TIMER 0
|
||||
#define TIMER0A 1
|
||||
#define TIMER0B 2
|
||||
#define TIMER1A 3
|
||||
#define TIMER1B 4
|
||||
#define TIMER2 5
|
||||
#define TIMER2A 6
|
||||
#define TIMER2B 7
|
||||
|
||||
#define TIMER3A 8
|
||||
#define TIMER3B 9
|
||||
#define TIMER3C 10
|
||||
#define TIMER4A 11
|
||||
#define TIMER4B 12
|
||||
#define TIMER4C 13
|
||||
#define TIMER5A 14
|
||||
#define TIMER5B 15
|
||||
#define TIMER5C 16
|
||||
|
||||
// On the ATmega1280, the addresses of some of the port registers are
|
||||
// greater than 255, so we can't store them in uint8_t's.
|
||||
extern const uint16_t PROGMEM port_to_mode_PGM[];
|
||||
extern const uint16_t PROGMEM port_to_input_PGM[];
|
||||
extern const uint16_t PROGMEM port_to_output_PGM[];
|
||||
|
||||
extern const uint8_t PROGMEM digital_pin_to_port_PGM[];
|
||||
// extern const uint8_t PROGMEM digital_pin_to_bit_PGM[];
|
||||
extern const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[];
|
||||
extern const uint8_t PROGMEM digital_pin_to_timer_PGM[];
|
||||
|
||||
// Get the bit location within the hardware port of the given virtual pin.
|
||||
// This comes from the pins_*.c file for the active board configuration.
|
||||
//
|
||||
// These perform slightly better as macros compared to inline functions
|
||||
//
|
||||
#define digitalPinToPort(P) ( pgm_read_byte( digital_pin_to_port_PGM + (P) ) )
|
||||
#define digitalPinToBitMask(P) ( pgm_read_byte( digital_pin_to_bit_mask_PGM + (P) ) )
|
||||
#define digitalPinToTimer(P) ( pgm_read_byte( digital_pin_to_timer_PGM + (P) ) )
|
||||
#define analogInPinToBit(P) (P)
|
||||
#define portOutputRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_output_PGM + (P))) )
|
||||
#define portInputRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_input_PGM + (P))) )
|
||||
#define portModeRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_mode_PGM + (P))) )
|
||||
|
||||
#endif
|
||||
238
arduino-0018-windows/hardware/arduino/cores/arduino/wiring.c
Normal file
238
arduino-0018-windows/hardware/arduino/cores/arduino/wiring.c
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
/*
|
||||
wiring.c - Partial implementation of the Wiring API for the ATmega8.
|
||||
Part of Arduino - http://www.arduino.cc/
|
||||
|
||||
Copyright (c) 2005-2006 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: wiring.c 808 2009-12-18 17:44:08Z dmellis $
|
||||
*/
|
||||
|
||||
#include "wiring_private.h"
|
||||
|
||||
// the prescaler is set so that timer0 ticks every 64 clock cycles, and the
|
||||
// the overflow handler is called every 256 ticks.
|
||||
#define MICROSECONDS_PER_TIMER0_OVERFLOW (clockCyclesToMicroseconds(64 * 256))
|
||||
|
||||
// the whole number of milliseconds per timer0 overflow
|
||||
#define MILLIS_INC (MICROSECONDS_PER_TIMER0_OVERFLOW / 1000)
|
||||
|
||||
// the fractional number of milliseconds per timer0 overflow. we shift right
|
||||
// by three to fit these numbers into a byte. (for the clock speeds we care
|
||||
// about - 8 and 16 MHz - this doesn't lose precision.)
|
||||
#define FRACT_INC ((MICROSECONDS_PER_TIMER0_OVERFLOW % 1000) >> 3)
|
||||
#define FRACT_MAX (1000 >> 3)
|
||||
|
||||
volatile unsigned long timer0_overflow_count = 0;
|
||||
volatile unsigned long timer0_millis = 0;
|
||||
static unsigned char timer0_fract = 0;
|
||||
|
||||
SIGNAL(TIMER0_OVF_vect)
|
||||
{
|
||||
// copy these to local variables so they can be stored in registers
|
||||
// (volatile variables must be read from memory on every access)
|
||||
unsigned long m = timer0_millis;
|
||||
unsigned char f = timer0_fract;
|
||||
|
||||
m += MILLIS_INC;
|
||||
f += FRACT_INC;
|
||||
if (f >= FRACT_MAX) {
|
||||
f -= FRACT_MAX;
|
||||
m += 1;
|
||||
}
|
||||
|
||||
timer0_fract = f;
|
||||
timer0_millis = m;
|
||||
timer0_overflow_count++;
|
||||
}
|
||||
|
||||
unsigned long millis()
|
||||
{
|
||||
unsigned long m;
|
||||
uint8_t oldSREG = SREG;
|
||||
|
||||
// disable interrupts while we read timer0_millis or we might get an
|
||||
// inconsistent value (e.g. in the middle of a write to timer0_millis)
|
||||
cli();
|
||||
m = timer0_millis;
|
||||
SREG = oldSREG;
|
||||
|
||||
return m;
|
||||
}
|
||||
|
||||
unsigned long micros() {
|
||||
unsigned long m;
|
||||
uint8_t oldSREG = SREG, t;
|
||||
|
||||
cli();
|
||||
m = timer0_overflow_count;
|
||||
t = TCNT0;
|
||||
|
||||
#ifdef TIFR0
|
||||
if ((TIFR0 & _BV(TOV0)) && (t < 255))
|
||||
m++;
|
||||
#else
|
||||
if ((TIFR & _BV(TOV0)) && (t < 255))
|
||||
m++;
|
||||
#endif
|
||||
|
||||
SREG = oldSREG;
|
||||
|
||||
return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond());
|
||||
}
|
||||
|
||||
void delay(unsigned long ms)
|
||||
{
|
||||
unsigned long start = millis();
|
||||
|
||||
while (millis() - start <= ms)
|
||||
;
|
||||
}
|
||||
|
||||
/* Delay for the given number of microseconds. Assumes a 8 or 16 MHz clock. */
|
||||
void delayMicroseconds(unsigned int us)
|
||||
{
|
||||
// calling avrlib's delay_us() function with low values (e.g. 1 or
|
||||
// 2 microseconds) gives delays longer than desired.
|
||||
//delay_us(us);
|
||||
|
||||
#if F_CPU >= 16000000L
|
||||
// for the 16 MHz clock on most Arduino boards
|
||||
|
||||
// for a one-microsecond delay, simply return. the overhead
|
||||
// of the function call yields a delay of approximately 1 1/8 us.
|
||||
if (--us == 0)
|
||||
return;
|
||||
|
||||
// the following loop takes a quarter of a microsecond (4 cycles)
|
||||
// per iteration, so execute it four times for each microsecond of
|
||||
// delay requested.
|
||||
us <<= 2;
|
||||
|
||||
// account for the time taken in the preceeding commands.
|
||||
us -= 2;
|
||||
#else
|
||||
// for the 8 MHz internal clock on the ATmega168
|
||||
|
||||
// for a one- or two-microsecond delay, simply return. the overhead of
|
||||
// the function calls takes more than two microseconds. can't just
|
||||
// subtract two, since us is unsigned; we'd overflow.
|
||||
if (--us == 0)
|
||||
return;
|
||||
if (--us == 0)
|
||||
return;
|
||||
|
||||
// the following loop takes half of a microsecond (4 cycles)
|
||||
// per iteration, so execute it twice for each microsecond of
|
||||
// delay requested.
|
||||
us <<= 1;
|
||||
|
||||
// partially compensate for the time taken by the preceeding commands.
|
||||
// we can't subtract any more than this or we'd overflow w/ small delays.
|
||||
us--;
|
||||
#endif
|
||||
|
||||
// busy wait
|
||||
__asm__ __volatile__ (
|
||||
"1: sbiw %0,1" "\n\t" // 2 cycles
|
||||
"brne 1b" : "=w" (us) : "0" (us) // 2 cycles
|
||||
);
|
||||
}
|
||||
|
||||
void init()
|
||||
{
|
||||
// this needs to be called before setup() or some functions won't
|
||||
// work there
|
||||
sei();
|
||||
|
||||
// on the ATmega168, timer 0 is also used for fast hardware pwm
|
||||
// (using phase-correct PWM would mean that timer 0 overflowed half as often
|
||||
// resulting in different millis() behavior on the ATmega8 and ATmega168)
|
||||
#if !defined(__AVR_ATmega8__)
|
||||
sbi(TCCR0A, WGM01);
|
||||
sbi(TCCR0A, WGM00);
|
||||
#endif
|
||||
// set timer 0 prescale factor to 64
|
||||
#if defined(__AVR_ATmega8__)
|
||||
sbi(TCCR0, CS01);
|
||||
sbi(TCCR0, CS00);
|
||||
#else
|
||||
sbi(TCCR0B, CS01);
|
||||
sbi(TCCR0B, CS00);
|
||||
#endif
|
||||
// enable timer 0 overflow interrupt
|
||||
#if defined(__AVR_ATmega8__)
|
||||
sbi(TIMSK, TOIE0);
|
||||
#else
|
||||
sbi(TIMSK0, TOIE0);
|
||||
#endif
|
||||
|
||||
// timers 1 and 2 are used for phase-correct hardware pwm
|
||||
// this is better for motors as it ensures an even waveform
|
||||
// note, however, that fast pwm mode can achieve a frequency of up
|
||||
// 8 MHz (with a 16 MHz clock) at 50% duty cycle
|
||||
|
||||
// set timer 1 prescale factor to 64
|
||||
sbi(TCCR1B, CS11);
|
||||
sbi(TCCR1B, CS10);
|
||||
// put timer 1 in 8-bit phase correct pwm mode
|
||||
sbi(TCCR1A, WGM10);
|
||||
|
||||
// set timer 2 prescale factor to 64
|
||||
#if defined(__AVR_ATmega8__)
|
||||
sbi(TCCR2, CS22);
|
||||
#else
|
||||
sbi(TCCR2B, CS22);
|
||||
#endif
|
||||
// configure timer 2 for phase correct pwm (8-bit)
|
||||
#if defined(__AVR_ATmega8__)
|
||||
sbi(TCCR2, WGM20);
|
||||
#else
|
||||
sbi(TCCR2A, WGM20);
|
||||
#endif
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
// set timer 3, 4, 5 prescale factor to 64
|
||||
sbi(TCCR3B, CS31); sbi(TCCR3B, CS30);
|
||||
sbi(TCCR4B, CS41); sbi(TCCR4B, CS40);
|
||||
sbi(TCCR5B, CS51); sbi(TCCR5B, CS50);
|
||||
// put timer 3, 4, 5 in 8-bit phase correct pwm mode
|
||||
sbi(TCCR3A, WGM30);
|
||||
sbi(TCCR4A, WGM40);
|
||||
sbi(TCCR5A, WGM50);
|
||||
#endif
|
||||
|
||||
// set a2d prescale factor to 128
|
||||
// 16 MHz / 128 = 125 KHz, inside the desired 50-200 KHz range.
|
||||
// XXX: this will not work properly for other clock speeds, and
|
||||
// this code should use F_CPU to determine the prescale factor.
|
||||
sbi(ADCSRA, ADPS2);
|
||||
sbi(ADCSRA, ADPS1);
|
||||
sbi(ADCSRA, ADPS0);
|
||||
|
||||
// enable a2d conversions
|
||||
sbi(ADCSRA, ADEN);
|
||||
|
||||
// the bootloader connects pins 0 and 1 to the USART; disconnect them
|
||||
// here so they can be used as normal digital i/o; they will be
|
||||
// reconnected in Serial.begin()
|
||||
#if defined(__AVR_ATmega8__)
|
||||
UCSRB = 0;
|
||||
#else
|
||||
UCSR0B = 0;
|
||||
#endif
|
||||
}
|
||||
133
arduino-0018-windows/hardware/arduino/cores/arduino/wiring.h
Normal file
133
arduino-0018-windows/hardware/arduino/cores/arduino/wiring.h
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
wiring.h - Partial implementation of the Wiring API for the ATmega8.
|
||||
Part of Arduino - http://www.arduino.cc/
|
||||
|
||||
Copyright (c) 2005-2006 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: wiring.h 804 2009-12-18 16:05:52Z dmellis $
|
||||
*/
|
||||
|
||||
#ifndef Wiring_h
|
||||
#define Wiring_h
|
||||
|
||||
#include <avr/io.h>
|
||||
#include "binary.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#define HIGH 0x1
|
||||
#define LOW 0x0
|
||||
|
||||
#define INPUT 0x0
|
||||
#define OUTPUT 0x1
|
||||
|
||||
#define true 0x1
|
||||
#define false 0x0
|
||||
|
||||
#define PI 3.1415926535897932384626433832795
|
||||
#define HALF_PI 1.5707963267948966192313216916398
|
||||
#define TWO_PI 6.283185307179586476925286766559
|
||||
#define DEG_TO_RAD 0.017453292519943295769236907684886
|
||||
#define RAD_TO_DEG 57.295779513082320876798154814105
|
||||
|
||||
#define SERIAL 0x0
|
||||
#define DISPLAY 0x1
|
||||
|
||||
#define LSBFIRST 0
|
||||
#define MSBFIRST 1
|
||||
|
||||
#define CHANGE 1
|
||||
#define FALLING 2
|
||||
#define RISING 3
|
||||
|
||||
#define INTERNAL 3
|
||||
#define DEFAULT 1
|
||||
#define EXTERNAL 0
|
||||
|
||||
// undefine stdlib's abs if encountered
|
||||
#ifdef abs
|
||||
#undef abs
|
||||
#endif
|
||||
|
||||
#define min(a,b) ((a)<(b)?(a):(b))
|
||||
#define max(a,b) ((a)>(b)?(a):(b))
|
||||
#define abs(x) ((x)>0?(x):-(x))
|
||||
#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt)))
|
||||
#define round(x) ((x)>=0?(long)((x)+0.5):(long)((x)-0.5))
|
||||
#define radians(deg) ((deg)*DEG_TO_RAD)
|
||||
#define degrees(rad) ((rad)*RAD_TO_DEG)
|
||||
#define sq(x) ((x)*(x))
|
||||
|
||||
#define interrupts() sei()
|
||||
#define noInterrupts() cli()
|
||||
|
||||
#define clockCyclesPerMicrosecond() ( F_CPU / 1000000L )
|
||||
#define clockCyclesToMicroseconds(a) ( (a) / clockCyclesPerMicrosecond() )
|
||||
#define microsecondsToClockCycles(a) ( (a) * clockCyclesPerMicrosecond() )
|
||||
|
||||
#define lowByte(w) ((uint8_t) ((w) & 0xff))
|
||||
#define highByte(w) ((uint8_t) ((w) >> 8))
|
||||
|
||||
#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
|
||||
#define bitSet(value, bit) ((value) |= (1UL << (bit)))
|
||||
#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
|
||||
#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit))
|
||||
|
||||
typedef unsigned int word;
|
||||
|
||||
#define bit(b) (1UL << (b))
|
||||
|
||||
typedef uint8_t boolean;
|
||||
typedef uint8_t byte;
|
||||
|
||||
void init(void);
|
||||
|
||||
void pinMode(uint8_t, uint8_t);
|
||||
void digitalWrite(uint8_t, uint8_t);
|
||||
int digitalRead(uint8_t);
|
||||
int analogRead(uint8_t);
|
||||
void analogReference(uint8_t mode);
|
||||
void analogWrite(uint8_t, int);
|
||||
|
||||
void beginSerial(long);
|
||||
void serialWrite(unsigned char);
|
||||
int serialAvailable(void);
|
||||
int serialRead(void);
|
||||
void serialFlush(void);
|
||||
|
||||
unsigned long millis(void);
|
||||
unsigned long micros(void);
|
||||
void delay(unsigned long);
|
||||
void delayMicroseconds(unsigned int us);
|
||||
unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout);
|
||||
|
||||
void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, byte val);
|
||||
|
||||
void attachInterrupt(uint8_t, void (*)(void), int mode);
|
||||
void detachInterrupt(uint8_t);
|
||||
|
||||
void setup(void);
|
||||
void loop(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
wiring_analog.c - analog input and output
|
||||
Part of Arduino - http://www.arduino.cc/
|
||||
|
||||
Copyright (c) 2005-2006 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: wiring.c 248 2007-02-03 15:36:30Z mellis $
|
||||
*/
|
||||
|
||||
#include "wiring_private.h"
|
||||
#include "pins_arduino.h"
|
||||
|
||||
uint8_t analog_reference = DEFAULT;
|
||||
|
||||
void analogReference(uint8_t mode)
|
||||
{
|
||||
// can't actually set the register here because the default setting
|
||||
// will connect AVCC and the AREF pin, which would cause a short if
|
||||
// there's something connected to AREF.
|
||||
analog_reference = mode;
|
||||
}
|
||||
|
||||
int analogRead(uint8_t pin)
|
||||
{
|
||||
uint8_t low, high;
|
||||
|
||||
// set the analog reference (high two bits of ADMUX) and select the
|
||||
// channel (low 4 bits). this also sets ADLAR (left-adjust result)
|
||||
// to 0 (the default).
|
||||
ADMUX = (analog_reference << 6) | (pin & 0x07);
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
// the MUX5 bit of ADCSRB selects whether we're reading from channels
|
||||
// 0 to 7 (MUX5 low) or 8 to 15 (MUX5 high).
|
||||
ADCSRB = (ADCSRB & ~(1 << MUX5)) | (((pin >> 3) & 0x01) << MUX5);
|
||||
#endif
|
||||
|
||||
// without a delay, we seem to read from the wrong channel
|
||||
//delay(1);
|
||||
|
||||
// start the conversion
|
||||
sbi(ADCSRA, ADSC);
|
||||
|
||||
// ADSC is cleared when the conversion finishes
|
||||
while (bit_is_set(ADCSRA, ADSC));
|
||||
|
||||
// we have to read ADCL first; doing so locks both ADCL
|
||||
// and ADCH until ADCH is read. reading ADCL second would
|
||||
// cause the results of each conversion to be discarded,
|
||||
// as ADCL and ADCH would be locked when it completed.
|
||||
low = ADCL;
|
||||
high = ADCH;
|
||||
|
||||
// combine the two bytes
|
||||
return (high << 8) | low;
|
||||
}
|
||||
|
||||
// Right now, PWM output only works on the pins with
|
||||
// hardware support. These are defined in the appropriate
|
||||
// pins_*.c file. For the rest of the pins, we default
|
||||
// to digital output.
|
||||
void analogWrite(uint8_t pin, int val)
|
||||
{
|
||||
// We need to make sure the PWM output is enabled for those pins
|
||||
// that support it, as we turn it off when digitally reading or
|
||||
// writing with them. Also, make sure the pin is in output mode
|
||||
// for consistenty with Wiring, which doesn't require a pinMode
|
||||
// call for the analog output pins.
|
||||
pinMode(pin, OUTPUT);
|
||||
|
||||
if (digitalPinToTimer(pin) == TIMER1A) {
|
||||
// connect pwm to pin on timer 1, channel A
|
||||
sbi(TCCR1A, COM1A1);
|
||||
// set pwm duty
|
||||
OCR1A = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER1B) {
|
||||
// connect pwm to pin on timer 1, channel B
|
||||
sbi(TCCR1A, COM1B1);
|
||||
// set pwm duty
|
||||
OCR1B = val;
|
||||
#if defined(__AVR_ATmega8__)
|
||||
} else if (digitalPinToTimer(pin) == TIMER2) {
|
||||
// connect pwm to pin on timer 2, channel B
|
||||
sbi(TCCR2, COM21);
|
||||
// set pwm duty
|
||||
OCR2 = val;
|
||||
#else
|
||||
} else if (digitalPinToTimer(pin) == TIMER0A) {
|
||||
if (val == 0) {
|
||||
digitalWrite(pin, LOW);
|
||||
} else {
|
||||
// connect pwm to pin on timer 0, channel A
|
||||
sbi(TCCR0A, COM0A1);
|
||||
// set pwm duty
|
||||
OCR0A = val;
|
||||
}
|
||||
} else if (digitalPinToTimer(pin) == TIMER0B) {
|
||||
if (val == 0) {
|
||||
digitalWrite(pin, LOW);
|
||||
} else {
|
||||
// connect pwm to pin on timer 0, channel B
|
||||
sbi(TCCR0A, COM0B1);
|
||||
// set pwm duty
|
||||
OCR0B = val;
|
||||
}
|
||||
} else if (digitalPinToTimer(pin) == TIMER2A) {
|
||||
// connect pwm to pin on timer 2, channel A
|
||||
sbi(TCCR2A, COM2A1);
|
||||
// set pwm duty
|
||||
OCR2A = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER2B) {
|
||||
// connect pwm to pin on timer 2, channel B
|
||||
sbi(TCCR2A, COM2B1);
|
||||
// set pwm duty
|
||||
OCR2B = val;
|
||||
#endif
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
// XXX: need to handle other timers here
|
||||
} else if (digitalPinToTimer(pin) == TIMER3A) {
|
||||
// connect pwm to pin on timer 3, channel A
|
||||
sbi(TCCR3A, COM3A1);
|
||||
// set pwm duty
|
||||
OCR3A = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER3B) {
|
||||
// connect pwm to pin on timer 3, channel B
|
||||
sbi(TCCR3A, COM3B1);
|
||||
// set pwm duty
|
||||
OCR3B = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER3C) {
|
||||
// connect pwm to pin on timer 3, channel C
|
||||
sbi(TCCR3A, COM3C1);
|
||||
// set pwm duty
|
||||
OCR3C = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER4A) {
|
||||
// connect pwm to pin on timer 4, channel A
|
||||
sbi(TCCR4A, COM4A1);
|
||||
// set pwm duty
|
||||
OCR4A = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER4B) {
|
||||
// connect pwm to pin on timer 4, channel B
|
||||
sbi(TCCR4A, COM4B1);
|
||||
// set pwm duty
|
||||
OCR4B = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER4C) {
|
||||
// connect pwm to pin on timer 4, channel C
|
||||
sbi(TCCR4A, COM4C1);
|
||||
// set pwm duty
|
||||
OCR4C = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER5A) {
|
||||
// connect pwm to pin on timer 5, channel A
|
||||
sbi(TCCR5A, COM5A1);
|
||||
// set pwm duty
|
||||
OCR5A = val;
|
||||
} else if (digitalPinToTimer(pin) == TIMER5B) {
|
||||
// connect pwm to pin on timer 5, channel B
|
||||
sbi(TCCR5A, COM5B1);
|
||||
// set pwm duty
|
||||
OCR5B = val;
|
||||
#endif
|
||||
} else if (val < 128)
|
||||
digitalWrite(pin, LOW);
|
||||
else
|
||||
digitalWrite(pin, HIGH);
|
||||
}
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
wiring_digital.c - digital input and output functions
|
||||
Part of Arduino - http://www.arduino.cc/
|
||||
|
||||
Copyright (c) 2005-2006 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: wiring.c 248 2007-02-03 15:36:30Z mellis $
|
||||
*/
|
||||
|
||||
#include "wiring_private.h"
|
||||
#include "pins_arduino.h"
|
||||
|
||||
void pinMode(uint8_t pin, uint8_t mode)
|
||||
{
|
||||
uint8_t bit = digitalPinToBitMask(pin);
|
||||
uint8_t port = digitalPinToPort(pin);
|
||||
volatile uint8_t *reg;
|
||||
|
||||
if (port == NOT_A_PIN) return;
|
||||
|
||||
// JWS: can I let the optimizer do this?
|
||||
reg = portModeRegister(port);
|
||||
|
||||
if (mode == INPUT) *reg &= ~bit;
|
||||
else *reg |= bit;
|
||||
}
|
||||
|
||||
// Forcing this inline keeps the callers from having to push their own stuff
|
||||
// on the stack. It is a good performance win and only takes 1 more byte per
|
||||
// user than calling. (It will take more bytes on the 168.)
|
||||
//
|
||||
// But shouldn't this be moved into pinMode? Seems silly to check and do on
|
||||
// each digitalread or write.
|
||||
//
|
||||
static inline void turnOffPWM(uint8_t timer) __attribute__ ((always_inline));
|
||||
static inline void turnOffPWM(uint8_t timer)
|
||||
{
|
||||
if (timer == TIMER1A) cbi(TCCR1A, COM1A1);
|
||||
if (timer == TIMER1B) cbi(TCCR1A, COM1B1);
|
||||
|
||||
#if defined(__AVR_ATmega8__)
|
||||
if (timer == TIMER2) cbi(TCCR2, COM21);
|
||||
#else
|
||||
if (timer == TIMER0A) cbi(TCCR0A, COM0A1);
|
||||
if (timer == TIMER0B) cbi(TCCR0A, COM0B1);
|
||||
if (timer == TIMER2A) cbi(TCCR2A, COM2A1);
|
||||
if (timer == TIMER2B) cbi(TCCR2A, COM2B1);
|
||||
#endif
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
if (timer == TIMER3A) cbi(TCCR3A, COM3A1);
|
||||
if (timer == TIMER3B) cbi(TCCR3A, COM3B1);
|
||||
if (timer == TIMER3C) cbi(TCCR3A, COM3C1);
|
||||
if (timer == TIMER4A) cbi(TCCR4A, COM4A1);
|
||||
if (timer == TIMER4B) cbi(TCCR4A, COM4B1);
|
||||
if (timer == TIMER4C) cbi(TCCR4A, COM4C1);
|
||||
if (timer == TIMER5A) cbi(TCCR5A, COM5A1);
|
||||
if (timer == TIMER5B) cbi(TCCR5A, COM5B1);
|
||||
if (timer == TIMER5C) cbi(TCCR5A, COM5C1);
|
||||
#endif
|
||||
}
|
||||
|
||||
void digitalWrite(uint8_t pin, uint8_t val)
|
||||
{
|
||||
uint8_t timer = digitalPinToTimer(pin);
|
||||
uint8_t bit = digitalPinToBitMask(pin);
|
||||
uint8_t port = digitalPinToPort(pin);
|
||||
volatile uint8_t *out;
|
||||
|
||||
if (port == NOT_A_PIN) return;
|
||||
|
||||
// If the pin that support PWM output, we need to turn it off
|
||||
// before doing a digital write.
|
||||
if (timer != NOT_ON_TIMER) turnOffPWM(timer);
|
||||
|
||||
out = portOutputRegister(port);
|
||||
|
||||
if (val == LOW) *out &= ~bit;
|
||||
else *out |= bit;
|
||||
}
|
||||
|
||||
int digitalRead(uint8_t pin)
|
||||
{
|
||||
uint8_t timer = digitalPinToTimer(pin);
|
||||
uint8_t bit = digitalPinToBitMask(pin);
|
||||
uint8_t port = digitalPinToPort(pin);
|
||||
|
||||
if (port == NOT_A_PIN) return LOW;
|
||||
|
||||
// If the pin that support PWM output, we need to turn it off
|
||||
// before getting a digital reading.
|
||||
if (timer != NOT_ON_TIMER) turnOffPWM(timer);
|
||||
|
||||
if (*portInputRegister(port) & bit) return HIGH;
|
||||
return LOW;
|
||||
}
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
wiring_private.h - Internal header file.
|
||||
Part of Arduino - http://www.arduino.cc/
|
||||
|
||||
Copyright (c) 2005-2006 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: wiring.h 239 2007-01-12 17:58:39Z mellis $
|
||||
*/
|
||||
|
||||
#ifndef WiringPrivate_h
|
||||
#define WiringPrivate_h
|
||||
|
||||
#include <avr/io.h>
|
||||
#include <avr/interrupt.h>
|
||||
#include <avr/delay.h>
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
|
||||
#include "wiring.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#ifndef cbi
|
||||
#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
|
||||
#endif
|
||||
#ifndef sbi
|
||||
#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
|
||||
#endif
|
||||
|
||||
#define EXTERNAL_INT_0 0
|
||||
#define EXTERNAL_INT_1 1
|
||||
#define EXTERNAL_INT_2 2
|
||||
#define EXTERNAL_INT_3 3
|
||||
#define EXTERNAL_INT_4 4
|
||||
#define EXTERNAL_INT_5 5
|
||||
#define EXTERNAL_INT_6 6
|
||||
#define EXTERNAL_INT_7 7
|
||||
|
||||
#if defined(__AVR_ATmega1280__)
|
||||
#define EXTERNAL_NUM_INTERRUPTS 8
|
||||
#else
|
||||
#define EXTERNAL_NUM_INTERRUPTS 2
|
||||
#endif
|
||||
|
||||
typedef void (*voidFuncPtr)(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
wiring_pulse.c - pulseIn() function
|
||||
Part of Arduino - http://www.arduino.cc/
|
||||
|
||||
Copyright (c) 2005-2006 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: wiring.c 248 2007-02-03 15:36:30Z mellis $
|
||||
*/
|
||||
|
||||
#include "wiring_private.h"
|
||||
#include "pins_arduino.h"
|
||||
|
||||
/* Measures the length (in microseconds) of a pulse on the pin; state is HIGH
|
||||
* or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds
|
||||
* to 3 minutes in length, but must be called at least a few dozen microseconds
|
||||
* before the start of the pulse. */
|
||||
unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout)
|
||||
{
|
||||
// cache the port and bit of the pin in order to speed up the
|
||||
// pulse width measuring loop and achieve finer resolution. calling
|
||||
// digitalRead() instead yields much coarser resolution.
|
||||
uint8_t bit = digitalPinToBitMask(pin);
|
||||
uint8_t port = digitalPinToPort(pin);
|
||||
uint8_t stateMask = (state ? bit : 0);
|
||||
unsigned long width = 0; // keep initialization out of time critical area
|
||||
|
||||
// convert the timeout from microseconds to a number of times through
|
||||
// the initial loop; it takes 16 clock cycles per iteration.
|
||||
unsigned long numloops = 0;
|
||||
unsigned long maxloops = microsecondsToClockCycles(timeout) / 16;
|
||||
|
||||
// wait for any previous pulse to end
|
||||
while ((*portInputRegister(port) & bit) == stateMask)
|
||||
if (numloops++ == maxloops)
|
||||
return 0;
|
||||
|
||||
// wait for the pulse to start
|
||||
while ((*portInputRegister(port) & bit) != stateMask)
|
||||
if (numloops++ == maxloops)
|
||||
return 0;
|
||||
|
||||
// wait for the pulse to stop
|
||||
while ((*portInputRegister(port) & bit) == stateMask)
|
||||
width++;
|
||||
|
||||
// convert the reading to microseconds. The loop has been determined
|
||||
// to be 10 clock cycles long and have about 16 clocks between the edge
|
||||
// and the start of the loop. There will be some error introduced by
|
||||
// the interrupt handlers.
|
||||
return clockCyclesToMicroseconds(width * 10 + 16);
|
||||
}
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
wiring_shift.c - shiftOut() function
|
||||
Part of Arduino - http://www.arduino.cc/
|
||||
|
||||
Copyright (c) 2005-2006 David A. Mellis
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General
|
||||
Public License along with this library; if not, write to the
|
||||
Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
||||
Boston, MA 02111-1307 USA
|
||||
|
||||
$Id: wiring.c 248 2007-02-03 15:36:30Z mellis $
|
||||
*/
|
||||
|
||||
#include "wiring_private.h"
|
||||
|
||||
void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, byte val)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (bitOrder == LSBFIRST)
|
||||
digitalWrite(dataPin, !!(val & (1 << i)));
|
||||
else
|
||||
digitalWrite(dataPin, !!(val & (1 << (7 - i))));
|
||||
|
||||
digitalWrite(clockPin, HIGH);
|
||||
digitalWrite(clockPin, LOW);
|
||||
}
|
||||
}
|
||||
20
arduino-0018-windows/hardware/arduino/programmers.txt
Normal file
20
arduino-0018-windows/hardware/arduino/programmers.txt
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
avrisp.name=AVR ISP
|
||||
avrisp.communication=serial
|
||||
avrisp.protocol=stk500v1
|
||||
|
||||
avrispmkii.name=AVRISP mkII
|
||||
avrispmkii.communication=usb
|
||||
avrispmkii.protocol=stk500v2
|
||||
|
||||
usbtinyisp.name=USBtinyISP
|
||||
usbtinyisp.protocol=usbtiny
|
||||
|
||||
parallel.name=Parallel Programmer
|
||||
parallel.protocol=dapa
|
||||
parallel.force=true
|
||||
# parallel.delay=200
|
||||
|
||||
arduinoisp.name=Arduino as ISP
|
||||
arduinoisp.communication=serial
|
||||
arduinoisp.protocol=stk500v1
|
||||
arduinoisp.speed=19200
|
||||
Binary file not shown.
4271
arduino-0018-windows/hardware/tools/avr/WinAVR-manifest.log
Normal file
4271
arduino-0018-windows/hardware/tools/avr/WinAVR-manifest.log
Normal file
File diff suppressed because it is too large
Load diff
2090
arduino-0018-windows/hardware/tools/avr/WinAVR-user-manual.html
Normal file
2090
arduino-0018-windows/hardware/tools/avr/WinAVR-user-manual.html
Normal file
File diff suppressed because it is too large
Load diff
1314
arduino-0018-windows/hardware/tools/avr/WinAVR-user-manual.txt
Normal file
1314
arduino-0018-windows/hardware/tools/avr/WinAVR-user-manual.txt
Normal file
File diff suppressed because it is too large
Load diff
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/ar.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/ar.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/as.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/as.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/c++.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/c++.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/g++.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/g++.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/gcc.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/gcc.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/ld.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/ld.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/nm.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/nm.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/objcopy.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/objcopy.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/objdump.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/objdump.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/ranlib.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/ranlib.exe
Normal file
Binary file not shown.
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/strip.exe
Normal file
BIN
arduino-0018-windows/hardware/tools/avr/avr/bin/strip.exe
Normal file
Binary file not shown.
59
arduino-0018-windows/hardware/tools/avr/avr/include/alloca.h
Normal file
59
arduino-0018-windows/hardware/tools/avr/avr/include/alloca.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/* Copyright (c) 2007, Dmitry Xmelkov
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: alloca.h,v 1.2 2007/12/18 13:34:15 dmix Exp $ */
|
||||
|
||||
#ifndef _ALLOCA_H
|
||||
#define _ALLOCA_H 1
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
/** \defgroup alloca <alloca.h>: Allocate space in the stack */
|
||||
|
||||
/** \ingroup alloca
|
||||
\brief Allocate \a __size bytes of space in the stack frame of the caller.
|
||||
|
||||
This temporary space is automatically freed when the function that
|
||||
called alloca() returns to its caller. Avr-libc defines the alloca() as
|
||||
a macro, which is translated into the inlined \c __builtin_alloca()
|
||||
function. The fact that the code is inlined, means that it is impossible
|
||||
to take the address of this function, or to change its behaviour by
|
||||
linking with a different library.
|
||||
|
||||
\return alloca() returns a pointer to the beginning of the allocated
|
||||
space. If the allocation causes stack overflow, program behaviour is
|
||||
undefined.
|
||||
|
||||
\warning Avoid use alloca() inside the list of arguments of a function
|
||||
call.
|
||||
*/
|
||||
extern void *alloca (size_t __size);
|
||||
|
||||
#define alloca(size) __builtin_alloca (size)
|
||||
|
||||
#endif /* alloca.h */
|
||||
112
arduino-0018-windows/hardware/tools/avr/avr/include/assert.h
Normal file
112
arduino-0018-windows/hardware/tools/avr/avr/include/assert.h
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/* Copyright (c) 2005,2007 Joerg Wunsch
|
||||
All rights reserved.
|
||||
|
||||
Portions of documentation Copyright (c) 1991, 1993
|
||||
The Regents of the University of California.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$Id: assert.h,v 1.3 2007/01/23 15:32:48 joerg_wunsch Exp $
|
||||
*/
|
||||
|
||||
/** \file */
|
||||
/** \defgroup avr_assert <assert.h>: Diagnostics
|
||||
\code #include <assert.h> \endcode
|
||||
|
||||
This header file defines a debugging aid.
|
||||
|
||||
As there is no standard error output stream available for many
|
||||
applications using this library, the generation of a printable
|
||||
error message is not enabled by default. These messages will
|
||||
only be generated if the application defines the macro
|
||||
|
||||
\code __ASSERT_USE_STDERR \endcode
|
||||
|
||||
before including the \c <assert.h> header file. By default,
|
||||
only abort() will be called to halt the application.
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* The ability to include this file (with or without NDEBUG) is a
|
||||
* feature.
|
||||
*/
|
||||
|
||||
#undef assert
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/**
|
||||
* \def assert
|
||||
* \param expression Expression to test for.
|
||||
*
|
||||
* The assert() macro tests the given expression and if it is false,
|
||||
* the calling process is terminated. A diagnostic message is written
|
||||
* to stderr and the function abort() is called, effectively
|
||||
* terminating the program.
|
||||
*
|
||||
* If expression is true, the assert() macro does nothing.
|
||||
*
|
||||
* The assert() macro may be removed at compile time by defining
|
||||
* NDEBUG as a macro (e.g., by using the compiler option -DNDEBUG).
|
||||
*/
|
||||
# define assert(expression)
|
||||
|
||||
#else /* !DOXYGEN */
|
||||
|
||||
# if defined(NDEBUG)
|
||||
# define assert(e) ((void)0)
|
||||
# else /* !NDEBUG */
|
||||
# if defined(__ASSERT_USE_STDERR)
|
||||
# define assert(e) ((e) ? (void)0 : \
|
||||
__assert(__func__, __FILE__, __LINE__, #e))
|
||||
# else /* !__ASSERT_USE_STDERR */
|
||||
# define assert(e) ((e) ? (void)0 : abort())
|
||||
# endif /* __ASSERT_USE_STDERR */
|
||||
# endif /* NDEBUG */
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
extern void __assert(const char *__func, const char *__file,
|
||||
int __lineno, const char *__sexp);
|
||||
|
||||
#endif /* not __DOXYGEN__ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
/* EOF */
|
||||
677
arduino-0018-windows/hardware/tools/avr/avr/include/avr/boot.h
Normal file
677
arduino-0018-windows/hardware/tools/avr/avr/include/avr/boot.h
Normal file
|
|
@ -0,0 +1,677 @@
|
|||
/* Copyright (c) 2002, 2003, 2004, 2005, 2006, 2007 Eric B. Weddington
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: boot.h,v 1.27.2.3 2008/09/30 13:58:48 arcanum Exp $ */
|
||||
|
||||
#ifndef _AVR_BOOT_H_
|
||||
#define _AVR_BOOT_H_ 1
|
||||
|
||||
/** \file */
|
||||
/** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
|
||||
\code
|
||||
#include <avr/io.h>
|
||||
#include <avr/boot.h>
|
||||
\endcode
|
||||
|
||||
The macros in this module provide a C language interface to the
|
||||
bootloader support functionality of certain AVR processors. These
|
||||
macros are designed to work with all sizes of flash memory.
|
||||
|
||||
Global interrupts are not automatically disabled for these macros. It
|
||||
is left up to the programmer to do this. See the code example below.
|
||||
Also see the processor datasheet for caveats on having global interrupts
|
||||
enabled during writing of the Flash.
|
||||
|
||||
\note Not all AVR processors provide bootloader support. See your
|
||||
processor datasheet to see if it provides bootloader support.
|
||||
|
||||
\todo From email with Marek: On smaller devices (all except ATmega64/128),
|
||||
__SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
|
||||
instructions - since the boot loader has a limited size, this could be an
|
||||
important optimization.
|
||||
|
||||
\par API Usage Example
|
||||
The following code shows typical usage of the boot API.
|
||||
|
||||
\code
|
||||
#include <inttypes.h>
|
||||
#include <avr/interrupt.h>
|
||||
#include <avr/pgmspace.h>
|
||||
|
||||
void boot_program_page (uint32_t page, uint8_t *buf)
|
||||
{
|
||||
uint16_t i;
|
||||
uint8_t sreg;
|
||||
|
||||
// Disable interrupts.
|
||||
|
||||
sreg = SREG;
|
||||
cli();
|
||||
|
||||
eeprom_busy_wait ();
|
||||
|
||||
boot_page_erase (page);
|
||||
boot_spm_busy_wait (); // Wait until the memory is erased.
|
||||
|
||||
for (i=0; i<SPM_PAGESIZE; i+=2)
|
||||
{
|
||||
// Set up little-endian word.
|
||||
|
||||
uint16_t w = *buf++;
|
||||
w += (*buf++) << 8;
|
||||
|
||||
boot_page_fill (page + i, w);
|
||||
}
|
||||
|
||||
boot_page_write (page); // Store buffer in flash page.
|
||||
boot_spm_busy_wait(); // Wait until the memory is written.
|
||||
|
||||
// Reenable RWW-section again. We need this if we want to jump back
|
||||
// to the application after bootloading.
|
||||
|
||||
boot_rww_enable ();
|
||||
|
||||
// Re-enable interrupts (if they were ever enabled).
|
||||
|
||||
SREG = sreg;
|
||||
}\endcode */
|
||||
|
||||
#include <avr/eeprom.h>
|
||||
#include <avr/io.h>
|
||||
#include <inttypes.h>
|
||||
#include <limits.h>
|
||||
|
||||
/* Check for SPM Control Register in processor. */
|
||||
#if defined (SPMCSR)
|
||||
# define __SPM_REG SPMCSR
|
||||
#elif defined (SPMCR)
|
||||
# define __SPM_REG SPMCR
|
||||
#else
|
||||
# error AVR processor does not provide bootloader support!
|
||||
#endif
|
||||
|
||||
|
||||
/* Check for SPM Enable bit. */
|
||||
#if defined(SPMEN)
|
||||
# define __SPM_ENABLE SPMEN
|
||||
#elif defined(SELFPRGEN)
|
||||
# define __SPM_ENABLE SELFPRGEN
|
||||
#else
|
||||
# error Cannot find SPM Enable bit definition!
|
||||
#endif
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def BOOTLOADER_SECTION
|
||||
|
||||
Used to declare a function or variable to be placed into a
|
||||
new section called .bootloader. This section and its contents
|
||||
can then be relocated to any address (such as the bootloader
|
||||
NRWW area) at link-time. */
|
||||
|
||||
#define BOOTLOADER_SECTION __attribute__ ((section (".bootloader")))
|
||||
|
||||
/* Create common bit definitions. */
|
||||
#ifdef ASB
|
||||
#define __COMMON_ASB ASB
|
||||
#else
|
||||
#define __COMMON_ASB RWWSB
|
||||
#endif
|
||||
|
||||
#ifdef ASRE
|
||||
#define __COMMON_ASRE ASRE
|
||||
#else
|
||||
#define __COMMON_ASRE RWWSRE
|
||||
#endif
|
||||
|
||||
/* Define the bit positions of the Boot Lock Bits. */
|
||||
|
||||
#define BLB12 5
|
||||
#define BLB11 4
|
||||
#define BLB02 3
|
||||
#define BLB01 2
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_spm_interrupt_enable()
|
||||
Enable the SPM interrupt. */
|
||||
|
||||
#define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE))
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_spm_interrupt_disable()
|
||||
Disable the SPM interrupt. */
|
||||
|
||||
#define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE))
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_is_spm_interrupt()
|
||||
Check if the SPM interrupt is enabled. */
|
||||
|
||||
#define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE))
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_rww_busy()
|
||||
Check if the RWW section is busy. */
|
||||
|
||||
#define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_spm_busy()
|
||||
Check if the SPM instruction is busy. */
|
||||
|
||||
#define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_spm_busy_wait()
|
||||
Wait while the SPM instruction is busy. */
|
||||
|
||||
#define boot_spm_busy_wait() do{}while(boot_spm_busy())
|
||||
|
||||
#define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS))
|
||||
#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
|
||||
#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
|
||||
#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
|
||||
#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
|
||||
|
||||
#define __boot_page_fill_normal(address, data) \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"movw r0, %3\n\t" \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
"clr r1\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_FILL), \
|
||||
"z" ((uint16_t)address), \
|
||||
"r" ((uint16_t)data) \
|
||||
: "r0" \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_page_fill_alternate(address, data)\
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"movw r0, %3\n\t" \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
".word 0xffff\n\t" \
|
||||
"nop\n\t" \
|
||||
"clr r1\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_FILL), \
|
||||
"z" ((uint16_t)address), \
|
||||
"r" ((uint16_t)data) \
|
||||
: "r0" \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_page_fill_extended(address, data) \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"movw r0, %4\n\t" \
|
||||
"movw r30, %A3\n\t" \
|
||||
"sts %1, %C3\n\t" \
|
||||
"sts %0, %2\n\t" \
|
||||
"spm\n\t" \
|
||||
"clr r1\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"i" (_SFR_MEM_ADDR(RAMPZ)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_FILL), \
|
||||
"r" ((uint32_t)address), \
|
||||
"r" ((uint16_t)data) \
|
||||
: "r0", "r30", "r31" \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_page_erase_normal(address) \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_ERASE), \
|
||||
"z" ((uint16_t)address) \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_page_erase_alternate(address) \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
".word 0xffff\n\t" \
|
||||
"nop\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_ERASE), \
|
||||
"z" ((uint16_t)address) \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_page_erase_extended(address) \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"movw r30, %A3\n\t" \
|
||||
"sts %1, %C3\n\t" \
|
||||
"sts %0, %2\n\t" \
|
||||
"spm\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"i" (_SFR_MEM_ADDR(RAMPZ)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_ERASE), \
|
||||
"r" ((uint32_t)address) \
|
||||
: "r30", "r31" \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_page_write_normal(address) \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_WRITE), \
|
||||
"z" ((uint16_t)address) \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_page_write_alternate(address) \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
".word 0xffff\n\t" \
|
||||
"nop\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_WRITE), \
|
||||
"z" ((uint16_t)address) \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_page_write_extended(address) \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"movw r30, %A3\n\t" \
|
||||
"sts %1, %C3\n\t" \
|
||||
"sts %0, %2\n\t" \
|
||||
"spm\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"i" (_SFR_MEM_ADDR(RAMPZ)), \
|
||||
"r" ((uint8_t)__BOOT_PAGE_WRITE), \
|
||||
"r" ((uint32_t)address) \
|
||||
: "r30", "r31" \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_rww_enable() \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_RWW_ENABLE) \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_rww_enable_alternate() \
|
||||
(__extension__({ \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
".word 0xffff\n\t" \
|
||||
"nop\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_RWW_ENABLE) \
|
||||
); \
|
||||
}))
|
||||
|
||||
/* From the mega16/mega128 data sheets (maybe others):
|
||||
|
||||
Bits by SPM To set the Boot Loader Lock bits, write the desired data to
|
||||
R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
|
||||
after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
|
||||
that may prevent the Application and Boot Loader section from any
|
||||
software update by the MCU.
|
||||
|
||||
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
|
||||
will be programmed if an SPM instruction is executed within four cycles
|
||||
after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
|
||||
don't care during this operation, but for future compatibility it is
|
||||
recommended to load the Z-pointer with $0001 (same as used for reading the
|
||||
Lock bits). For future compatibility It is also recommended to set bits 7,
|
||||
6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
|
||||
Lock bits the entire Flash can be read during the operation. */
|
||||
|
||||
#define __boot_lock_bits_set(lock_bits) \
|
||||
(__extension__({ \
|
||||
uint8_t value = (uint8_t)(~(lock_bits)); \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"ldi r30, 1\n\t" \
|
||||
"ldi r31, 0\n\t" \
|
||||
"mov r0, %2\n\t" \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
|
||||
"r" (value) \
|
||||
: "r0", "r30", "r31" \
|
||||
); \
|
||||
}))
|
||||
|
||||
#define __boot_lock_bits_set_alternate(lock_bits) \
|
||||
(__extension__({ \
|
||||
uint8_t value = (uint8_t)(~(lock_bits)); \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"ldi r30, 1\n\t" \
|
||||
"ldi r31, 0\n\t" \
|
||||
"mov r0, %2\n\t" \
|
||||
"sts %0, %1\n\t" \
|
||||
"spm\n\t" \
|
||||
".word 0xffff\n\t" \
|
||||
"nop\n\t" \
|
||||
: \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
|
||||
"r" (value) \
|
||||
: "r0", "r30", "r31" \
|
||||
); \
|
||||
}))
|
||||
|
||||
/*
|
||||
Reading lock and fuse bits:
|
||||
|
||||
Similarly to writing the lock bits above, set BLBSET and SPMEN (or
|
||||
SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
|
||||
LPM instruction.
|
||||
|
||||
Z address: contents:
|
||||
0x0000 low fuse bits
|
||||
0x0001 lock bits
|
||||
0x0002 extended fuse bits
|
||||
0x0003 high fuse bits
|
||||
|
||||
Sounds confusing, doesn't it?
|
||||
|
||||
Unlike the macros in pgmspace.h, no need to care for non-enhanced
|
||||
cores here as these old cores do not provide SPM support anyway.
|
||||
*/
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def GET_LOW_FUSE_BITS
|
||||
address to read the low fuse bits, using boot_lock_fuse_bits_get
|
||||
*/
|
||||
#define GET_LOW_FUSE_BITS (0x0000)
|
||||
/** \ingroup avr_boot
|
||||
\def GET_LOCK_BITS
|
||||
address to read the lock bits, using boot_lock_fuse_bits_get
|
||||
*/
|
||||
#define GET_LOCK_BITS (0x0001)
|
||||
/** \ingroup avr_boot
|
||||
\def GET_EXTENDED_FUSE_BITS
|
||||
address to read the extended fuse bits, using boot_lock_fuse_bits_get
|
||||
*/
|
||||
#define GET_EXTENDED_FUSE_BITS (0x0002)
|
||||
/** \ingroup avr_boot
|
||||
\def GET_HIGH_FUSE_BITS
|
||||
address to read the high fuse bits, using boot_lock_fuse_bits_get
|
||||
*/
|
||||
#define GET_HIGH_FUSE_BITS (0x0003)
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_lock_fuse_bits_get(address)
|
||||
|
||||
Read the lock or fuse bits at \c address.
|
||||
|
||||
Parameter \c address can be any of GET_LOW_FUSE_BITS,
|
||||
GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
|
||||
|
||||
\note The lock and fuse bits returned are the physical values,
|
||||
i.e. a bit returned as 0 means the corresponding fuse or lock bit
|
||||
is programmed.
|
||||
*/
|
||||
#define boot_lock_fuse_bits_get(address) \
|
||||
(__extension__({ \
|
||||
uint8_t __result; \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"ldi r30, %3\n\t" \
|
||||
"ldi r31, 0\n\t" \
|
||||
"sts %1, %2\n\t" \
|
||||
"lpm %0, Z\n\t" \
|
||||
: "=r" (__result) \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
|
||||
"M" (address) \
|
||||
: "r0", "r30", "r31" \
|
||||
); \
|
||||
__result; \
|
||||
}))
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_signature_byte_get(address)
|
||||
|
||||
Read the Signature Row byte at \c address. For some MCU types,
|
||||
this function can also retrieve the factory-stored oscillator
|
||||
calibration bytes.
|
||||
|
||||
Parameter \c address can be 0-0x1f as documented by the datasheet.
|
||||
\note The values are MCU type dependent.
|
||||
*/
|
||||
|
||||
#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
|
||||
|
||||
#define boot_signature_byte_get(addr) \
|
||||
(__extension__({ \
|
||||
uint16_t __addr16 = (uint16_t)(addr); \
|
||||
uint8_t __result; \
|
||||
__asm__ __volatile__ \
|
||||
( \
|
||||
"sts %1, %2\n\t" \
|
||||
"lpm %0, Z" "\n\t" \
|
||||
: "=r" (__result) \
|
||||
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
||||
"r" ((uint8_t) __BOOT_SIGROW_READ), \
|
||||
"z" (__addr16) \
|
||||
); \
|
||||
__result; \
|
||||
}))
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_page_fill(address, data)
|
||||
|
||||
Fill the bootloader temporary page buffer for flash
|
||||
address with data word.
|
||||
|
||||
\note The address is a byte address. The data is a word. The AVR
|
||||
writes data to the buffer a word at a time, but addresses the buffer
|
||||
per byte! So, increment your address by 2 between calls, and send 2
|
||||
data bytes in a word format! The LSB of the data is written to the lower
|
||||
address; the MSB of the data is written to the higher address.*/
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_page_erase(address)
|
||||
|
||||
Erase the flash page that contains address.
|
||||
|
||||
\note address is a byte address in flash, not a word address. */
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_page_write(address)
|
||||
|
||||
Write the bootloader temporary page buffer
|
||||
to flash page that contains address.
|
||||
|
||||
\note address is a byte address in flash, not a word address. */
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_rww_enable()
|
||||
|
||||
Enable the Read-While-Write memory section. */
|
||||
|
||||
/** \ingroup avr_boot
|
||||
\def boot_lock_bits_set(lock_bits)
|
||||
|
||||
Set the bootloader lock bits.
|
||||
|
||||
\param lock_bits A mask of which Boot Loader Lock Bits to set.
|
||||
|
||||
\note In this context, a 'set bit' will be written to a zero value.
|
||||
Note also that only BLBxx bits can be programmed by this command.
|
||||
|
||||
For example, to disallow the SPM instruction from writing to the Boot
|
||||
Loader memory section of flash, you would use this macro as such:
|
||||
|
||||
\code
|
||||
boot_lock_bits_set (_BV (BLB11));
|
||||
\endcode
|
||||
|
||||
\note Like any lock bits, the Boot Loader Lock Bits, once set,
|
||||
cannot be cleared again except by a chip erase which will in turn
|
||||
also erase the boot loader itself. */
|
||||
|
||||
/* Normal versions of the macros use 16-bit addresses.
|
||||
Extended versions of the macros use 32-bit addresses.
|
||||
Alternate versions of the macros use 16-bit addresses and require special
|
||||
instruction sequences after LPM.
|
||||
|
||||
FLASHEND is defined in the ioXXXX.h file.
|
||||
USHRT_MAX is defined in <limits.h>. */
|
||||
|
||||
#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
|
||||
|| defined(__AVR_ATmega323__)
|
||||
|
||||
/* Alternate: ATmega161/163/323 and 16 bit address */
|
||||
#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
|
||||
#define boot_page_erase(address) __boot_page_erase_alternate(address)
|
||||
#define boot_page_write(address) __boot_page_write_alternate(address)
|
||||
#define boot_rww_enable() __boot_rww_enable_alternate()
|
||||
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
|
||||
|
||||
#elif (FLASHEND > USHRT_MAX)
|
||||
|
||||
/* Extended: >16 bit address */
|
||||
#define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
|
||||
#define boot_page_erase(address) __boot_page_erase_extended(address)
|
||||
#define boot_page_write(address) __boot_page_write_extended(address)
|
||||
#define boot_rww_enable() __boot_rww_enable()
|
||||
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
|
||||
|
||||
#else
|
||||
|
||||
/* Normal: 16 bit address */
|
||||
#define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
|
||||
#define boot_page_erase(address) __boot_page_erase_normal(address)
|
||||
#define boot_page_write(address) __boot_page_write_normal(address)
|
||||
#define boot_rww_enable() __boot_rww_enable()
|
||||
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
|
||||
|
||||
#endif
|
||||
|
||||
/** \ingroup avr_boot
|
||||
|
||||
Same as boot_page_fill() except it waits for eeprom and spm operations to
|
||||
complete before filling the page. */
|
||||
|
||||
#define boot_page_fill_safe(address, data) \
|
||||
do { \
|
||||
boot_spm_busy_wait(); \
|
||||
eeprom_busy_wait(); \
|
||||
boot_page_fill(address, data); \
|
||||
} while (0)
|
||||
|
||||
/** \ingroup avr_boot
|
||||
|
||||
Same as boot_page_erase() except it waits for eeprom and spm operations to
|
||||
complete before erasing the page. */
|
||||
|
||||
#define boot_page_erase_safe(address) \
|
||||
do { \
|
||||
boot_spm_busy_wait(); \
|
||||
eeprom_busy_wait(); \
|
||||
boot_page_erase (address); \
|
||||
} while (0)
|
||||
|
||||
/** \ingroup avr_boot
|
||||
|
||||
Same as boot_page_write() except it waits for eeprom and spm operations to
|
||||
complete before writing the page. */
|
||||
|
||||
#define boot_page_write_safe(address) \
|
||||
do { \
|
||||
boot_spm_busy_wait(); \
|
||||
eeprom_busy_wait(); \
|
||||
boot_page_write (address); \
|
||||
} while (0)
|
||||
|
||||
/** \ingroup avr_boot
|
||||
|
||||
Same as boot_rww_enable() except waits for eeprom and spm operations to
|
||||
complete before enabling the RWW mameory. */
|
||||
|
||||
#define boot_rww_enable_safe() \
|
||||
do { \
|
||||
boot_spm_busy_wait(); \
|
||||
eeprom_busy_wait(); \
|
||||
boot_rww_enable(); \
|
||||
} while (0)
|
||||
|
||||
/** \ingroup avr_boot
|
||||
|
||||
Same as boot_lock_bits_set() except waits for eeprom and spm operations to
|
||||
complete before setting the lock bits. */
|
||||
|
||||
#define boot_lock_bits_set_safe(lock_bits) \
|
||||
do { \
|
||||
boot_spm_busy_wait(); \
|
||||
eeprom_busy_wait(); \
|
||||
boot_lock_bits_set (lock_bits); \
|
||||
} while (0)
|
||||
|
||||
#endif /* _AVR_BOOT_H_ */
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/* Copyright (c) 2008 Anatoly Sokolv
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id:$ */
|
||||
|
||||
/*
|
||||
avr/builtins.h -
|
||||
*/
|
||||
|
||||
#ifndef _AVR_BUILTINS_H_
|
||||
#define _AVR_BUILTINS_H_
|
||||
|
||||
/** \file */
|
||||
/** \defgroup avr_builtins <avr/builtins.h>: GCC builtins
|
||||
\code #include <avr/builtins.h> \endcode
|
||||
|
||||
This header file declares avr builtins. */
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
Enables interrupts by setting the global interrupt mask. */
|
||||
extern void __builtin_avr_sei(void);
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
Disables all interrupts by clearing the global interrupt mask. */
|
||||
extern void __builtin_avr_cli(void);
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
TODO. */
|
||||
|
||||
extern void __builtin_avr_sleep(void);
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
TODO. */
|
||||
extern void __builtin_avr_wdr(void);
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
TODO. */
|
||||
extern unsigned char __builtin_avr_swap(unsigned char __b);
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
TODO. */
|
||||
extern unsigned int __builtin_avr_fmul(unsigned char __a, unsigned char __b);
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
TODO. */
|
||||
extern int __builtin_avr_fmuls(char __a, char __b);
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
TODO. */
|
||||
extern int __builtin_avr_fmulsu(char __a, unsigned char __b);
|
||||
|
||||
/**
|
||||
\ingroup avr_builtins
|
||||
|
||||
TODO. */
|
||||
extern void __builtin_avr_delay_cycles(unsigned long __n);
|
||||
|
||||
#endif /* _AVR_BUILTINS_H_ */
|
||||
293
arduino-0018-windows/hardware/tools/avr/avr/include/avr/common.h
Normal file
293
arduino-0018-windows/hardware/tools/avr/avr/include/avr/common.h
Normal file
|
|
@ -0,0 +1,293 @@
|
|||
/* Copyright (c) 2007 Eric B. Weddington
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: common.h,v 1.3.4.3 2008/03/24 17:11:06 arcanum Exp $ */
|
||||
|
||||
|
||||
#ifndef _AVR_COMMON_H
|
||||
#define _AVR_COMMON_H
|
||||
|
||||
#include <avr/sfr_defs.h>
|
||||
|
||||
/*
|
||||
This purpose of this header is to define registers that have not been
|
||||
previously defined in the individual device IO header files, and to define
|
||||
other symbols that are common across AVR device families.
|
||||
|
||||
This file is designed to be included in <avr/io.h> after the individual
|
||||
device IO header files, and after <avr/sfr_defs.h>
|
||||
|
||||
*/
|
||||
|
||||
/*------------ Registers Not Previously Defined ------------*/
|
||||
|
||||
/*
|
||||
These are registers that are not previously defined in the individual
|
||||
IO header files, OR they are defined here because they are used in parts of
|
||||
avr-libc even if a device is not selected but a general architecture has
|
||||
been selected.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
Stack pointer register.
|
||||
|
||||
AVR architecture 1 has no RAM, thus no stack pointer.
|
||||
|
||||
All other architectures do have a stack pointer. Some devices have only
|
||||
less than 256 bytes of possible RAM locations (128 Bytes of SRAM
|
||||
and no option for external RAM), thus SPH is officially "reserved"
|
||||
for them.
|
||||
*/
|
||||
#if __AVR_ARCH__ >= 100
|
||||
# ifndef SPL
|
||||
# define SPL _SFR_MEM8(0x3D)
|
||||
# endif
|
||||
# ifndef SPH
|
||||
# define SPH _SFR_MEM8(0x3E)
|
||||
# endif
|
||||
# ifndef SP
|
||||
# define SP _SFR_MEM16(0x3D)
|
||||
# endif
|
||||
#elif __AVR_ARCH__ != 1
|
||||
# ifndef SPL
|
||||
# define SPL _SFR_IO8(0x3D)
|
||||
# endif
|
||||
# if XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__)
|
||||
# ifndef SP
|
||||
# define SP _SFR_IO8(0x3D)
|
||||
# endif
|
||||
# else
|
||||
# ifndef SP
|
||||
# define SP _SFR_IO16(0x3D)
|
||||
# endif
|
||||
# ifndef SPH
|
||||
# define SPH _SFR_IO8(0x3E)
|
||||
# endif
|
||||
# endif /* XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) */
|
||||
#endif /* __AVR_ARCH__ != 1 */
|
||||
|
||||
|
||||
/* Status Register */
|
||||
#ifndef SREG
|
||||
# if __AVR_ARCH__ >= 100
|
||||
# define SREG _SFR_MEM8(0x3F)
|
||||
# else
|
||||
# define SREG _SFR_IO8(0x3F)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
||||
/* SREG bit definitions */
|
||||
#ifndef SREG_C
|
||||
# define SREG_C (0)
|
||||
#endif
|
||||
#ifndef SREG_Z
|
||||
# define SREG_Z (1)
|
||||
#endif
|
||||
#ifndef SREG_N
|
||||
# define SREG_N (2)
|
||||
#endif
|
||||
#ifndef SREG_V
|
||||
# define SREG_V (3)
|
||||
#endif
|
||||
#ifndef SREG_S
|
||||
# define SREG_S (4)
|
||||
#endif
|
||||
#ifndef SREG_H
|
||||
# define SREG_H (5)
|
||||
#endif
|
||||
#ifndef SREG_T
|
||||
# define SREG_T (6)
|
||||
#endif
|
||||
#ifndef SREG_I
|
||||
# define SREG_I (7)
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__COMPILING_AVR_LIBC__)
|
||||
|
||||
/* AVR 6 Architecture */
|
||||
# if __AVR_ARCH__ == 6
|
||||
# ifndef EIND
|
||||
# define EIND _SFR_IO8(0X3C)
|
||||
# endif
|
||||
/* XMEGA Architectures */
|
||||
# elif __AVR_ARCH__ >= 100
|
||||
# ifndef EIND
|
||||
# define EIND _SFR_MEM8(0x3C)
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/*
|
||||
Only few devices come without EEPROM. In order to assemble the
|
||||
EEPROM library components without defining a specific device, we
|
||||
keep the EEPROM-related definitions here.
|
||||
*/
|
||||
|
||||
/* EEPROM Control Register */
|
||||
# ifndef EECR
|
||||
# define EECR _SFR_IO8(0x1C)
|
||||
# endif
|
||||
|
||||
/* EEPROM Data Register */
|
||||
# ifndef EEDR
|
||||
# define EEDR _SFR_IO8(0x1D)
|
||||
# endif
|
||||
|
||||
/* EEPROM Address Register */
|
||||
# ifndef EEAR
|
||||
# define EEAR _SFR_IO16(0x1E)
|
||||
# endif
|
||||
# ifndef EEARL
|
||||
# define EEARL _SFR_IO8(0x1E)
|
||||
# endif
|
||||
# ifndef EEARH
|
||||
# define EEARH _SFR_IO8(0x1F)
|
||||
# endif
|
||||
|
||||
/* EEPROM Control Register bits */
|
||||
# ifndef EERE
|
||||
# define EERE (0)
|
||||
# endif
|
||||
# ifndef EEWE
|
||||
# define EEWE (1)
|
||||
# endif
|
||||
# ifndef EEMWE
|
||||
# define EEMWE (2)
|
||||
# endif
|
||||
# ifndef EERIE
|
||||
# define EERIE (3)
|
||||
# endif
|
||||
|
||||
#endif /* __COMPILING_AVR_LIBC__ */
|
||||
|
||||
|
||||
|
||||
/*------------ Common Symbols ------------*/
|
||||
|
||||
/*
|
||||
Generic definitions for registers that are common across multiple AVR devices
|
||||
and families.
|
||||
*/
|
||||
|
||||
/* Pointer registers definitions */
|
||||
#if __AVR_ARCH__ != 1 /* avr1 does not have X and Y pointers */
|
||||
# define XL r26
|
||||
# define XH r27
|
||||
# define YL r28
|
||||
# define YH r29
|
||||
#endif /* #if __AVR_ARCH__ != 1 */
|
||||
#define ZL r30
|
||||
#define ZH r31
|
||||
|
||||
|
||||
/* Status Register */
|
||||
#if defined(SREG)
|
||||
# define AVR_STATUS_REG SREG
|
||||
# if __AVR_ARCH__ >= 100
|
||||
# define AVR_STATUS_ADDR _SFR_MEM_ADDR(SREG)
|
||||
# else
|
||||
# define AVR_STATUS_ADDR _SFR_IO_ADDR(SREG)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Stack Pointer (combined) Register */
|
||||
#if defined(SP)
|
||||
# define AVR_STACK_POINTER_REG SP
|
||||
# if __AVR_ARCH__ >= 100
|
||||
# define AVR_STACK_POINTER_ADDR _SFR_MEM_ADDR(SP)
|
||||
# else
|
||||
# define AVR_STACK_POINTER_ADDR _SFR_IO_ADDR(SP)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Stack Pointer High Register */
|
||||
#if defined(SPH)
|
||||
# define _HAVE_AVR_STACK_POINTER_HI 1
|
||||
# define AVR_STACK_POINTER_HI_REG SPH
|
||||
# if __AVR_ARCH__ >= 100
|
||||
# define AVR_STACK_POINTER_HI_ADDR _SFR_MEM_ADDR(SPH)
|
||||
# else
|
||||
# define AVR_STACK_POINTER_HI_ADDR _SFR_IO_ADDR(SPH)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Stack Pointer Low Register */
|
||||
#if defined(SPL)
|
||||
# define AVR_STACK_POINTER_LO_REG SPL
|
||||
# if __AVR_ARCH__ >= 100
|
||||
# define AVR_STACK_POINTER_LO_ADDR _SFR_MEM_ADDR(SPL)
|
||||
# else
|
||||
# define AVR_STACK_POINTER_LO_ADDR _SFR_IO_ADDR(SPL)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* RAMPZ Register */
|
||||
#if defined(RAMPZ)
|
||||
# define AVR_RAMPZ_REG RAMPZ
|
||||
# if __AVR_ARCH__ >= 100
|
||||
# define AVR_RAMPZ_ADDR _SFR_MEM_ADDR(RAMPZ)
|
||||
# else
|
||||
# define AVR_RAMPZ_ADDR _SFR_IO_ADDR(RAMPZ)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Extended Indirect Register */
|
||||
#if defined(EIND)
|
||||
# define AVR_EXTENDED_INDIRECT_REG EIND
|
||||
# if __AVR_ARCH__ >= 100
|
||||
# define AVR_EXTENDED_INDIRECT_ADDR _SFR_MEM_ADDR(EIND)
|
||||
# else
|
||||
# define AVR_EXTENDED_INDIRECT_ADDR _SFR_IO_ADDR(EIND)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*------------ Workaround to old compilers (4.1.2 and earlier) ------------*/
|
||||
|
||||
#ifndef __AVR_HAVE_MOVW__
|
||||
# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
|
||||
# define __AVR_HAVE_MOVW__ 1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef __AVR_HAVE_LPMX__
|
||||
# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
|
||||
# define __AVR_HAVE_LPMX__ 1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef __AVR_HAVE_MUL__
|
||||
# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
|
||||
# define __AVR_HAVE_MUL__ 1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* _AVR_COMMON_H */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/* Copyright (c) 2005 Joerg Wunsch
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: crc16.h,v 1.10 2005/11/05 22:23:15 joerg_wunsch Exp $ */
|
||||
|
||||
#ifndef _AVR_CRC16_H_
|
||||
#define _AVR_CRC16_H_
|
||||
|
||||
#warning "This file has been moved to <util/crc16.h>."
|
||||
#include <util/crc16.h>
|
||||
|
||||
#endif /* _AVR_CRC16_H_ */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/* Copyright (c) 2005 Joerg Wunsch
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: delay.h,v 1.14 2005/11/05 22:23:15 joerg_wunsch Exp $ */
|
||||
|
||||
#ifndef _AVR_DELAY_H_
|
||||
#define _AVR_DELAY_H_
|
||||
|
||||
#warning "This file has been moved to <util/delay.h>."
|
||||
#include <util/delay.h>
|
||||
|
||||
#endif /* _AVR_DELAY_H_ */
|
||||
423
arduino-0018-windows/hardware/tools/avr/avr/include/avr/eeprom.h
Normal file
423
arduino-0018-windows/hardware/tools/avr/avr/include/avr/eeprom.h
Normal file
|
|
@ -0,0 +1,423 @@
|
|||
/* Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz
|
||||
Copyright (c) 2005, 2006 Bjoern Haase
|
||||
Copyright (c) 2008 Atmel Corporation
|
||||
Copyright (c) 2008 Wouter van Gulik
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: eeprom.h,v 1.21.2.6 2008/08/19 22:10:39 arcanum Exp $ */
|
||||
|
||||
#ifndef _AVR_EEPROM_H_
|
||||
#define _AVR_EEPROM_H_ 1
|
||||
|
||||
#include <avr/io.h>
|
||||
#include <stddef.h> /* size_t */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ATTR_PURE__
|
||||
# ifdef __DOXYGEN__
|
||||
# define __ATTR_PURE__
|
||||
# else
|
||||
# define __ATTR_PURE__ __attribute__((__pure__))
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
|
||||
uint16_t __eerd_word (const uint16_t *, uint8_t (*)(const uint8_t *))
|
||||
__ATTR_PURE__;
|
||||
uint32_t __eerd_dword (const uint32_t *, uint8_t (*)(const uint8_t *))
|
||||
__ATTR_PURE__;
|
||||
void __eerd_block (void *, const void *, size_t, uint8_t (*)(const uint8_t *));
|
||||
|
||||
void __eewr_word (uint16_t *, uint16_t, void (*)(uint8_t *, uint8_t));
|
||||
void __eewr_dword (uint32_t *, uint32_t, void (*)(uint8_t *, uint8_t));
|
||||
void __eewr_block (void *, const void *, size_t, void (*)(uint8_t *, uint8_t));
|
||||
#endif /* (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) ) */
|
||||
|
||||
#if !E2END && !defined(__DOXYGEN__)
|
||||
# ifndef __COMPILING_AVR_LIBC__
|
||||
# warning "Device does not have EEPROM available."
|
||||
# endif
|
||||
/* Omit below for chips without EEPROM. */
|
||||
|
||||
#else
|
||||
|
||||
/** \defgroup avr_eeprom <avr/eeprom.h>: EEPROM handling
|
||||
\code #include <avr/eeprom.h> \endcode
|
||||
|
||||
This header file declares the interface to some simple library
|
||||
routines suitable for handling the data EEPROM contained in the
|
||||
AVR microcontrollers. The implementation uses a simple polled
|
||||
mode interface. Applications that require interrupt-controlled
|
||||
EEPROM access to ensure that no time will be wasted in spinloops
|
||||
will have to deploy their own implementation.
|
||||
|
||||
\note All of the read/write functions first make sure the EEPROM
|
||||
is ready to be accessed. Since this may cause long delays if a
|
||||
write operation is still pending, time-critical applications
|
||||
should first poll the EEPROM e. g. using eeprom_is_ready() before
|
||||
attempting any actual I/O. But this functions are not wait until
|
||||
SELFPRGEN in SPMCSR becomes zero. Do this manually, if your
|
||||
softwate contains the Flash burning.
|
||||
|
||||
\note As these functions modify IO registers, they are known to be
|
||||
non-reentrant. If any of these functions are used from both,
|
||||
standard and interrupt context, the applications must ensure
|
||||
proper protection (e.g. by disabling interrupts before accessing
|
||||
them).
|
||||
|
||||
\note All write functions force erase_and_write programming mode.
|
||||
*/
|
||||
|
||||
/** \def EEMEM
|
||||
\ingroup avr_eeprom
|
||||
Attribute expression causing a variable to be allocated within the
|
||||
.eeprom section. */
|
||||
#define EEMEM __attribute__((section(".eeprom")))
|
||||
|
||||
|
||||
/* Register definitions */
|
||||
|
||||
/* Check for aliases. */
|
||||
#if !defined(EEWE) && defined(EEPE)
|
||||
# define EEWE EEPE
|
||||
#endif
|
||||
|
||||
#if !defined(EEMWE) && defined(EEMPE)
|
||||
# define EEMWE EEMPE
|
||||
#endif
|
||||
|
||||
#if !defined(EECR) && defined(DEECR)
|
||||
/* AT86RF401 */
|
||||
# define EECR DEECR
|
||||
# define EEAR DEEAR
|
||||
# define EEARL DEEAR
|
||||
# define EEDR DEEDR
|
||||
# define EERE EER
|
||||
# define EEWE EEL
|
||||
# define EEMWE EEU
|
||||
#endif
|
||||
|
||||
|
||||
#if !defined(EECR) || !defined(EEDR) || !defined(EEARL)
|
||||
|
||||
# if !defined(__EEPROM_REG_LOCATIONS__) \
|
||||
&& !defined(EEPROM_REG_LOCATIONS_OVERRIDE)
|
||||
/* 6-byte string denoting where to find the EEPROM registers in memory
|
||||
space. Adresses denoted in hex syntax with uppercase letters. Used
|
||||
by the EEPROM subroutines.
|
||||
First two letters: EECR address.
|
||||
Second two letters: EEDR address.
|
||||
Last two letters: EEAR address.
|
||||
*/
|
||||
# error "Unknown EEPROM register(s) location."
|
||||
# endif
|
||||
|
||||
/* If needed, override the locations defined in the IO headers. */
|
||||
# ifdef EEPROM_REG_LOCATIONS_OVERRIDE
|
||||
# undef __EEPROM_REG_LOCATIONS__
|
||||
# define __EEPROM_REG_LOCATIONS__ EEPROM_REG_LOCATIONS_OVERRIDE
|
||||
# endif
|
||||
|
||||
# define CONCAT1(a, b) CONCAT2(a, b)
|
||||
# define CONCAT2(a, b) a ## b
|
||||
# define HEXNR CONCAT1(0x, __EEPROM_REG_LOCATIONS__)
|
||||
|
||||
# undef EECR
|
||||
# define EECR _SFR_IO8((HEXNR >> 16) & 0xFF)
|
||||
|
||||
# undef EEDR
|
||||
# define EEDR _SFR_IO8((HEXNR >> 8) & 0xFF)
|
||||
|
||||
# undef EEAR
|
||||
# define EEAR _SFR_IO8(HEXNR & 0xFF)
|
||||
|
||||
# undef EEARH
|
||||
|
||||
# undef EEARL
|
||||
# define EEARL EEAR
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/** \def eeprom_is_ready
|
||||
\ingroup avr_eeprom
|
||||
\returns 1 if EEPROM is ready for a new read/write operation, 0 if not.
|
||||
*/
|
||||
#if defined(__DOXYGEN__)
|
||||
# define eeprom_is_ready()
|
||||
#elif defined(DEECR)
|
||||
# define eeprom_is_ready() bit_is_clear(DEECR, BSY)
|
||||
#else
|
||||
# define eeprom_is_ready() bit_is_clear(EECR, EEWE)
|
||||
#endif
|
||||
|
||||
|
||||
/** \def eeprom_busy_wait
|
||||
\ingroup avr_eeprom
|
||||
Loops until the eeprom is no longer busy.
|
||||
\returns Nothing.
|
||||
*/
|
||||
#define eeprom_busy_wait() do {} while (!eeprom_is_ready())
|
||||
|
||||
|
||||
/** \ingroup avr_eeprom
|
||||
Read one byte from EEPROM address \a __p.
|
||||
*/
|
||||
__ATTR_PURE__ static __inline__ uint8_t eeprom_read_byte (const uint8_t *__p)
|
||||
{
|
||||
do {} while (!eeprom_is_ready ());
|
||||
#if E2END <= 0xFF
|
||||
EEARL = (uint8_t)__p;
|
||||
#else
|
||||
EEAR = (uint16_t)__p;
|
||||
#endif
|
||||
/* Use inline assembly below as some AVRs have problems with accessing
|
||||
EECR with STS instructions. For example, see errata for ATmega64.
|
||||
The code below also assumes that EECR and EEDR are in the I/O space.
|
||||
*/
|
||||
uint8_t __result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"/* START EEPROM READ CRITICAL SECTION */ \n\t"
|
||||
"sbi %1, %2 \n\t"
|
||||
"in %0, %3 \n\t"
|
||||
"/* END EEPROM READ CRITICAL SECTION */ \n\t"
|
||||
: "=r" (__result)
|
||||
: "i" (_SFR_IO_ADDR(EECR)),
|
||||
"i" (EERE),
|
||||
"i" (_SFR_IO_ADDR(EEDR))
|
||||
);
|
||||
return __result;
|
||||
}
|
||||
|
||||
/** \ingroup avr_eeprom
|
||||
Read one 16-bit word (little endian) from EEPROM address \a __p.
|
||||
*/
|
||||
__ATTR_PURE__ static __inline__ uint16_t eeprom_read_word (const uint16_t *__p)
|
||||
{
|
||||
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
|
||||
return __eerd_word (__p, eeprom_read_byte);
|
||||
#else
|
||||
/* If ATmega256x device, do not call function. */
|
||||
union
|
||||
{
|
||||
uint16_t word;
|
||||
struct
|
||||
{
|
||||
uint8_t lo;
|
||||
uint8_t hi;
|
||||
} byte;
|
||||
} x;
|
||||
|
||||
x.byte.lo = eeprom_read_byte ((const uint8_t *)__p);
|
||||
x.byte.hi = eeprom_read_byte ((const uint8_t *)__p + 1);
|
||||
return x.word;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \ingroup avr_eeprom
|
||||
Read one 32-bit double word (little endian) from EEPROM address \a __p.
|
||||
*/
|
||||
__ATTR_PURE__ static __inline__
|
||||
uint32_t eeprom_read_dword (const uint32_t *__p)
|
||||
{
|
||||
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
|
||||
return __eerd_dword (__p, eeprom_read_byte);
|
||||
#else
|
||||
/* If ATmega256x device, do not call function. */
|
||||
union
|
||||
{
|
||||
uint32_t dword;
|
||||
struct
|
||||
{
|
||||
uint8_t byte0;
|
||||
uint8_t byte1;
|
||||
uint8_t byte2;
|
||||
uint8_t byte3;
|
||||
} byte;
|
||||
} x;
|
||||
|
||||
x.byte.byte0 = eeprom_read_byte ((const uint8_t *)__p);
|
||||
x.byte.byte1 = eeprom_read_byte ((const uint8_t *)__p + 1);
|
||||
x.byte.byte2 = eeprom_read_byte ((const uint8_t *)__p + 2);
|
||||
x.byte.byte3 = eeprom_read_byte ((const uint8_t *)__p + 3);
|
||||
return x.dword;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \ingroup avr_eeprom
|
||||
Read a block of \a __n bytes from EEPROM address \a __src to SRAM
|
||||
\a __dst.
|
||||
*/
|
||||
static __inline__ void
|
||||
eeprom_read_block (void *__dst, const void *__src, size_t __n)
|
||||
{
|
||||
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
|
||||
__eerd_block (__dst, __src, __n, eeprom_read_byte);
|
||||
#else
|
||||
/* If ATmega256x device, do not call function. */
|
||||
while (__n--)
|
||||
{
|
||||
*(char *)__dst++ = eeprom_read_byte(__src++);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \ingroup avr_eeprom
|
||||
Write a byte \a __value to EEPROM address \a __p.
|
||||
*/
|
||||
static __inline__ void eeprom_write_byte (uint8_t *__p, uint8_t __value)
|
||||
{
|
||||
do {} while (!eeprom_is_ready ());
|
||||
|
||||
#if defined(EEPM0) && defined(EEPM1)
|
||||
EECR = 0; /* Set programming mode: erase and write. */
|
||||
#elif defined(EEPM0) || defined(EEPM1)
|
||||
# warning "Unknown EECR register, eeprom_write_byte() has become outdated."
|
||||
#endif
|
||||
|
||||
#if E2END <= 0xFF
|
||||
EEARL = (unsigned)__p;
|
||||
#else
|
||||
EEAR = (unsigned)__p;
|
||||
#endif
|
||||
EEDR = __value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"/* START EEPROM WRITE CRITICAL SECTION */\n\t"
|
||||
"in r0, %[__sreg] \n\t"
|
||||
"cli \n\t"
|
||||
"sbi %[__eecr], %[__eemwe] \n\t"
|
||||
"sbi %[__eecr], %[__eewe] \n\t"
|
||||
"out %[__sreg], r0 \n\t"
|
||||
"/* END EEPROM WRITE CRITICAL SECTION */"
|
||||
:
|
||||
: [__eecr] "i" (_SFR_IO_ADDR(EECR)),
|
||||
[__sreg] "i" (_SFR_IO_ADDR(SREG)),
|
||||
[__eemwe] "i" (EEMWE),
|
||||
[__eewe] "i" (EEWE)
|
||||
: "r0"
|
||||
);
|
||||
}
|
||||
|
||||
/** \ingroup avr_eeprom
|
||||
Write a word \a __value to EEPROM address \a __p.
|
||||
*/
|
||||
static __inline__ void eeprom_write_word (uint16_t *__p, uint16_t __value)
|
||||
{
|
||||
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
|
||||
__eewr_word (__p, __value, eeprom_write_byte);
|
||||
#else
|
||||
/* If ATmega256x device, do not call function. */
|
||||
union
|
||||
{
|
||||
uint16_t word;
|
||||
struct
|
||||
{
|
||||
uint8_t lo;
|
||||
uint8_t hi;
|
||||
} byte;
|
||||
} x;
|
||||
|
||||
x.word = __value;
|
||||
eeprom_write_byte ((uint8_t *)__p, x.byte.lo);
|
||||
eeprom_write_byte ((uint8_t *)__p + 1, x.byte.hi);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \ingroup avr_eeprom
|
||||
Write a 32-bit double word \a __value to EEPROM address \a __p.
|
||||
*/
|
||||
static __inline__ void eeprom_write_dword (uint32_t *__p, uint32_t __value)
|
||||
{
|
||||
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
|
||||
__eewr_dword (__p, __value, eeprom_write_byte);
|
||||
#else
|
||||
/* If ATmega256x device, do not call function. */
|
||||
union
|
||||
{
|
||||
uint32_t dword;
|
||||
struct
|
||||
{
|
||||
uint8_t byte0;
|
||||
uint8_t byte1;
|
||||
uint8_t byte2;
|
||||
uint8_t byte3;
|
||||
} byte;
|
||||
} x;
|
||||
|
||||
x.dword = __value;
|
||||
eeprom_write_byte ((uint8_t *)__p, x.byte.byte0);
|
||||
eeprom_write_byte ((uint8_t *)__p + 1, x.byte.byte1);
|
||||
eeprom_write_byte ((uint8_t *)__p + 2, x.byte.byte2);
|
||||
eeprom_write_byte ((uint8_t *)__p + 3, x.byte.byte3);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \ingroup avr_eeprom
|
||||
Write a block of \a __n bytes to EEPROM address \a __dst from \a __src.
|
||||
\note The argument order is mismatch with common functions like strcpy().
|
||||
*/
|
||||
static __inline__ void
|
||||
eeprom_write_block (const void *__src, void *__dst, size_t __n)
|
||||
{
|
||||
#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
|
||||
__eewr_block (__dst, __src, __n, eeprom_write_byte);
|
||||
#else
|
||||
/* If ATmega256x device, do not call function. */
|
||||
while (__n--)
|
||||
eeprom_write_byte (__dst++, *(uint8_t *)__src++);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \name IAR C compatibility defines */
|
||||
/*@{*/
|
||||
|
||||
/** \def _EEPUT
|
||||
\ingroup avr_eeprom
|
||||
Write a byte to EEPROM. Compatibility define for IAR C. */
|
||||
#define _EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
|
||||
|
||||
/** \def _EEGET
|
||||
\ingroup avr_eeprom
|
||||
Read a byte from EEPROM. Compatibility define for IAR C. */
|
||||
#define _EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* E2END || defined(__DOXYGEN__) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !_AVR_EEPROM_H */
|
||||
264
arduino-0018-windows/hardware/tools/avr/avr/include/avr/fuse.h
Normal file
264
arduino-0018-windows/hardware/tools/avr/avr/include/avr/fuse.h
Normal file
|
|
@ -0,0 +1,264 @@
|
|||
/* Copyright (c) 2007, Atmel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: fuse.h,v 1.3.2.5 2008/07/18 20:32:14 arcanum Exp $ */
|
||||
|
||||
/* avr/fuse.h - Fuse API */
|
||||
|
||||
#ifndef _AVR_FUSE_H_
|
||||
#define _AVR_FUSE_H_ 1
|
||||
|
||||
|
||||
/** \file */
|
||||
/** \defgroup avr_fuse <avr/fuse.h>: Fuse Support
|
||||
|
||||
\par Introduction
|
||||
|
||||
The Fuse API allows a user to specify the fuse settings for the specific
|
||||
AVR device they are compiling for. These fuse settings will be placed
|
||||
in a special section in the ELF output file, after linking.
|
||||
|
||||
Programming tools can take advantage of the fuse information embedded in
|
||||
the ELF file, by extracting this information and determining if the fuses
|
||||
need to be programmed before programming the Flash and EEPROM memories.
|
||||
This also allows a single ELF file to contain all the
|
||||
information needed to program an AVR.
|
||||
|
||||
To use the Fuse API, include the <avr/io.h> header file, which in turn
|
||||
automatically includes the individual I/O header file and the <avr/fuse.h>
|
||||
file. These other two files provides everything necessary to set the AVR
|
||||
fuses.
|
||||
|
||||
\par Fuse API
|
||||
|
||||
Each I/O header file must define the FUSE_MEMORY_SIZE macro which is
|
||||
defined to the number of fuse bytes that exist in the AVR device.
|
||||
|
||||
A new type, __fuse_t, is defined as a structure. The number of fields in
|
||||
this structure are determined by the number of fuse bytes in the
|
||||
FUSE_MEMORY_SIZE macro.
|
||||
|
||||
If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type
|
||||
unsigned char.
|
||||
|
||||
If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type
|
||||
unsigned char.
|
||||
|
||||
If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended,
|
||||
of type unsigned char.
|
||||
|
||||
If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array
|
||||
of unsigned char with the size of the array being FUSE_MEMORY_SIZE.
|
||||
|
||||
A convenience macro, FUSEMEM, is defined as a GCC attribute for a
|
||||
custom-named section of ".fuse".
|
||||
|
||||
A convenience macro, FUSES, is defined that declares a variable, __fuse, of
|
||||
type __fuse_t with the attribute defined by FUSEMEM. This variable
|
||||
allows the end user to easily set the fuse data.
|
||||
|
||||
\note If a device-specific I/O header file has previously defined FUSEMEM,
|
||||
then FUSEMEM is not redefined. If a device-specific I/O header file has
|
||||
previously defined FUSES, then FUSES is not redefined.
|
||||
|
||||
Each AVR device I/O header file has a set of defined macros which specify the
|
||||
actual fuse bits available on that device. The AVR fuses have inverted
|
||||
values, logical 1 for an unprogrammed (disabled) bit and logical 0 for a
|
||||
programmed (enabled) bit. The defined macros for each individual fuse
|
||||
bit represent this in their definition by a bit-wise inversion of a mask.
|
||||
For example, the FUSE_EESAVE fuse in the ATmega128 is defined as:
|
||||
\code
|
||||
#define FUSE_EESAVE ~_BV(3)
|
||||
\endcode
|
||||
\note The _BV macro creates a bit mask from a bit number. It is then
|
||||
inverted to represent logical values for a fuse memory byte.
|
||||
|
||||
To combine the fuse bits macros together to represent a whole fuse byte,
|
||||
use the bitwise AND operator, like so:
|
||||
\code
|
||||
(FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN)
|
||||
\endcode
|
||||
|
||||
Each device I/O header file also defines macros that provide default values
|
||||
for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low
|
||||
Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT
|
||||
is defined for an Extended Fuse byte.
|
||||
|
||||
If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that
|
||||
provide default values for each fuse byte like so:
|
||||
FUSE0_DEFAULT
|
||||
FUSE1_DEFAULT
|
||||
FUSE2_DEFAULT
|
||||
FUSE3_DEFAULT
|
||||
FUSE4_DEFAULT
|
||||
....
|
||||
|
||||
\par API Usage Example
|
||||
|
||||
Putting all of this together is easy. Using C99's designated initializers:
|
||||
|
||||
\code
|
||||
#include <avr/io.h>
|
||||
|
||||
FUSES =
|
||||
{
|
||||
.low = LFUSE_DEFAULT,
|
||||
.high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
|
||||
.extended = EFUSE_DEFAULT,
|
||||
};
|
||||
|
||||
int main(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
\endcode
|
||||
|
||||
Or, using the variable directly instead of the FUSES macro,
|
||||
|
||||
\code
|
||||
#include <avr/io.h>
|
||||
|
||||
__fuse_t __fuse __attribute__((section (".fuse"))) =
|
||||
{
|
||||
.low = LFUSE_DEFAULT,
|
||||
.high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
|
||||
.extended = EFUSE_DEFAULT,
|
||||
};
|
||||
|
||||
int main(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
\endcode
|
||||
|
||||
If you are compiling in C++, you cannot use the designated intializers so
|
||||
you must do:
|
||||
|
||||
\code
|
||||
#include <avr/io.h>
|
||||
|
||||
FUSES =
|
||||
{
|
||||
LFUSE_DEFAULT, // .low
|
||||
(FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high
|
||||
EFUSE_DEFAULT, // .extended
|
||||
};
|
||||
|
||||
int main(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
\endcode
|
||||
|
||||
|
||||
However there are a number of caveats that you need to be aware of to
|
||||
use this API properly.
|
||||
|
||||
Be sure to include <avr/io.h> to get all of the definitions for the API.
|
||||
The FUSES macro defines a global variable to store the fuse data. This
|
||||
variable is assigned to its own linker section. Assign the desired fuse
|
||||
values immediately in the variable initialization.
|
||||
|
||||
The .fuse section in the ELF file will get its values from the initial
|
||||
variable assignment ONLY. This means that you can NOT assign values to
|
||||
this variable in functions and the new values will not be put into the
|
||||
ELF .fuse section.
|
||||
|
||||
The global variable is declared in the FUSES macro has two leading
|
||||
underscores, which means that it is reserved for the "implementation",
|
||||
meaning the library, so it will not conflict with a user-named variable.
|
||||
|
||||
You must initialize ALL fields in the __fuse_t structure. This is because
|
||||
the fuse bits in all bytes default to a logical 1, meaning unprogrammed.
|
||||
Normal uninitialized data defaults to all locgial zeros. So it is vital that
|
||||
all fuse bytes are initialized, even with default data. If they are not,
|
||||
then the fuse bits may not programmed to the desired settings.
|
||||
|
||||
Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
|
||||
your linker command line to have the correct device selected and to have
|
||||
the correct I/O header file included when you include <avr/io.h>.
|
||||
|
||||
You can print out the contents of the .fuse section in the ELF file by
|
||||
using this command line:
|
||||
\code
|
||||
avr-objdump -s -j .fuse <ELF file>
|
||||
\endcode
|
||||
The section contents shows the address on the left, then the data going from
|
||||
lower address to a higher address, left to right.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#ifndef FUSEMEM
|
||||
#define FUSEMEM __attribute__((section (".fuse")))
|
||||
#endif
|
||||
|
||||
#if FUSE_MEMORY_SIZE > 3
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned char byte[FUSE_MEMORY_SIZE];
|
||||
} __fuse_t;
|
||||
|
||||
|
||||
#elif FUSE_MEMORY_SIZE == 3
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned char low;
|
||||
unsigned char high;
|
||||
unsigned char extended;
|
||||
} __fuse_t;
|
||||
|
||||
#elif FUSE_MEMORY_SIZE == 2
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned char low;
|
||||
unsigned char high;
|
||||
} __fuse_t;
|
||||
|
||||
#elif FUSE_MEMORY_SIZE == 1
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned char byte;
|
||||
} __fuse_t;
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef FUSES
|
||||
#define FUSES __fuse_t __fuse FUSEMEM
|
||||
#endif
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
#endif /* _AVR_FUSE_H_ */
|
||||
|
|
@ -0,0 +1,344 @@
|
|||
/* Copyright (c) 2002,2005,2007 Marek Michalkiewicz
|
||||
Copyright (c) 2007, Dean Camera
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: interrupt.h,v 1.25.2.1 2008/01/05 06:33:11 dmix Exp $ */
|
||||
|
||||
#ifndef _AVR_INTERRUPT_H_
|
||||
#define _AVR_INTERRUPT_H_
|
||||
|
||||
#include <avr/io.h>
|
||||
|
||||
#if !defined(__DOXYGEN__) && !defined(__STRINGIFY)
|
||||
/* Auxiliary macro for ISR_ALIAS(). */
|
||||
#define __STRINGIFY(x) #x
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/**
|
||||
\file
|
||||
\@{
|
||||
*/
|
||||
|
||||
|
||||
/** \name Global manipulation of the interrupt flag
|
||||
|
||||
The global interrupt flag is maintained in the I bit of the status
|
||||
register (SREG).
|
||||
*/
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def sei()
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code #include <avr/interrupt.h> \endcode
|
||||
|
||||
Enables interrupts by setting the global interrupt mask. This function
|
||||
actually compiles into a single line of assembly, so there is no function
|
||||
call overhead. */
|
||||
#define sei()
|
||||
#else /* !DOXYGEN */
|
||||
# define sei() __asm__ __volatile__ ("sei" ::)
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def cli()
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code #include <avr/interrupt.h> \endcode
|
||||
|
||||
Disables all interrupts by clearing the global interrupt mask. This function
|
||||
actually compiles into a single line of assembly, so there is no function
|
||||
call overhead. */
|
||||
#define cli()
|
||||
#else /* !DOXYGEN */
|
||||
# define cli() __asm__ __volatile__ ("cli" ::)
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
|
||||
/** \name Macros for writing interrupt handler functions */
|
||||
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def ISR(vector [, attributes])
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code #include <avr/interrupt.h> \endcode
|
||||
|
||||
Introduces an interrupt handler function (interrupt service
|
||||
routine) that runs with global interrupts initially disabled
|
||||
by default with no attributes specified.
|
||||
|
||||
The attributes are optional and alter the behaviour and resultant
|
||||
generated code of the interrupt routine. Multiple attributes may
|
||||
be used for a single function, with a space seperating each
|
||||
attribute.
|
||||
|
||||
Valid attributes are ISR_BLOCK, ISR_NOBLOCK, ISR_NAKED and
|
||||
ISR_ALIASOF(vect).
|
||||
|
||||
\c vector must be one of the interrupt vector names that are
|
||||
valid for the particular MCU type.
|
||||
*/
|
||||
# define ISR(vector, [attributes])
|
||||
#else /* real code */
|
||||
|
||||
#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
|
||||
# define __INTR_ATTRS used, externally_visible
|
||||
#else /* GCC < 4.1 */
|
||||
# define __INTR_ATTRS used
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
# define ISR(vector, ...) \
|
||||
extern "C" void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
|
||||
void vector (void)
|
||||
#else
|
||||
# define ISR(vector, ...) \
|
||||
void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
|
||||
void vector (void)
|
||||
#endif
|
||||
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def SIGNAL(vector)
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code #include <avr/interrupt.h> \endcode
|
||||
|
||||
Introduces an interrupt handler function that runs with global interrupts
|
||||
initially disabled.
|
||||
|
||||
This is the same as the ISR macro without optional attributes.
|
||||
\deprecated Do not use SIGNAL() in new code. Use ISR() instead.
|
||||
*/
|
||||
# define SIGNAL(vector)
|
||||
#else /* real code */
|
||||
|
||||
#ifdef __cplusplus
|
||||
# define SIGNAL(vector) \
|
||||
extern "C" void vector(void) __attribute__ ((signal, __INTR_ATTRS)); \
|
||||
void vector (void)
|
||||
#else
|
||||
# define SIGNAL(vector) \
|
||||
void vector (void) __attribute__ ((signal, __INTR_ATTRS)); \
|
||||
void vector (void)
|
||||
#endif
|
||||
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def EMPTY_INTERRUPT(vector)
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code #include <avr/interrupt.h> \endcode
|
||||
|
||||
Defines an empty interrupt handler function. This will not generate
|
||||
any prolog or epilog code and will only return from the ISR. Do not
|
||||
define a function body as this will define it for you.
|
||||
Example:
|
||||
\code EMPTY_INTERRUPT(ADC_vect);\endcode */
|
||||
# define EMPTY_INTERRUPT(vector)
|
||||
#else /* real code */
|
||||
|
||||
#ifdef __cplusplus
|
||||
# define EMPTY_INTERRUPT(vector) \
|
||||
extern "C" void vector(void) __attribute__ ((signal,naked,__INTR_ATTRS)); \
|
||||
void vector (void) { __asm__ __volatile__ ("reti" ::); }
|
||||
#else
|
||||
# define EMPTY_INTERRUPT(vector) \
|
||||
void vector (void) __attribute__ ((signal,naked,__INTR_ATTRS)); \
|
||||
void vector (void) { __asm__ __volatile__ ("reti" ::); }
|
||||
#endif
|
||||
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def ISR_ALIAS(vector, target_vector)
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code #include <avr/interrupt.h> \endcode
|
||||
|
||||
Aliases a given vector to another one in the same manner as the
|
||||
ISR_ALIASOF attribute for the ISR() macro. Unlike the ISR_ALIASOF
|
||||
attribute macro however, this is compatible for all versions of
|
||||
GCC rather than just GCC version 4.2 onwards.
|
||||
|
||||
\note This macro creates a trampoline function for the aliased
|
||||
macro. This will result in a two cycle penalty for the aliased
|
||||
vector compared to the ISR the vector is aliased to, due to the
|
||||
JMP/RJMP opcode used.
|
||||
|
||||
\deprecated
|
||||
For new code, the use of ISR(..., ISR_ALIASOF(...)) is
|
||||
recommended.
|
||||
|
||||
Example:
|
||||
\code
|
||||
ISR(INT0_vect)
|
||||
{
|
||||
PORTB = 42;
|
||||
}
|
||||
|
||||
ISR_ALIAS(INT1_vect, INT0_vect);
|
||||
\endcode
|
||||
*/
|
||||
# define ISR_ALIAS(vector, target_vector)
|
||||
#else /* real code */
|
||||
|
||||
#ifdef __cplusplus
|
||||
# if defined(__AVR_MEGA__) && __AVR_MEGA__
|
||||
# define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \
|
||||
__attribute__((signal, naked, __INTR_ATTRS)); \
|
||||
void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); }
|
||||
# else /* !__AVR_MEGA */
|
||||
# define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \
|
||||
__attribute__((signal, naked, __INTR_ATTRS)); \
|
||||
void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); }
|
||||
# endif /* __AVR_MEGA__ */
|
||||
#else /* !__cplusplus */
|
||||
# if defined(__AVR_MEGA__) && __AVR_MEGA__
|
||||
# define ISR_ALIAS(vector, tgt) void vector (void) \
|
||||
__attribute__((signal, naked, __INTR_ATTRS)); \
|
||||
void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); }
|
||||
# else /* !__AVR_MEGA */
|
||||
# define ISR_ALIAS(vector, tgt) void vector (void) \
|
||||
__attribute__((signal, naked, __INTR_ATTRS)); \
|
||||
void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); }
|
||||
# endif /* __AVR_MEGA__ */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def reti()
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code #include <avr/interrupt.h> \endcode
|
||||
|
||||
Returns from an interrupt routine, enabling global interrupts. This should
|
||||
be the last command executed before leaving an ISR defined with the ISR_NAKED
|
||||
attribute.
|
||||
|
||||
This macro actually compiles into a single line of assembly, so there is
|
||||
no function call overhead.
|
||||
*/
|
||||
# define reti()
|
||||
#else /* !DOXYGEN */
|
||||
# define reti() __asm__ __volatile__ ("reti" ::)
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def BADISR_vect
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code #include <avr/interrupt.h> \endcode
|
||||
|
||||
This is a vector which is aliased to __vector_default, the vector
|
||||
executed when an ISR fires with no accompanying ISR handler. This
|
||||
may be used along with the ISR() macro to create a catch-all for
|
||||
undefined but used ISRs for debugging purposes.
|
||||
*/
|
||||
# define BADISR_vect
|
||||
#else /* !DOXYGEN */
|
||||
# define BADISR_vect __vector_default
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
/** \name ISR attributes */
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \def ISR_BLOCK
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code# include <avr/interrupt.h> \endcode
|
||||
|
||||
Identical to an ISR with no attributes specified. Global
|
||||
interrupts are initially disabled by the AVR hardware when
|
||||
entering the ISR, without the compiler modifying this state.
|
||||
|
||||
Use this attribute in the attributes parameter of the ISR macro.
|
||||
*/
|
||||
# define ISR_BLOCK
|
||||
|
||||
/** \def ISR_NOBLOCK
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code# include <avr/interrupt.h> \endcode
|
||||
|
||||
ISR runs with global interrupts initially enabled. The interrupt
|
||||
enable flag is activated by the compiler as early as possible
|
||||
within the ISR to ensure minimal processing delay for nested
|
||||
interrupts.
|
||||
|
||||
This may be used to create nested ISRs, however care should be
|
||||
taken to avoid stack overflows, or to avoid infinitely entering
|
||||
the ISR for those cases where the AVR hardware does not clear the
|
||||
respective interrupt flag before entering the ISR.
|
||||
|
||||
Use this attribute in the attributes parameter of the ISR macro.
|
||||
*/
|
||||
# define ISR_NOBLOCK
|
||||
|
||||
/** \def ISR_NAKED
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code# include <avr/interrupt.h> \endcode
|
||||
|
||||
ISR is created with no prologue or epilogue code. The user code is
|
||||
responsible for preservation of the machine state including the
|
||||
SREG register, as well as placing a reti() at the end of the
|
||||
interrupt routine.
|
||||
|
||||
Use this attribute in the attributes parameter of the ISR macro.
|
||||
*/
|
||||
# define ISR_NAKED
|
||||
|
||||
/** \def ISR_ALIASOF(target_vector)
|
||||
\ingroup avr_interrupts
|
||||
|
||||
\code#include <avr/interrupt.h>\endcode
|
||||
|
||||
The ISR is linked to another ISR, specified by the vect parameter.
|
||||
This is compatible with GCC 4.2 and greater only.
|
||||
|
||||
Use this attribute in the attributes parameter of the ISR macro.
|
||||
*/
|
||||
# define ISR_ALIASOF(target_vector)
|
||||
#else /* !DOXYGEN */
|
||||
# define ISR_BLOCK
|
||||
# define ISR_NOBLOCK __attribute__((interrupt))
|
||||
# define ISR_NAKED __attribute__((naked))
|
||||
# define ISR_ALIASOF(v) __attribute__((alias(__STRINGIFY(v))))
|
||||
#endif /* DOXYGEN */
|
||||
|
||||
/* \@} */
|
||||
|
||||
#endif
|
||||
346
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io.h
Normal file
346
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io.h
Normal file
|
|
@ -0,0 +1,346 @@
|
|||
/* Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch
|
||||
Copyright (c) 2007 Eric B. Weddington
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io.h,v 1.52.2.9 2008/11/03 04:13:14 arcanum Exp $ */
|
||||
|
||||
/** \file */
|
||||
/** \defgroup avr_io <avr/io.h>: AVR device-specific IO definitions
|
||||
\code #include <avr/io.h> \endcode
|
||||
|
||||
This header file includes the apropriate IO definitions for the
|
||||
device that has been specified by the <tt>-mmcu=</tt> compiler
|
||||
command-line switch. This is done by diverting to the appropriate
|
||||
file <tt><avr/io</tt><em>XXXX</em><tt>.h></tt> which should
|
||||
never be included directly. Some register names common to all
|
||||
AVR devices are defined directly within <tt><avr/common.h></tt>,
|
||||
which is included in <tt><avr/io.h></tt>,
|
||||
but most of the details come from the respective include file.
|
||||
|
||||
Note that this file always includes the following files:
|
||||
\code
|
||||
#include <avr/sfr_defs.h>
|
||||
#include <avr/portpins.h>
|
||||
#include <avr/common.h>
|
||||
#include <avr/version.h>
|
||||
\endcode
|
||||
See \ref avr_sfr for more details about that header file.
|
||||
|
||||
Included are definitions of the IO register set and their
|
||||
respective bit values as specified in the Atmel documentation.
|
||||
Note that inconsistencies in naming conventions,
|
||||
so even identical functions sometimes get different names on
|
||||
different devices.
|
||||
|
||||
Also included are the specific names useable for interrupt
|
||||
function definitions as documented
|
||||
\ref avr_signames "here".
|
||||
|
||||
Finally, the following macros are defined:
|
||||
|
||||
- \b RAMEND
|
||||
<br>
|
||||
The last on-chip RAM address.
|
||||
<br>
|
||||
- \b XRAMEND
|
||||
<br>
|
||||
The last possible RAM location that is addressable. This is equal to
|
||||
RAMEND for devices that do not allow for external RAM. For devices
|
||||
that allow external RAM, this will larger than RAMEND.
|
||||
<br>
|
||||
- \b E2END
|
||||
<br>
|
||||
The last EEPROM address.
|
||||
<br>
|
||||
- \b FLASHEND
|
||||
<br>
|
||||
The last byte address in the Flash program space.
|
||||
<br>
|
||||
- \b SPM_PAGESIZE
|
||||
<br>
|
||||
For devices with bootloader support, the flash pagesize
|
||||
(in bytes) to be used for the \c SPM instruction.
|
||||
- \b E2PAGESIZE
|
||||
<br>
|
||||
The size of the EEPROM page.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
#define _AVR_IO_H_
|
||||
|
||||
#include <avr/sfr_defs.h>
|
||||
|
||||
#if defined (__AVR_AT94K__)
|
||||
# include <avr/ioat94k.h>
|
||||
#elif defined (__AVR_AT43USB320__)
|
||||
# include <avr/io43u32x.h>
|
||||
#elif defined (__AVR_AT43USB355__)
|
||||
# include <avr/io43u35x.h>
|
||||
#elif defined (__AVR_AT76C711__)
|
||||
# include <avr/io76c711.h>
|
||||
#elif defined (__AVR_AT86RF401__)
|
||||
# include <avr/io86r401.h>
|
||||
#elif defined (__AVR_AT90PWM1__)
|
||||
# include <avr/io90pwm1.h>
|
||||
#elif defined (__AVR_AT90PWM2__)
|
||||
# include <avr/io90pwmx.h>
|
||||
#elif defined (__AVR_AT90PWM2B__)
|
||||
# include <avr/io90pwm2b.h>
|
||||
#elif defined (__AVR_AT90PWM3__)
|
||||
# include <avr/io90pwmx.h>
|
||||
#elif defined (__AVR_AT90PWM3B__)
|
||||
# include <avr/io90pwm3b.h>
|
||||
#elif defined (__AVR_AT90PWM216__)
|
||||
# include <avr/io90pwm216.h>
|
||||
#elif defined (__AVR_AT90PWM316__)
|
||||
# include <avr/io90pwm316.h>
|
||||
#elif defined (__AVR_ATmega32C1__)
|
||||
# include <avr/iom32c1.h>
|
||||
#elif defined (__AVR_ATmega32M1__)
|
||||
# include <avr/iom32m1.h>
|
||||
#elif defined (__AVR_ATmega32U4__)
|
||||
# include <avr/iom32u4.h>
|
||||
#elif defined (__AVR_ATmega32U6__)
|
||||
# include <avr/iom32u6.h>
|
||||
#elif defined (__AVR_ATmega128__)
|
||||
# include <avr/iom128.h>
|
||||
#elif defined (__AVR_ATmega1280__)
|
||||
# include <avr/iom1280.h>
|
||||
#elif defined (__AVR_ATmega1281__)
|
||||
# include <avr/iom1281.h>
|
||||
#elif defined (__AVR_ATmega1284P__)
|
||||
# include <avr/iom1284p.h>
|
||||
#elif defined (__AVR_ATmega2560__)
|
||||
# include <avr/iom2560.h>
|
||||
#elif defined (__AVR_ATmega2561__)
|
||||
# include <avr/iom2561.h>
|
||||
#elif defined (__AVR_AT90CAN32__)
|
||||
# include <avr/iocan32.h>
|
||||
#elif defined (__AVR_AT90CAN64__)
|
||||
# include <avr/iocan64.h>
|
||||
#elif defined (__AVR_AT90CAN128__)
|
||||
# include <avr/iocan128.h>
|
||||
#elif defined (__AVR_AT90USB82__)
|
||||
# include <avr/iousb82.h>
|
||||
#elif defined (__AVR_AT90USB162__)
|
||||
# include <avr/iousb162.h>
|
||||
#elif defined (__AVR_AT90USB646__)
|
||||
# include <avr/iousb646.h>
|
||||
#elif defined (__AVR_AT90USB647__)
|
||||
# include <avr/iousb647.h>
|
||||
#elif defined (__AVR_AT90USB1286__)
|
||||
# include <avr/iousb1286.h>
|
||||
#elif defined (__AVR_AT90USB1287__)
|
||||
# include <avr/iousb1287.h>
|
||||
#elif defined (__AVR_ATmega64__)
|
||||
# include <avr/iom64.h>
|
||||
#elif defined (__AVR_ATmega640__)
|
||||
# include <avr/iom640.h>
|
||||
#elif defined (__AVR_ATmega644__)
|
||||
# include <avr/iom644.h>
|
||||
#elif defined (__AVR_ATmega644P__)
|
||||
# include <avr/iom644.h>
|
||||
#elif defined (__AVR_ATmega645__)
|
||||
# include <avr/iom645.h>
|
||||
#elif defined (__AVR_ATmega6450__)
|
||||
# include <avr/iom6450.h>
|
||||
#elif defined (__AVR_ATmega649__)
|
||||
# include <avr/iom649.h>
|
||||
#elif defined (__AVR_ATmega6490__)
|
||||
# include <avr/iom6490.h>
|
||||
#elif defined (__AVR_ATmega103__)
|
||||
# include <avr/iom103.h>
|
||||
#elif defined (__AVR_ATmega32__)
|
||||
# include <avr/iom32.h>
|
||||
#elif defined (__AVR_ATmega323__)
|
||||
# include <avr/iom323.h>
|
||||
#elif defined (__AVR_ATmega324P__)
|
||||
# include <avr/iom324.h>
|
||||
#elif defined (__AVR_ATmega325__)
|
||||
# include <avr/iom325.h>
|
||||
#elif defined (__AVR_ATmega325P__)
|
||||
# include <avr/iom325.h>
|
||||
#elif defined (__AVR_ATmega3250__)
|
||||
# include <avr/iom3250.h>
|
||||
#elif defined (__AVR_ATmega3250P__)
|
||||
# include <avr/iom3250.h>
|
||||
#elif defined (__AVR_ATmega328P__)
|
||||
# include <avr/iom328p.h>
|
||||
#elif defined (__AVR_ATmega329__)
|
||||
# include <avr/iom329.h>
|
||||
#elif defined (__AVR_ATmega329P__)
|
||||
# include <avr/iom329.h>
|
||||
#elif defined (__AVR_ATmega3290__)
|
||||
# include <avr/iom3290.h>
|
||||
#elif defined (__AVR_ATmega3290P__)
|
||||
# include <avr/iom3290.h>
|
||||
#elif defined (__AVR_ATmega32HVB__)
|
||||
# include <avr/iom32hvb.h>
|
||||
#elif defined (__AVR_ATmega406__)
|
||||
# include <avr/iom406.h>
|
||||
#elif defined (__AVR_ATmega16__)
|
||||
# include <avr/iom16.h>
|
||||
#elif defined (__AVR_ATmega161__)
|
||||
# include <avr/iom161.h>
|
||||
#elif defined (__AVR_ATmega162__)
|
||||
# include <avr/iom162.h>
|
||||
#elif defined (__AVR_ATmega163__)
|
||||
# include <avr/iom163.h>
|
||||
#elif defined (__AVR_ATmega164P__)
|
||||
# include <avr/iom164.h>
|
||||
#elif defined (__AVR_ATmega165__)
|
||||
# include <avr/iom165.h>
|
||||
#elif defined (__AVR_ATmega165P__)
|
||||
# include <avr/iom165p.h>
|
||||
#elif defined (__AVR_ATmega168__)
|
||||
# include <avr/iom168.h>
|
||||
#elif defined (__AVR_ATmega168P__)
|
||||
# include <avr/iom168p.h>
|
||||
#elif defined (__AVR_ATmega169__)
|
||||
# include <avr/iom169.h>
|
||||
#elif defined (__AVR_ATmega169P__)
|
||||
# include <avr/iom169p.h>
|
||||
#elif defined (__AVR_ATmega8HVA__)
|
||||
# include <avr/iom8hva.h>
|
||||
#elif defined (__AVR_ATmega16HVA__)
|
||||
# include <avr/iom16hva.h>
|
||||
#elif defined (__AVR_ATmega8__)
|
||||
# include <avr/iom8.h>
|
||||
#elif defined (__AVR_ATmega48__)
|
||||
# include <avr/iom48.h>
|
||||
#elif defined (__AVR_ATmega48P__)
|
||||
# include <avr/iom48p.h>
|
||||
#elif defined (__AVR_ATmega88__)
|
||||
# include <avr/iom88.h>
|
||||
#elif defined (__AVR_ATmega88P__)
|
||||
# include <avr/iom88p.h>
|
||||
#elif defined (__AVR_ATmega8515__)
|
||||
# include <avr/iom8515.h>
|
||||
#elif defined (__AVR_ATmega8535__)
|
||||
# include <avr/iom8535.h>
|
||||
#elif defined (__AVR_AT90S8535__)
|
||||
# include <avr/io8535.h>
|
||||
#elif defined (__AVR_AT90C8534__)
|
||||
# include <avr/io8534.h>
|
||||
#elif defined (__AVR_AT90S8515__)
|
||||
# include <avr/io8515.h>
|
||||
#elif defined (__AVR_AT90S4434__)
|
||||
# include <avr/io4434.h>
|
||||
#elif defined (__AVR_AT90S4433__)
|
||||
# include <avr/io4433.h>
|
||||
#elif defined (__AVR_AT90S4414__)
|
||||
# include <avr/io4414.h>
|
||||
#elif defined (__AVR_ATtiny22__)
|
||||
# include <avr/iotn22.h>
|
||||
#elif defined (__AVR_ATtiny26__)
|
||||
# include <avr/iotn26.h>
|
||||
#elif defined (__AVR_AT90S2343__)
|
||||
# include <avr/io2343.h>
|
||||
#elif defined (__AVR_AT90S2333__)
|
||||
# include <avr/io2333.h>
|
||||
#elif defined (__AVR_AT90S2323__)
|
||||
# include <avr/io2323.h>
|
||||
#elif defined (__AVR_AT90S2313__)
|
||||
# include <avr/io2313.h>
|
||||
#elif defined (__AVR_ATtiny2313__)
|
||||
# include <avr/iotn2313.h>
|
||||
#elif defined (__AVR_ATtiny13__)
|
||||
# include <avr/iotn13.h>
|
||||
#elif defined (__AVR_ATtiny13A__)
|
||||
# include <avr/iotn13a.h>
|
||||
#elif defined (__AVR_ATtiny25__)
|
||||
# include <avr/iotn25.h>
|
||||
#elif defined (__AVR_ATtiny45__)
|
||||
# include <avr/iotn45.h>
|
||||
#elif defined (__AVR_ATtiny85__)
|
||||
# include <avr/iotn85.h>
|
||||
#elif defined (__AVR_ATtiny24__)
|
||||
# include <avr/iotn24.h>
|
||||
#elif defined (__AVR_ATtiny44__)
|
||||
# include <avr/iotn44.h>
|
||||
#elif defined (__AVR_ATtiny84__)
|
||||
# include <avr/iotn84.h>
|
||||
#elif defined (__AVR_ATtiny261__)
|
||||
# include <avr/iotn261.h>
|
||||
#elif defined (__AVR_ATtiny461__)
|
||||
# include <avr/iotn461.h>
|
||||
#elif defined (__AVR_ATtiny861__)
|
||||
# include <avr/iotn861.h>
|
||||
#elif defined (__AVR_ATtiny43U__)
|
||||
# include <avr/iotn43u.h>
|
||||
#elif defined (__AVR_ATtiny48__)
|
||||
# include <avr/iotn48.h>
|
||||
#elif defined (__AVR_ATtiny88__)
|
||||
# include <avr/iotn88.h>
|
||||
#elif defined (__AVR_ATtiny167__)
|
||||
# include <avr/iotn167.h>
|
||||
/* avr1: the following only supported for assembler programs */
|
||||
#elif defined (__AVR_ATtiny28__)
|
||||
# include <avr/iotn28.h>
|
||||
#elif defined (__AVR_AT90S1200__)
|
||||
# include <avr/io1200.h>
|
||||
#elif defined (__AVR_ATtiny15__)
|
||||
# include <avr/iotn15.h>
|
||||
#elif defined (__AVR_ATtiny12__)
|
||||
# include <avr/iotn12.h>
|
||||
#elif defined (__AVR_ATtiny11__)
|
||||
# include <avr/iotn11.h>
|
||||
#elif defined (__AVR_ATxmega64A1__)
|
||||
# include <avr/iox64a1.h>
|
||||
#elif defined (__AVR_ATxmega64A3__)
|
||||
# include <avr/iox64a3.h>
|
||||
#elif defined (__AVR_ATxmega128A1__)
|
||||
# include <avr/iox128a1.h>
|
||||
#elif defined (__AVR_ATxmega128A3__)
|
||||
# include <avr/iox128a3.h>
|
||||
#elif defined (__AVR_ATxmega256A3__)
|
||||
# include <avr/iox256a3.h>
|
||||
#elif defined (__AVR_ATxmega256A3B__)
|
||||
# include <avr/iox256a3b.h>
|
||||
#else
|
||||
# if !defined(__COMPILING_AVR_LIBC__)
|
||||
# warning "device type not defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#include <avr/portpins.h>
|
||||
|
||||
#include <avr/common.h>
|
||||
|
||||
#include <avr/version.h>
|
||||
|
||||
/* Include fuse.h after individual IO header files. */
|
||||
#include <avr/fuse.h>
|
||||
|
||||
/* Include lock.h after individual IO header files. */
|
||||
#include <avr/lock.h>
|
||||
|
||||
#endif /* _AVR_IO_H_ */
|
||||
270
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io1200.h
Normal file
270
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io1200.h
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io1200.h,v 1.8.4.3 2008/08/14 00:07:59 arcanum Exp $ */
|
||||
|
||||
/* avr/io1200.h - definitions for AT90S1200 */
|
||||
|
||||
#ifndef _AVR_IO1200_H_
|
||||
#define _AVR_IO1200_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io1200.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
# warning "MCU not supported by the C compiler"
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* 0x00..0x07 reserved */
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* 0x09..0x0F reserved */
|
||||
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* 0x13..0x15 reserved */
|
||||
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* 0x19..0x1B reserved */
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO8(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* 0x1F..0x20 reserved */
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* 0x22..0x31 reserved */
|
||||
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* 0x34 reserved */
|
||||
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* 0x36..0x37 reserved */
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK Register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* 0x3A reserved */
|
||||
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3C..0x3E reserved */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(2)
|
||||
#define SIG_OVERFLOW0 _VECTOR(2)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(3)
|
||||
#define SIG_COMPARATOR _VECTOR(3)
|
||||
|
||||
#define _VECTORS_SIZE 8
|
||||
|
||||
/* Bit numbers */
|
||||
|
||||
/* GIMSK */
|
||||
#define INT0 6
|
||||
|
||||
/* TIMSK */
|
||||
#define TOIE0 1
|
||||
|
||||
/* TIFR */
|
||||
#define TOV0 1
|
||||
|
||||
/* MCUCR */
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* TCCR0 */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* WDTCR */
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* EECR */
|
||||
#undef EEMWE
|
||||
|
||||
/*
|
||||
PB7 = SCK
|
||||
PB6 = MISO
|
||||
PB5 = MOSI
|
||||
PB1 = AIN1
|
||||
PB0 = AIN0
|
||||
*/
|
||||
|
||||
/* PORTB */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* DDRB */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* PINB */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* PORTD */
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* DDRD */
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* PIND */
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* ACSR */
|
||||
#define ACD 7
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
#undef ZH
|
||||
|
||||
/* Last memory addresses */
|
||||
#define RAMEND 0x1F
|
||||
#define XRAMEND 0x0
|
||||
#define E2END 0x3F
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x3FF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_RCEN (unsigned char)~_BV(0)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x90
|
||||
#define SIGNATURE_2 0x01
|
||||
|
||||
|
||||
#endif /* _AVR_IO1200_H_ */
|
||||
371
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io2313.h
Normal file
371
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io2313.h
Normal file
|
|
@ -0,0 +1,371 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io2313.h,v 1.10.2.3 2008/08/14 00:07:59 arcanum Exp $ */
|
||||
|
||||
/* avr/io2313.h - definitions for AT90S2313 */
|
||||
|
||||
#ifndef _AVR_IO2313_H_
|
||||
#define _AVR_IO2313_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io2313.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control Register */
|
||||
#define UCR _SFR_IO8(0x0A)
|
||||
|
||||
/* UART Status Register */
|
||||
#define USR _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO8(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x24)
|
||||
#define ICR1L _SFR_IO8(0x24)
|
||||
#define ICR1H _SFR_IO8(0x25)
|
||||
|
||||
/* Output Compare Register 1 */
|
||||
#define OCR1 _SFR_IO16(0x2A)
|
||||
#define OCR1L _SFR_IO8(0x2A)
|
||||
#define OCR1H _SFR_IO8(0x2B)
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3C..0x3D SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt Request 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt Request 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter1 Capture Event */
|
||||
#define TIMER1_CAPT1_vect _VECTOR(3)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter1 Compare Match */
|
||||
#define TIMER1_COMP1_vect _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF1_vect _VECTOR(5)
|
||||
#define SIG_OVERFLOW1 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF0_vect _VECTOR(6)
|
||||
#define SIG_OVERFLOW0 _VECTOR(6)
|
||||
|
||||
/* UART, Rx Complete */
|
||||
#define UART_RX_vect _VECTOR(7)
|
||||
#define SIG_UART_RECV _VECTOR(7)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(8)
|
||||
#define SIG_UART_DATA _VECTOR(8)
|
||||
|
||||
/* UART, Tx Complete */
|
||||
#define UART_TX_vect _VECTOR(9)
|
||||
#define SIG_UART_TRANS _VECTOR(9)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(10)
|
||||
#define SIG_COMPARATOR _VECTOR(10)
|
||||
|
||||
#define _VECTORS_SIZE 22
|
||||
|
||||
/*
|
||||
* The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TOIE1 7
|
||||
#define OCIE1A 6
|
||||
#define TICIE 3 /* old name */
|
||||
#define TICIE1 3
|
||||
#define TOIE0 1
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TOV1 7
|
||||
#define OCF1A 6
|
||||
#define ICF1 3
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACD 7
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0xDF
|
||||
#define XRAMEND 0xDF
|
||||
#define E2END 0x7F
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x07FF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_FSTRT (unsigned char)~_BV(0)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x91
|
||||
#define SIGNATURE_2 0x01
|
||||
|
||||
|
||||
#endif /* _AVR_IO2313_H_ */
|
||||
204
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io2323.h
Normal file
204
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io2323.h
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io2323.h,v 1.8.4.4 2008/10/17 23:27:45 arcanum Exp $ */
|
||||
|
||||
/* avr/io2323.h - definitions for AT90S2323 */
|
||||
|
||||
#ifndef _AVR_IO2323_H_
|
||||
#define _AVR_IO2323_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io2323.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO8(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU Status Register */
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF0_vect _VECTOR(2)
|
||||
#define SIG_OVERFLOW0 _VECTOR(2)
|
||||
|
||||
#define _VECTORS_SIZE 6
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT0 6
|
||||
#define INTF0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define TOIE0 1
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/*
|
||||
PB2 = SCK/T0
|
||||
PB1 = MISO/INT0
|
||||
PB0 = MOSI
|
||||
*/
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0xDF
|
||||
#define XRAMEND 0xDF
|
||||
#define E2END 0x7F
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x07FF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_FSTRT (unsigned char)~_BV(0)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x91
|
||||
#define SIGNATURE_2 0x02
|
||||
|
||||
|
||||
#endif /* _AVR_IO2323_H_ */
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x91
|
||||
#define SIGNATURE_2 0x02
|
||||
|
||||
444
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io2333.h
Normal file
444
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io2333.h
Normal file
|
|
@ -0,0 +1,444 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io2333.h,v 1.9 2005/10/30 22:11:23 joerg_wunsch Exp $ */
|
||||
|
||||
/* avr/io2333.h - definitions for AT90S2333 */
|
||||
|
||||
#ifndef _AVR_IO2333_H_
|
||||
#define _AVR_IO2333_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io2333.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* UART Baud Rate Register high */
|
||||
#define UBRRH _SFR_IO8(0x03)
|
||||
|
||||
/* ADC Data register */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x04)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x04)
|
||||
#define ADCL _SFR_IO8(0x04)
|
||||
#define ADCH _SFR_IO8(0x05)
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADCSR _SFR_IO8(0x06)
|
||||
|
||||
/* ADC MUX */
|
||||
#define ADMUX _SFR_IO8(0x07)
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control/Status Registers */
|
||||
#define UCSRB _SFR_IO8(0x0A)
|
||||
#define UCSRA _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO8(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x26)
|
||||
#define ICR1L _SFR_IO8(0x26)
|
||||
#define ICR1H _SFR_IO8(0x27)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1 _SFR_IO16(0x2A)
|
||||
#define OCR1L _SFR_IO8(0x2A)
|
||||
#define OCR1H _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(3)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter1 Compare Match */
|
||||
#define TIMER1_COMP_vect _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(5)
|
||||
#define SIG_OVERFLOW1 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(6)
|
||||
#define SIG_OVERFLOW0 _VECTOR(6)
|
||||
|
||||
/* Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(7)
|
||||
#define SIG_SPI _VECTOR(7)
|
||||
|
||||
/* UART, Rx Complete */
|
||||
#define UART_RX_vect _VECTOR(8)
|
||||
#define SIG_UART_RECV _VECTOR(8)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(9)
|
||||
#define SIG_UART_DATA _VECTOR(9)
|
||||
|
||||
/* UART, Tx Complete */
|
||||
#define UART_TX_vect _VECTOR(10)
|
||||
#define SIG_UART_TRANS _VECTOR(10)
|
||||
|
||||
/* ADC Conversion Complete */
|
||||
#define ADC_vect _VECTOR(11)
|
||||
#define SIG_ADC _VECTOR(11)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_RDY_vect _VECTOR(12)
|
||||
#define SIG_EEPROM_READY _VECTOR(12)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(13)
|
||||
#define SIG_COMPARATOR _VECTOR(13)
|
||||
|
||||
#define _VECTORS_SIZE 28
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define WDRF 3
|
||||
#define BORF 2
|
||||
#define EXTRF 1
|
||||
#define PORF 0
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TOIE1 7
|
||||
#define OCIE1 6
|
||||
#define TICIE1 3
|
||||
#define TOIE0 1
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TOV1 7
|
||||
#define OCF1 6
|
||||
#define ICF1 3
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM11 7
|
||||
#define COM10 6
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
#define MPCM 0
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACD 7
|
||||
#define AINBG 6
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* ADC MUX */
|
||||
#define ACDBG 6
|
||||
#define MUX2 2
|
||||
#define MUX1 1
|
||||
#define MUX0 0
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADEN 7
|
||||
#define ADSC 6
|
||||
#define ADFR 5
|
||||
#define ADIF 4
|
||||
#define ADIE 3
|
||||
#define ADPS2 2
|
||||
#define ADPS1 1
|
||||
#define ADPS0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0xDF /*Last On-Chip SRAM location*/
|
||||
#define XRAMEND 0xDF
|
||||
#define E2END 0x7F
|
||||
#define FLASHEND 0x7FF
|
||||
|
||||
#endif /* _AVR_IO2333_H_ */
|
||||
209
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io2343.h
Normal file
209
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io2343.h
Normal file
|
|
@ -0,0 +1,209 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io2343.h,v 1.9.2.3 2008/08/14 00:07:59 arcanum Exp $ */
|
||||
|
||||
/* avr/io2343.h - definitions for AT90S2343 */
|
||||
|
||||
#ifndef _AVR_IO2343_H_
|
||||
#define _AVR_IO2343_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io2343.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO8(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU Status Register */
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF0_vect _VECTOR(2)
|
||||
#define SIG_OVERFLOW0 _VECTOR(2)
|
||||
|
||||
#define _VECTORS_SIZE 6
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT0 6
|
||||
#define INTF0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define TOIE0 1
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* MCU Status Register */
|
||||
#define PORF 0
|
||||
#define EXTRF 1
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/*
|
||||
PB3 = CLOCK
|
||||
PB2 = SCK/T0
|
||||
PB1 = MISO/INT0
|
||||
PB0 = MOSI
|
||||
*/
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0xDF
|
||||
#define XRAMEND 0xDF
|
||||
#define E2END 0x7F
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x07FF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_RCEN (unsigned char)~_BV(0)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x91
|
||||
#define SIGNATURE_2 0x03
|
||||
|
||||
|
||||
#endif /* _AVR_IO2343_H_ */
|
||||
|
|
@ -0,0 +1,436 @@
|
|||
/* Copyright (c) 2003,2005 Keith Gudger
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io43u32x.h,v 1.5 2005/11/10 22:19:07 joerg_wunsch Exp $ */
|
||||
|
||||
/* avr/io43u32x.h - definitions for AT43USB32x */
|
||||
|
||||
#ifndef _AVR_IO43U32X_H_
|
||||
#define _AVR_IO43U32X_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io43u32x.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control Register */
|
||||
#define UCR _SFR_IO8(0x0A)
|
||||
|
||||
/* UART Status Register */
|
||||
#define USR _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* Input Pins, Port E */ // new port for 43324/6
|
||||
#define PINE _SFR_IO8(0x01)
|
||||
|
||||
/* Data Direction Register, Port E */
|
||||
#define DDRE _SFR_IO8(0x02)
|
||||
|
||||
/* Data Register, Port E */
|
||||
#define PORTE _SFR_IO8(0x03)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* 0x1C..0x1F reserved */
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x24)
|
||||
#define ICR1L _SFR_IO8(0x24)
|
||||
#define ICR1H _SFR_IO8(0x25)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register B */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Control Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt Mask register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
#define SIG_TIMER1_CAPT1 _VECTOR(3)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
|
||||
#define SIG_OVERFLOW1 _VECTOR(6)
|
||||
#define SIG_OVERFLOW0 _VECTOR(7)
|
||||
#define SIG_SPI _VECTOR(8)
|
||||
#define SIG_UART_RECV _VECTOR(9)
|
||||
#define SIG_UART_DATA _VECTOR(10)
|
||||
#define SIG_UART_TRANS _VECTOR(11)
|
||||
#define SIG_USB_INT _VECTOR(12)
|
||||
|
||||
#define _VECTORS_SIZE 52
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TICIE1 3
|
||||
#define OCIE1A 6
|
||||
#define OCIE1B 5
|
||||
#define TOIE1 7
|
||||
#define TOIE0 1
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define ICF1 3
|
||||
#define OCF1A 6
|
||||
#define OCF1B 5
|
||||
#define TOV1 7
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* Data Register, Port E */
|
||||
#define PE7 7
|
||||
#define PE6 6
|
||||
#define PE5 5
|
||||
#define PE4 4
|
||||
#define PE3 3
|
||||
#define PE2 2
|
||||
#define PE1 1
|
||||
#define PE0 0
|
||||
|
||||
/* Data Direction Register, Port E */
|
||||
#define DDE7 7
|
||||
#define DDE6 6
|
||||
#define DDE5 5
|
||||
#define DDE4 4
|
||||
#define DDE3 3
|
||||
#define DDE2 2
|
||||
#define DDE1 1
|
||||
#define DDE0 0
|
||||
|
||||
/* Input Pins, Port E */
|
||||
#define PINE7 7
|
||||
#define PINE6 6
|
||||
#define PINE5 5
|
||||
#define PINE4 4
|
||||
#define PINE3 3
|
||||
#define PINE2 2
|
||||
#define PINE1 1
|
||||
#define PINE0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0x025F /*Last On-Chip SRAM Location*/
|
||||
#define XRAMEND 0x025F
|
||||
#define E2END 0x0000
|
||||
|
||||
/* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory,
|
||||
but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now... */
|
||||
#define FLASHEND 0x0FFFF
|
||||
|
||||
#endif /* _AVR_43USB32X_H_ */
|
||||
|
|
@ -0,0 +1,428 @@
|
|||
/* Copyright (c) 2003,2005 Keith Gudger
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io43u35x.h,v 1.7 2005/11/10 22:19:07 joerg_wunsch Exp $ */
|
||||
|
||||
/* avr/io43u35x.h - definitions for AT43USB35x */
|
||||
|
||||
#ifndef _AVR_IO43U35X_H_
|
||||
#define _AVR_IO43U35X_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io43u35x.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* ADC Data Register */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x02)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x02)
|
||||
#define ADCL _SFR_IO8(0x02)
|
||||
#define ADCH _SFR_IO8(0x03)
|
||||
|
||||
/* ADC Control and status register */
|
||||
#define ADCSR _SFR_IO8(0x07)
|
||||
|
||||
/* ADC Multiplexer select */
|
||||
#define ADMUX _SFR_IO8(0x08)
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* Input Pins, Port F */
|
||||
#define PINF _SFR_IO8(0x04)
|
||||
|
||||
/* Data Direction Register, Port F */
|
||||
#define DDRF _SFR_IO8(0x05)
|
||||
|
||||
/* Data Register, Port F */
|
||||
#define PORTF _SFR_IO8(0x06)
|
||||
|
||||
/* Input Pins, Port E */
|
||||
#define PINE _SFR_IO8(0x01)
|
||||
|
||||
/* Data Direction Register, Port E */
|
||||
#define DDRE _SFR_IO8(0x02)
|
||||
|
||||
/* Data Register, Port E */
|
||||
#define PORTE _SFR_IO8(0x03)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* 0x1C..0x1F reserved */
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x24)
|
||||
#define ICR1L _SFR_IO8(0x24)
|
||||
#define ICR1H _SFR_IO8(0x25)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register B */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Control Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt Mask register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
#define SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
#define SIG_TIMER1_CAPT1 _VECTOR(3)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
|
||||
#define SIG_OVERFLOW1 _VECTOR(6)
|
||||
#define SIG_OVERFLOW0 _VECTOR(7)
|
||||
#define SIG_SPI _VECTOR(8)
|
||||
/* 9, 10: reserved */
|
||||
#define SIG_ADC _VECTOR(11)
|
||||
#define SIG_USB_INT _VECTOR(12)
|
||||
|
||||
#define _VECTORS_SIZE 52
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TICIE1 3
|
||||
#define OCIE1A 6
|
||||
#define OCIE1B 5
|
||||
#define TOIE1 7
|
||||
#define TOIE0 1
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define ICF1 3
|
||||
#define OCF1A 6
|
||||
#define OCF1B 5
|
||||
#define TOV1 7
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* Data Register, Port F */
|
||||
#define PF3 3
|
||||
#define PF2 2
|
||||
#define PF1 1
|
||||
#define PF0 0
|
||||
|
||||
/* Data Direction Register, Port F */
|
||||
#define DDF3 3
|
||||
#define DDF2 2
|
||||
#define DDF1 1
|
||||
|
||||
/* Input Pins, Port F */
|
||||
#define PINF3 3
|
||||
#define PINF2 2
|
||||
#define PINF1 1
|
||||
#define PINF0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* ADC Multiplexer select */
|
||||
#define MUX2 2
|
||||
#define MUX1 1
|
||||
#define MUX0 0
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADEN 7
|
||||
#define ADSC 6
|
||||
#define ADFR 5
|
||||
#define ADIF 4
|
||||
#define ADIE 3
|
||||
#define ADPS2 2
|
||||
#define ADPS1 1
|
||||
#define ADPS0 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0x045F /*Last On-Chip SRAM Location*/
|
||||
#define XRAMEND 0x045F
|
||||
#define E2END 0x0000
|
||||
#define FLASHEND 0x5FFF
|
||||
|
||||
#endif /* _AVR_43USB355_H_ */
|
||||
485
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io4414.h
Normal file
485
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io4414.h
Normal file
|
|
@ -0,0 +1,485 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io4414.h,v 1.8.4.3 2008/08/14 00:07:59 arcanum Exp $ */
|
||||
|
||||
/* avr/io4414.h - definitions for AT90S4414 */
|
||||
|
||||
#ifndef _AVR_IO4414_H_
|
||||
#define _AVR_IO4414_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io4414.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control Register */
|
||||
#define UCR _SFR_IO8(0x0A)
|
||||
|
||||
/* UART Status Register */
|
||||
#define USR _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO8(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x24)
|
||||
#define ICR1L _SFR_IO8(0x24)
|
||||
#define ICR1H _SFR_IO8(0x25)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register B */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3C..0x3D SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt Request 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt Request 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(3)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Compare MatchB */
|
||||
#define TIMER1_COMPB_vect _VECTOR(5)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(6)
|
||||
#define SIG_OVERFLOW1 _VECTOR(6)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(7)
|
||||
#define SIG_OVERFLOW0 _VECTOR(7)
|
||||
|
||||
/* Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(8)
|
||||
#define SIG_SPI _VECTOR(8)
|
||||
|
||||
/* UART, Rx Complete */
|
||||
#define UART_RX_vect _VECTOR(9)
|
||||
#define SIG_UART_RECV _VECTOR(9)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(10)
|
||||
#define SIG_UART_DATA _VECTOR(10)
|
||||
|
||||
/* UART, Tx Complete */
|
||||
#define UART_TX_vect _VECTOR(11)
|
||||
#define SIG_UART_TRANS _VECTOR(11)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(12)
|
||||
#define SIG_COMPARATOR _VECTOR(12)
|
||||
|
||||
#define _VECTORS_SIZE 26
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TOIE1 7
|
||||
#define OCIE1A 6
|
||||
#define OCIE1B 5
|
||||
#define TICIE1 3
|
||||
#define TOIE0 1
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TOV1 7
|
||||
#define OCF1A 6
|
||||
#define OCF1B 5
|
||||
#define ICF1 3
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SRE 7
|
||||
#define SRW 6
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACD 7
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0x15F /* Last On-Chip SRAM Location */
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0xFF
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0xFFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */
|
||||
#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x92
|
||||
#define SIGNATURE_2 0x01
|
||||
|
||||
|
||||
#endif /* _AVR_IO4414_H_ */
|
||||
473
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io4433.h
Normal file
473
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io4433.h
Normal file
|
|
@ -0,0 +1,473 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io4433.h,v 1.9.4.3 2008/08/14 00:07:59 arcanum Exp $ */
|
||||
|
||||
/* avr/io4433.h - definitions for AT90S4433 */
|
||||
|
||||
#ifndef _AVR_IO4433_H_
|
||||
#define _AVR_IO4433_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io4433.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* UART Baud Rate Register high */
|
||||
#define UBRRH _SFR_IO8(0x03)
|
||||
|
||||
/* ADC Data register */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x04)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x04)
|
||||
#define ADCL _SFR_IO8(0x04)
|
||||
#define ADCH _SFR_IO8(0x05)
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADCSR _SFR_IO8(0x06)
|
||||
|
||||
/* ADC MUX */
|
||||
#define ADMUX _SFR_IO8(0x07)
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control/Status Registers */
|
||||
#define UCSRB _SFR_IO8(0x0A)
|
||||
#define UCSRA _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO8(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x26)
|
||||
#define ICR1L _SFR_IO8(0x26)
|
||||
#define ICR1H _SFR_IO8(0x27)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1 _SFR_IO16(0x2A)
|
||||
#define OCR1L _SFR_IO8(0x2A)
|
||||
#define OCR1H _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(3)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter1 Compare Match */
|
||||
#define TIMER1_COMP_vect _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(5)
|
||||
#define SIG_OVERFLOW1 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(6)
|
||||
#define SIG_OVERFLOW0 _VECTOR(6)
|
||||
|
||||
/* Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(7)
|
||||
#define SIG_SPI _VECTOR(7)
|
||||
|
||||
/* UART, Rx Complete */
|
||||
#define UART_RX_vect _VECTOR(8)
|
||||
#define SIG_UART_RECV _VECTOR(8)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(9)
|
||||
#define SIG_UART_DATA _VECTOR(9)
|
||||
|
||||
/* UART, Tx Complete */
|
||||
#define UART_TX_vect _VECTOR(10)
|
||||
#define SIG_UART_TRANS _VECTOR(10)
|
||||
|
||||
/* ADC Conversion Complete */
|
||||
#define ADC_vect _VECTOR(11)
|
||||
#define SIG_ADC _VECTOR(11)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_RDY_vect _VECTOR(12)
|
||||
#define SIG_EEPROM_READY _VECTOR(12)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(13)
|
||||
#define SIG_COMPARATOR _VECTOR(13)
|
||||
|
||||
#define _VECTORS_SIZE 28
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define WDRF 3
|
||||
#define BORF 2
|
||||
#define EXTRF 1
|
||||
#define PORF 0
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TOIE1 7
|
||||
#define OCIE1 6
|
||||
#define TICIE1 3
|
||||
#define TOIE0 1
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TOV1 7
|
||||
#define OCF1 6
|
||||
#define ICF1 3
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM11 7
|
||||
#define COM10 6
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
#define MPCM 0
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACD 7
|
||||
#define AINBG 6
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* ADC MUX */
|
||||
#define ACDBG 6
|
||||
#define MUX2 2
|
||||
#define MUX1 1
|
||||
#define MUX0 0
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADEN 7
|
||||
#define ADSC 6
|
||||
#define ADFR 5
|
||||
#define ADIF 4
|
||||
#define ADIE 3
|
||||
#define ADPS2 2
|
||||
#define ADPS1 1
|
||||
#define ADPS0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0xDF /*Last On-Chip SRAM location*/
|
||||
#define XRAMEND 0xDF
|
||||
#define E2END 0xFF
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0xFFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_BODEN (unsigned char)~_BV(3)
|
||||
#define FUSE_BODLEVEL (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x92
|
||||
#define SIGNATURE_2 0x03
|
||||
|
||||
|
||||
#endif /* _AVR_IO4433_H_ */
|
||||
567
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io4434.h
Normal file
567
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io4434.h
Normal file
|
|
@ -0,0 +1,567 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io4434.h,v 1.9.4.2 2008/08/14 00:07:59 arcanum Exp $ */
|
||||
|
||||
/* avr/io4434.h - definitions for AT90S4434 */
|
||||
|
||||
#ifndef _AVR_IO4434_H_
|
||||
#define _AVR_IO4434_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io4434.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* ADC Data register */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x04)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x04)
|
||||
#define ADCL _SFR_IO8(0x04)
|
||||
#define ADCH _SFR_IO8(0x05)
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADCSR _SFR_IO8(0x06)
|
||||
|
||||
/* ADC MUX */
|
||||
#define ADMUX _SFR_IO8(0x07)
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control Register */
|
||||
#define UCR _SFR_IO8(0x0A)
|
||||
|
||||
/* UART Status Register */
|
||||
#define USR _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO8(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* Asynchronous mode Status Register */
|
||||
#define ASSR _SFR_IO8(0x22)
|
||||
|
||||
/* Timer/Counter2 Output Compare Register */
|
||||
#define OCR2 _SFR_IO8(0x23)
|
||||
|
||||
/* Timer/Counter 2 */
|
||||
#define TCNT2 _SFR_IO8(0x24)
|
||||
|
||||
/* Timer/Counter 2 Control Register */
|
||||
#define TCCR2 _SFR_IO8(0x25)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x26)
|
||||
#define ICR1L _SFR_IO8(0x26)
|
||||
#define ICR1H _SFR_IO8(0x27)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register B */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter2 Compare Match */
|
||||
#define TIMER2_COMP_vect _VECTOR(3)
|
||||
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter2 Overflow */
|
||||
#define TIMER2_OVF_vect _VECTOR(4)
|
||||
#define SIG_OVERFLOW2 _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(5)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(6)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
|
||||
|
||||
/* Timer/Counter1 Compare Match B */
|
||||
#define TIMER1_COMPB_vect _VECTOR(7)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(8)
|
||||
#define SIG_OVERFLOW1 _VECTOR(8)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(9)
|
||||
#define SIG_OVERFLOW0 _VECTOR(9)
|
||||
|
||||
/* SPI Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(10)
|
||||
#define SIG_SPI _VECTOR(10)
|
||||
|
||||
/* UART, RX Complete */
|
||||
#define UART_RX_vect _VECTOR(11)
|
||||
#define SIG_UART_RECV _VECTOR(11)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(12)
|
||||
#define SIG_UART_DATA _VECTOR(12)
|
||||
|
||||
/* UART, TX Complete */
|
||||
#define UART_TX_vect _VECTOR(13)
|
||||
#define SIG_UART_TRANS _VECTOR(13)
|
||||
|
||||
/* ADC Conversion Complete */
|
||||
#define ADC_vect _VECTOR(14)
|
||||
#define SIG_ADC _VECTOR(14)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_RDY_vect _VECTOR(15)
|
||||
#define SIG_EEPROM_READY _VECTOR(15)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(16)
|
||||
#define SIG_COMPARATOR _VECTOR(16)
|
||||
|
||||
#define _VECTORS_SIZE 34
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define EXTRF 1
|
||||
#define PORF 0
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define OCIE2 7
|
||||
#define TOIE2 6
|
||||
#define TICIE1 5
|
||||
#define OCIE1A 4
|
||||
#define OCIE1B 3
|
||||
#define TOIE1 2
|
||||
#define TOIE0 0
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define OCF2 7
|
||||
#define TOV2 6
|
||||
#define ICF1 5
|
||||
#define OCF1A 4
|
||||
#define OCF1B 3
|
||||
#define TOV1 2
|
||||
#define TOV0 0
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 6
|
||||
#define SM1 5
|
||||
#define SM0 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Timer/Counter 2 Control Register */
|
||||
#define PWM2 6
|
||||
#define COM21 5
|
||||
#define COM20 4
|
||||
#define CTC2 3
|
||||
#define CS22 2
|
||||
#define CS21 1
|
||||
#define CS20 0
|
||||
|
||||
/* Asynchronous mode Status Register */
|
||||
#define AS2 3
|
||||
#define TCN2UB 2
|
||||
#define OCR2UB 1
|
||||
#define TCR2UB 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACD 7
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* ADC MUX */
|
||||
#define MUX2 2
|
||||
#define MUX1 1
|
||||
#define MUX0 0
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADEN 7
|
||||
#define ADSC 6
|
||||
#define ADFR 5
|
||||
#define ADIF 4
|
||||
#define ADIE 3
|
||||
#define ADPS2 2
|
||||
#define ADPS1 1
|
||||
#define ADPS0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0x15F /*Last On-Chip SRAM location*/
|
||||
#define XRAMEND 0x15F
|
||||
#define E2END 0xFF
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0xFFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */
|
||||
#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x93
|
||||
#define SIGNATURE_2 0x03
|
||||
|
||||
|
||||
#endif /* _AVR_IO4434_H_ */
|
||||
1558
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io58u54a.h
Normal file
1558
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io58u54a.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,493 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io76c711.h,v 1.5 2004/11/01 21:19:54 arcanum Exp $ */
|
||||
|
||||
/* avr/io76c711.h - definitions for AT76C711 */
|
||||
|
||||
#ifndef _AVR_IO76C711_H_
|
||||
#define _AVR_IO76C711_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io76c711.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* 0x00-0x0C reserved */
|
||||
|
||||
/* SPI */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Peripheral Enable Register */
|
||||
#define PERIPHEN _SFR_IO8(0x13)
|
||||
|
||||
/* Clock Control Register */
|
||||
#define CLK_CNTR _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* 0x1C-0x1F reserved */
|
||||
|
||||
#define IRDAMOD _SFR_IO8(0x20)
|
||||
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* 0x22-0x25 reserved */
|
||||
/* Timer 1 */
|
||||
#define ICR1 _SFR_IO16(0x26)
|
||||
#define ICR1L _SFR_IO8(0x26)
|
||||
#define ICR1H _SFR_IO8(0x27)
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* 0x30 reserved */
|
||||
|
||||
/* Timer 0 */
|
||||
#define PRELD _SFR_IO8(0x31)
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
#define TIFR _SFR_IO8(0x36)
|
||||
#define TIMSK _SFR_IO8(0x37)
|
||||
|
||||
/* 0x38 reserved */
|
||||
|
||||
#define EIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* 0x3A-0x3C reserved */
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
#define SIG_SUSPEND_RESUME _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(2)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
|
||||
#define SIG_OVERFLOW1 _VECTOR(6)
|
||||
#define SIG_OVERFLOW0 _VECTOR(7)
|
||||
#define SIG_SPI _VECTOR(8)
|
||||
#define SIG_TDMAC _VECTOR(9)
|
||||
#define SIG_UART0 _VECTOR(10)
|
||||
#define SIG_RDMAC _VECTOR(11)
|
||||
#define SIG_USB_HW _VECTOR(12)
|
||||
#define SIG_UART1 _VECTOR(13)
|
||||
#define SIG_INTERRUPT1 _VECTOR(14)
|
||||
|
||||
#define _VECTORS_SIZE 60
|
||||
|
||||
/* Bit numbers */
|
||||
|
||||
/* EIMSK */
|
||||
/* bits 7-4 reserved */
|
||||
#define POL1 3
|
||||
#define POL0 2
|
||||
#define INT1 1
|
||||
#define INT0 0
|
||||
|
||||
/* TIMSK */
|
||||
#define TOIE1 7
|
||||
#define OCIE1A 6
|
||||
#define OCIE1B 5
|
||||
/* bit 4 reserved */
|
||||
#define TICIE1 3
|
||||
/* bit 2 reserved */
|
||||
#define TOIE0 1
|
||||
/* bit 0 reserved */
|
||||
|
||||
/* TIFR */
|
||||
#define TOV1 7
|
||||
#define OCF1A 6
|
||||
#define OCF1B 5
|
||||
/* bit 4 reserved */
|
||||
#define ICF1 3
|
||||
/* bit 2 reserved */
|
||||
#define TOV0 1
|
||||
/* bit 0 reserved */
|
||||
|
||||
/* MCUCR */
|
||||
/* bits 7-6 reserved */
|
||||
#define SE 5
|
||||
#define SM1 4
|
||||
#define SM0 3
|
||||
/* bits 2-0 reserved */
|
||||
|
||||
/* MCUSR */
|
||||
/* bits 7-2 reserved */
|
||||
#define EXTRF 1
|
||||
#define PORF 0
|
||||
|
||||
/* TCCR0 */
|
||||
/* bits 7-6 reserved */
|
||||
#define COM01 5
|
||||
#define COM00 4
|
||||
#define CTC0 3
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* TCCR1A */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
/* bits 3-0 reserved */
|
||||
|
||||
/* TCCR1B */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
/* bits 5-4 reserved */
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* WDTCR */
|
||||
/* bits 7-5 reserved */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* IRDAMOD */
|
||||
/* bits 7-3 reserved */
|
||||
#define POL 2
|
||||
#define MODE 1
|
||||
#define EN 0
|
||||
|
||||
/* PORTA */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* DDRA */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* PINA */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/*
|
||||
PB7 = SCK
|
||||
PB6 = MISO
|
||||
PB5 = MOSI
|
||||
PB4 = SS#
|
||||
PB2 = ICP
|
||||
PB1 = T1
|
||||
PB0 = T0
|
||||
*/
|
||||
|
||||
/* PORTB */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* DDRB */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* PINB */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* PORTC */
|
||||
/* bits 7-4 reserved */
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/*
|
||||
PD7 = INT1 / OC1B
|
||||
PD6 = INT0 / OC1A
|
||||
PD1 = TXD
|
||||
PD0 = RXD
|
||||
*/
|
||||
|
||||
/* PORTD */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* DDRD */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* PIND */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* CLK_CNTR */
|
||||
/* bits 7-5 reserved */
|
||||
#define UOSC 4
|
||||
#define UCK 3
|
||||
#define IRCK 2
|
||||
/* bits 1-0 reserved */
|
||||
|
||||
/* PERIPHEN */
|
||||
/* bits 7-3 reserved */
|
||||
#define IRDA 2
|
||||
#define UART 1
|
||||
#define USB 0
|
||||
|
||||
/* SPSR */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
/* bits 5-0 reserved */
|
||||
|
||||
/* SPCR */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */
|
||||
|
||||
/* UART */
|
||||
#define UART0_BASE 0x2020
|
||||
#define UART1_BASE 0x2030
|
||||
/* offsets from the base address */
|
||||
#define US_RHR 0x00
|
||||
#define US_THR 0x00
|
||||
#define US_IER 0x01
|
||||
#define US_FCR 0x02
|
||||
#define US_PMR 0x03
|
||||
#define US_MR 0x04
|
||||
#define US_CSR 0x05
|
||||
#define US_CR 0x06
|
||||
#define US_BL 0x07
|
||||
#define US_BM 0x08
|
||||
#define US_RTO 0x09
|
||||
#define US_TTG 0x0A
|
||||
|
||||
/* DMA */
|
||||
#define DMA_BASE 0x2000
|
||||
/* offsets from the base address */
|
||||
#define TXTADL 0x01
|
||||
#define TXPLL 0x03
|
||||
#define TXPLM 0x04
|
||||
#define TXTPLL 0x05
|
||||
#define TXTPLM 0x06
|
||||
#define RXTADL 0x07
|
||||
#define RXTADMEN 0x08
|
||||
#define RSPLL 0x09
|
||||
#define RXPLM 0x0A
|
||||
#define RXTPLL 0x0B
|
||||
#define RXTPLM 0x0C
|
||||
#define INTCST 0x0D
|
||||
/* XXX DPORG register mentioned on page 20, but undocumented */
|
||||
|
||||
/* XXX Program Memory Control Bit mentioned on page 20, but undocumented */
|
||||
#define PROGRAM_MEMORY_CONTROL_BIT 0x2040
|
||||
|
||||
/* USB */
|
||||
#define USB_BASE 0x1000
|
||||
/* offsets from the base address */
|
||||
#define FRM_NUM_H 0x0FD
|
||||
#define FRM_NUM_L 0x0FC
|
||||
#define GLB_STATE 0x0FB
|
||||
#define SPRSR 0x0FA
|
||||
#define SPRSIE 0x0F9
|
||||
#define UISR 0x0F7
|
||||
#define UIAR 0x0F5
|
||||
#define FADDR 0x0F2
|
||||
#define ENDPPGPG 0x0F1
|
||||
#define ECR0 0x0EF
|
||||
#define ECR1 0x0EE
|
||||
#define ECR2 0x0ED
|
||||
#define ECR3 0x0EC
|
||||
#define ECR4 0x0EB
|
||||
#define ECR5 0x0EA
|
||||
#define ECR6 0x0E9
|
||||
#define ECR7 0x0E8
|
||||
#define CSR0 0x0DF
|
||||
#define CSR1 0x0DE
|
||||
#define CSR2 0x0DD
|
||||
#define CSR3 0x0DC
|
||||
#define CSR4 0x0DB
|
||||
#define CSR5 0x0DA
|
||||
#define CSR6 0x0D9
|
||||
#define CSR7 0x0D8
|
||||
#define FDR0 0x0CF
|
||||
#define FDR1 0x0CE
|
||||
#define FDR2 0x0CD
|
||||
#define FDR3 0x0CC
|
||||
#define FDR4 0x0CB
|
||||
#define FDR5 0x0CA
|
||||
#define FDR6 0x0C9
|
||||
#define FDR7 0x0C8
|
||||
#define FBYTE_CNT0_L 0x0BF
|
||||
#define FBYTE_CNT1_L 0x0BE
|
||||
#define FBYTE_CNT2_L 0x0BD
|
||||
#define FBYTE_CNT3_L 0x0BC
|
||||
#define FBYTE_CNT4_L 0x0BB
|
||||
#define FBYTE_CNT5_L 0x0BA
|
||||
#define FBYTE_CNT6_L 0x0B9
|
||||
#define FBYTE_CNT7_L 0x0B8
|
||||
#define FBYTE_CNT0_H 0x0AF
|
||||
#define FBYTE_CNT1_H 0x0AE
|
||||
#define FBYTE_CNT2_H 0x0AD
|
||||
#define FBYTE_CNT3_H 0x0AC
|
||||
#define FBYTE_CNT4_H 0x0AB
|
||||
#define FBYTE_CNT5_H 0x0AA
|
||||
#define FBYTE_CNT6_H 0x0A9
|
||||
#define FBYTE_CNT7_H 0x0A8
|
||||
#define SLP_MD_EN 0x100
|
||||
#define IRQ_EN 0x101
|
||||
#define IRQ_STAT 0x102
|
||||
#define SUSP_WUP 0x103
|
||||
#define PA_EN 0x104
|
||||
#define USB_DMA_ADL 0x105
|
||||
#define USB_DMA_ADH 0x106
|
||||
#define USB_DMA_PLR 0x107
|
||||
#define USB_DMA_EAD 0x108
|
||||
#define USB_DMA_PLT 0x109
|
||||
#define USB_DMA_EN 0x10A
|
||||
|
||||
/* Last memory addresses */
|
||||
#define RAMEND 0x07FF
|
||||
#define XRAMEND 0x07FF
|
||||
#define E2END 0
|
||||
#define FLASHEND 0x3FFF
|
||||
|
||||
/*
|
||||
AT76C711 data space memory map (ranges not listed are reserved):
|
||||
0x0000 - 0x001F - AVR registers
|
||||
0x0020 - 0x005F - AVR I/O space
|
||||
0x0060 - 0x07FF - AVR data SRAM
|
||||
0x1000 - 0x1FFF - USB (not all locations used)
|
||||
0x2000 - 0x201F - DMA controller
|
||||
0x2020 - 0x202F - UART0
|
||||
0x2030 - 0x203F - UART1 (IRDA)
|
||||
0x2040 - the mysterious Program Memory Control bit (???)
|
||||
0x3000 - 0x37FF - DPRAM
|
||||
0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other
|
||||
AVR devices did that as well (no need to use LPM!)
|
||||
*/
|
||||
#endif /* _AVR_IO76C711_H_ */
|
||||
486
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io8515.h
Normal file
486
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io8515.h
Normal file
|
|
@ -0,0 +1,486 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io8515.h,v 1.8.4.2 2008/08/14 00:07:59 arcanum Exp $ */
|
||||
|
||||
/* avr/io8515.h - definitions for AT90S8515 */
|
||||
|
||||
#ifndef _AVR_IO8515_H_
|
||||
#define _AVR_IO8515_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io8515.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control Register */
|
||||
#define UCR _SFR_IO8(0x0A)
|
||||
|
||||
/* UART Status Register */
|
||||
#define USR _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO16(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
#define EEARH _SFR_IO8(0x1F)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x24)
|
||||
#define ICR1L _SFR_IO8(0x24)
|
||||
#define ICR1H _SFR_IO8(0x25)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register B */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt Request 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt Request 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(3)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Compare MatchB */
|
||||
#define TIMER1_COMPB_vect _VECTOR(5)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(6)
|
||||
#define SIG_OVERFLOW1 _VECTOR(6)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(7)
|
||||
#define SIG_OVERFLOW0 _VECTOR(7)
|
||||
|
||||
/* Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(8)
|
||||
#define SIG_SPI _VECTOR(8)
|
||||
|
||||
/* UART, Rx Complete */
|
||||
#define UART_RX_vect _VECTOR(9)
|
||||
#define SIG_UART_RECV _VECTOR(9)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(10)
|
||||
#define SIG_UART_DATA _VECTOR(10)
|
||||
|
||||
/* UART, Tx Complete */
|
||||
#define UART_TX_vect _VECTOR(11)
|
||||
#define SIG_UART_TRANS _VECTOR(11)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(12)
|
||||
#define SIG_COMPARATOR _VECTOR(12)
|
||||
|
||||
#define _VECTORS_SIZE 26
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TOIE1 7
|
||||
#define OCIE1A 6
|
||||
#define OCIE1B 5
|
||||
#define TICIE1 3
|
||||
#define TOIE0 1
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TOV1 7
|
||||
#define OCF1A 6
|
||||
#define OCF1B 5
|
||||
#define ICF1 3
|
||||
#define TOV0 1
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SRE 7
|
||||
#define SRW 6
|
||||
#define SE 5
|
||||
#define SM 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACD 7
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0x25F /* Last On-Chip SRAM Location */
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0x1FF
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x1FFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */
|
||||
#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x93
|
||||
#define SIGNATURE_2 0x01
|
||||
|
||||
|
||||
#endif /* _AVR_IO8515_H_ */
|
||||
216
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io8534.h
Normal file
216
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io8534.h
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io8534.h,v 1.7 2005/07/09 14:01:11 aesok Exp $ */
|
||||
|
||||
/* avr/io8534.h - definitions for AT90C8534 */
|
||||
|
||||
#ifndef _AVR_IO8534_
|
||||
#define _AVR_IO8534_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io8534.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* 0x00..0x03 reserved */
|
||||
|
||||
/* ADC Data Register */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x04)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x04)
|
||||
#define ADCL _SFR_IO8(0x04)
|
||||
#define ADCH _SFR_IO8(0x05)
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADCSR _SFR_IO8(0x06)
|
||||
|
||||
/* ADC Multiplexer Select Register */
|
||||
#define ADMUX _SFR_IO8(0x07)
|
||||
|
||||
/* 0x08..0x0F reserved */
|
||||
|
||||
/* General Interrupt Pin Register */
|
||||
#define GIPR _SFR_IO8(0x10)
|
||||
|
||||
/* 0x11..0x19 reserved */
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO16(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
#define EEARH _SFR_IO8(0x1F)
|
||||
|
||||
/* 0x20..0x2B reserved */
|
||||
|
||||
/* Timer/Counter1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter1 Control Register */
|
||||
#define TCCR1 _SFR_IO8(0x2E)
|
||||
|
||||
/* 0x2F..0x31 reserved */
|
||||
|
||||
/* Timer/Counter0 (8-bit) */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* 0x34 reserved */
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* 0x36..0x37 reserved */
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK Register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3C reserved */
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
#define SIG_OVERFLOW1 _VECTOR(3)
|
||||
#define SIG_OVERFLOW0 _VECTOR(4)
|
||||
#define SIG_ADC _VECTOR(5)
|
||||
#define SIG_EEPROM_READY _VECTOR(6)
|
||||
|
||||
#define _VECTORS_SIZE 14
|
||||
|
||||
/* Bit numbers */
|
||||
|
||||
/* GIMSK */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
|
||||
/* GIFR */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
|
||||
/* GIPR */
|
||||
#define IPIN1 3
|
||||
#define IPIN0 2
|
||||
|
||||
/* TIMSK */
|
||||
#define TOIE1 2
|
||||
#define TOIE0 0
|
||||
|
||||
/* TIFR */
|
||||
#define TOV1 2
|
||||
#define TOV0 0
|
||||
|
||||
/* MCUCR */
|
||||
#define SE 6
|
||||
#define SM 5
|
||||
#define ISC1 2
|
||||
#define ISC0 0
|
||||
|
||||
/* TCCR0 */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* TCCR1 */
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* PORTA */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* DDRA */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Last memory addresses */
|
||||
#define RAMEND 0x15F
|
||||
#define XRAMEND 0x15F
|
||||
#define E2END 0x1FF
|
||||
#define FLASHEND 0x1FFF
|
||||
|
||||
#endif /* _AVR_IO8534_H_ */
|
||||
568
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io8535.h
Normal file
568
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io8535.h
Normal file
|
|
@ -0,0 +1,568 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: io8535.h,v 1.9.4.3 2008/08/14 00:07:59 arcanum Exp $ */
|
||||
|
||||
/* avr/io8535.h - definitions for AT90S8535 */
|
||||
|
||||
#ifndef _AVR_IO8535_H_
|
||||
#define _AVR_IO8535_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io8535.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* ADC Data register */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x04)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x04)
|
||||
#define ADCL _SFR_IO8(0x04)
|
||||
#define ADCH _SFR_IO8(0x05)
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADCSR _SFR_IO8(0x06)
|
||||
|
||||
/* ADC MUX */
|
||||
#define ADMUX _SFR_IO8(0x07)
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control Register */
|
||||
#define UCR _SFR_IO8(0x0A)
|
||||
|
||||
/* UART Status Register */
|
||||
#define USR _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO16(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
#define EEARH _SFR_IO8(0x1F)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* Asynchronous mode Status Register */
|
||||
#define ASSR _SFR_IO8(0x22)
|
||||
|
||||
/* Timer/Counter2 Output Compare Register */
|
||||
#define OCR2 _SFR_IO8(0x23)
|
||||
|
||||
/* Timer/Counter 2 */
|
||||
#define TCNT2 _SFR_IO8(0x24)
|
||||
|
||||
/* Timer/Counter 2 Control Register */
|
||||
#define TCCR2 _SFR_IO8(0x25)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x26)
|
||||
#define ICR1L _SFR_IO8(0x26)
|
||||
#define ICR1H _SFR_IO8(0x27)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register B */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter2 Compare Match */
|
||||
#define TIMER2_COMP_vect _VECTOR(3)
|
||||
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter2 Overflow */
|
||||
#define TIMER2_OVF_vect _VECTOR(4)
|
||||
#define SIG_OVERFLOW2 _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(5)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(6)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
|
||||
|
||||
/* Timer/Counter1 Compare Match B */
|
||||
#define TIMER1_COMPB_vect _VECTOR(7)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(8)
|
||||
#define SIG_OVERFLOW1 _VECTOR(8)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(9)
|
||||
#define SIG_OVERFLOW0 _VECTOR(9)
|
||||
|
||||
/* SPI Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(10)
|
||||
#define SIG_SPI _VECTOR(10)
|
||||
|
||||
/* UART, RX Complete */
|
||||
#define UART_RX_vect _VECTOR(11)
|
||||
#define SIG_UART_RECV _VECTOR(11)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(12)
|
||||
#define SIG_UART_DATA _VECTOR(12)
|
||||
|
||||
/* UART, TX Complete */
|
||||
#define UART_TX_vect _VECTOR(13)
|
||||
#define SIG_UART_TRANS _VECTOR(13)
|
||||
|
||||
/* ADC Conversion Complete */
|
||||
#define ADC_vect _VECTOR(14)
|
||||
#define SIG_ADC _VECTOR(14)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_RDY_vect _VECTOR(15)
|
||||
#define SIG_EEPROM_READY _VECTOR(15)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(16)
|
||||
#define SIG_COMPARATOR _VECTOR(16)
|
||||
|
||||
#define _VECTORS_SIZE 34
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define EXTRF 1
|
||||
#define PORF 0
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define OCIE2 7
|
||||
#define TOIE2 6
|
||||
#define TICIE1 5
|
||||
#define OCIE1A 4
|
||||
#define OCIE1B 3
|
||||
#define TOIE1 2
|
||||
#define TOIE0 0
|
||||
|
||||
/* Timer/Counter Interrupt Flag register */
|
||||
#define OCF2 7
|
||||
#define TOV2 6
|
||||
#define ICF1 5
|
||||
#define OCF1A 4
|
||||
#define OCF1B 3
|
||||
#define TOV1 2
|
||||
#define TOV0 0
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SE 6
|
||||
#define SM1 5
|
||||
#define SM0 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Timer/Counter 2 Control Register */
|
||||
#define PWM2 6
|
||||
#define COM21 5
|
||||
#define COM20 4
|
||||
#define CTC2 3
|
||||
#define CS22 2
|
||||
#define CS21 1
|
||||
#define CS20 0
|
||||
|
||||
/* Asynchronous mode Status Register */
|
||||
#define AS2 3
|
||||
#define TCN2UB 2
|
||||
#define OCR2UB 1
|
||||
#define TCR2UB 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACD 7
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* ADC MUX */
|
||||
#define MUX2 2
|
||||
#define MUX1 1
|
||||
#define MUX0 0
|
||||
|
||||
/* ADC Control and Status Register */
|
||||
#define ADEN 7
|
||||
#define ADSC 6
|
||||
#define ADFR 5
|
||||
#define ADIF 4
|
||||
#define ADIE 3
|
||||
#define ADPS2 2
|
||||
#define ADPS1 1
|
||||
#define ADPS0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0x25F /*Last On-Chip SRAM location*/
|
||||
#define XRAMEND 0x25F
|
||||
#define E2END 0x1FF
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x1FFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */
|
||||
#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */
|
||||
#define LFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x93
|
||||
#define SIGNATURE_2 0x03
|
||||
|
||||
|
||||
#endif /* _AVR_IO8535_H_ */
|
||||
|
|
@ -0,0 +1,308 @@
|
|||
/* Copyright (c) 2002, Colin O'Flynn
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* avr/io86r401.h - definitions for AT86RF401 */
|
||||
|
||||
#ifndef _AVR_IO86RF401_H_
|
||||
#define _AVR_IO86RF401_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "io86r401.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
#include <avr/sfr_defs.h>
|
||||
|
||||
/* Status REGister */
|
||||
#define SREG _SFR_IO8(0x3F)
|
||||
|
||||
/* Stack Pointer */
|
||||
#define SP _SFR_IO16(0x3D)
|
||||
#define SPH _SFR_IO8(0x3E)
|
||||
#define SPL _SFR_IO8(0x3D)
|
||||
|
||||
/*Battery low configeration register */
|
||||
#define BL_CONFIG _SFR_IO8(0x35)
|
||||
|
||||
/*Button detect register*/
|
||||
#define B_DET _SFR_IO8(0x34)
|
||||
|
||||
/*AVR Configeration register*/
|
||||
#define AVR_CONFIG _SFR_IO8(0x33)
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/*Data in register */
|
||||
#define IO_DATIN _SFR_IO8(0x32)
|
||||
|
||||
/*Data out register */
|
||||
#define IO_DATOUT _SFR_IO8(0x31)
|
||||
|
||||
/*IO Enable register */
|
||||
#define IO_ENAB _SFR_IO8(0x30)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x22)
|
||||
|
||||
/* Bit Timer Control Register */
|
||||
#define BTCR _SFR_IO8(0x21)
|
||||
|
||||
#define BTCNT _SFR_IO8(0x20)
|
||||
|
||||
/*
|
||||
NOTE: EEPROM name's changed to have D in front on them, per datasheet, but
|
||||
you may want to remove the leading D.
|
||||
*/
|
||||
/* EEPROM Control Register */
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define DEEAR _SFR_IO8(0x1E)
|
||||
#define DEEARL _SFR_IO8(0x1E)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define DEEDR _SFR_IO8(0x1D)
|
||||
/* EEPROM Control Register */
|
||||
#define DEECR _SFR_IO8(0x1C)
|
||||
|
||||
/* Lock Detector Configuration Register 2 */
|
||||
#define LOCKDET2 _SFR_IO8(0x17)
|
||||
|
||||
/* VCO Tuning Register*/
|
||||
#define VCOTUNE _SFR_IO8(0x16)
|
||||
|
||||
/* Power Attenuation Control Register */
|
||||
#define PWR_ATTEN _SFR_IO8(0x14)
|
||||
|
||||
/* Transmitter Control Register */
|
||||
#define TX_CNTL _SFR_IO8(0x12)
|
||||
|
||||
/* Lock Detector Configuration Register 1 */
|
||||
#define LOCKDET1 _SFR_IO8(0x10)
|
||||
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* Transmission Done, Bit Timer Flag 2 Interrupt */
|
||||
#define TXDONE_vect _VECTOR(1)
|
||||
#define SIG_TXDONE _VECTOR(1)
|
||||
|
||||
/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */
|
||||
#define TXEMPTY_vect _VECTOR(2)
|
||||
#define SIG_TXBE _VECTOR(2)
|
||||
|
||||
#define _VECTORS_SIZE 12
|
||||
|
||||
/*
|
||||
* The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* Lock Detector Configuration Register 1 - LOCKDET1 */
|
||||
#define UPOK 4
|
||||
#define ENKO 3
|
||||
#define BOD 2
|
||||
#define CS1 1
|
||||
#define CS0 0
|
||||
|
||||
/* Transmit Control Register - TX_CNTL */
|
||||
#define TXE 5
|
||||
#define TXK 4
|
||||
#define LOC 2
|
||||
|
||||
/* Power Attenuation Control Register - PWR_ATTEN */
|
||||
#define PCC2 5
|
||||
#define PCC1 4
|
||||
#define PCC0 3
|
||||
#define PCF2 2
|
||||
#define PCF1 1
|
||||
#define PCF0 0
|
||||
|
||||
/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/
|
||||
#define VCOVDET1 7
|
||||
#define VCOVDET0 6
|
||||
#define VCOTUNE4 4
|
||||
#define VCOTUNE3 3
|
||||
#define VCOTUNE2 2
|
||||
#define VCOTUNE1 1
|
||||
#define VCOTUNE0 0
|
||||
|
||||
/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/
|
||||
#define EUD 7
|
||||
#define LAT 6
|
||||
#define ULC2 5
|
||||
#define ULC1 4
|
||||
#define ULC0 3
|
||||
#define LC2 2
|
||||
#define LC1 1
|
||||
#define LC0 0
|
||||
|
||||
/* Data EEPROM Control Register - DEECR */
|
||||
#define BSY 3
|
||||
#define EEU 2
|
||||
#define EEL 1
|
||||
#define EER 0
|
||||
|
||||
/* Data EEPROM Data Register - DEEDR */
|
||||
#define ED7 7
|
||||
#define ED6 6
|
||||
#define ED5 5
|
||||
#define ED4 4
|
||||
#define ED3 3
|
||||
#define ED2 2
|
||||
#define ED1 1
|
||||
#define ED0 0
|
||||
|
||||
/* Data EEPROM Address Register - DEEAR */
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define BA2 2 /* B is not a typo! */
|
||||
#define BA1 1
|
||||
#define BA0 0
|
||||
|
||||
/* Bit Timer Count Register - BTCNT */
|
||||
#define C7 7
|
||||
#define C6 6
|
||||
#define C5 5
|
||||
#define C4 4
|
||||
#define C3 3
|
||||
#define C2 2
|
||||
#define C1 1
|
||||
#define C0 0
|
||||
|
||||
/* Bit Timer Control Register - BTCR */
|
||||
#define C9 7
|
||||
#define C8 6
|
||||
#define M1 5
|
||||
#define M0 4
|
||||
#define IE 3
|
||||
#define F2 2
|
||||
#define DATA 1
|
||||
#define F0 0
|
||||
|
||||
/* Watchdog Timer Control Register - WDTCR */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* I/O Enable Register - IO_ENAB */
|
||||
#define BOHYST 6
|
||||
#define IOE5 5
|
||||
#define IOE4 4
|
||||
#define IOE3 3
|
||||
#define IOE2 2
|
||||
#define IOE1 1
|
||||
#define IOE0 0
|
||||
|
||||
/* Note: No PORTB or whatever, this is the equivalent. */
|
||||
/* I/O Data Out Register - IO_DATOUT */
|
||||
#define IOO5 5
|
||||
#define IOO4 4
|
||||
#define IOO3 3
|
||||
#define IOO2 2
|
||||
#define IOO1 1
|
||||
#define IOO0 0
|
||||
|
||||
/* Note: No PINB or whatever, this is the equivalent. */
|
||||
/* I/O Data In Register - IO_DATIN */
|
||||
#define IOI5 5
|
||||
#define IOI4 4
|
||||
#define IOI3 3
|
||||
#define IOI2 2
|
||||
#define IOI1 1
|
||||
#define IOI0 0
|
||||
|
||||
/* AVR Configuration Register - AVR_CONFIG */
|
||||
#define ACS1 6
|
||||
#define ACS0 5
|
||||
#define TM 4
|
||||
#define BD 3
|
||||
#define BLI 2
|
||||
#define SLEEP 1
|
||||
#define BBM 0
|
||||
|
||||
/* Button Detect Register - B_DET */
|
||||
#define BD5 5
|
||||
#define BD4 4
|
||||
#define BD3 3
|
||||
#define BD2 2
|
||||
#define BD1 1
|
||||
#define BD0 0
|
||||
|
||||
/* Battery Low Configuration Register - BL_CONFIG */
|
||||
#define BL 7
|
||||
#define BLV 6
|
||||
#define BL5 5
|
||||
#define BL4 4
|
||||
#define BL3 3
|
||||
#define BL2 2
|
||||
#define BL1 1
|
||||
#define BL0 0
|
||||
|
||||
/* Pointer definition */
|
||||
#define XL r26
|
||||
#define XH r27
|
||||
#define YL r28
|
||||
#define YH r29
|
||||
#define ZL r30
|
||||
#define ZH r31
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0xDF
|
||||
#define XRAMEND 0xDF
|
||||
#define E2END 0x7F
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x07FF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 0
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x91
|
||||
#define SIGNATURE_2 0x81
|
||||
|
||||
|
||||
#endif /* _AVR_IO86RF401_H_ */
|
||||
1121
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm1.h
Normal file
1121
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm1.h
Normal file
File diff suppressed because it is too large
Load diff
1181
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm216.h
Normal file
1181
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm216.h
Normal file
File diff suppressed because it is too large
Load diff
1383
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm2b.h
Normal file
1383
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm2b.h
Normal file
File diff suppressed because it is too large
Load diff
1224
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm316.h
Normal file
1224
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm316.h
Normal file
File diff suppressed because it is too large
Load diff
1383
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm3b.h
Normal file
1383
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwm3b.h
Normal file
File diff suppressed because it is too large
Load diff
1371
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwmx.h
Normal file
1371
arduino-0018-windows/hardware/tools/avr/avr/include/avr/io90pwmx.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,557 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: ioat94k.h,v 1.9 2004/11/01 22:23:56 arcanum Exp $ */
|
||||
|
||||
/* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */
|
||||
|
||||
#ifndef _AVR_IOAT94K_H_
|
||||
#define _AVR_IOAT94K_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "ioat94k.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* UART1 Baud Rate Register */
|
||||
#define UBRR1 _SFR_IO8(0x00)
|
||||
|
||||
/* UART1 Control and Status Registers */
|
||||
#define UCSR1B _SFR_IO8(0x01)
|
||||
#define UCSR1A _SFR_IO8(0x02)
|
||||
|
||||
/* UART1 I/O Data Register */
|
||||
#define UDR1 _SFR_IO8(0x03)
|
||||
|
||||
/* 0x04 reserved */
|
||||
|
||||
/* Input Pins, Port E */
|
||||
#define PINE _SFR_IO8(0x05)
|
||||
|
||||
/* Data Direction Register, Port E */
|
||||
#define DDRE _SFR_IO8(0x06)
|
||||
|
||||
/* Data Register, Port E */
|
||||
#define PORTE _SFR_IO8(0x07)
|
||||
|
||||
/* On Chip Debug Register (reserved) */
|
||||
#define OCDR _SFR_IO8(0x08)
|
||||
|
||||
/* UART0 Baud Rate Register */
|
||||
#define UBRR0 _SFR_IO8(0x09)
|
||||
|
||||
/* UART0 Control and Status Registers */
|
||||
#define UCSR0B _SFR_IO8(0x0A)
|
||||
#define UCSR0A _SFR_IO8(0x0B)
|
||||
|
||||
/* UART0 I/O Data Register */
|
||||
#define UDR0 _SFR_IO8(0x0C)
|
||||
|
||||
/* 0x0D..0x0F reserved */
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* FPGA I/O Select Control Register */
|
||||
#define FISCR _SFR_IO8(0x13)
|
||||
|
||||
/* FPGA I/O Select Registers A, B, C, D */
|
||||
#define FISUA _SFR_IO8(0x14)
|
||||
#define FISUB _SFR_IO8(0x15)
|
||||
#define FISUC _SFR_IO8(0x16)
|
||||
#define FISUD _SFR_IO8(0x17)
|
||||
|
||||
/* FPGA Cache Logic(R) registers (top secret, under NDA) */
|
||||
#define FPGAX _SFR_IO8(0x18)
|
||||
#define FPGAY _SFR_IO8(0x19)
|
||||
#define FPGAZ _SFR_IO8(0x1A)
|
||||
#define FPGAD _SFR_IO8(0x1B)
|
||||
|
||||
/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
|
||||
|
||||
/* 2-wire Serial Bit Rate Register */
|
||||
#define TWBR _SFR_IO8(0x1C)
|
||||
|
||||
/* 2-wire Serial Status Register */
|
||||
#define TWSR _SFR_IO8(0x1D)
|
||||
|
||||
/* 2-wire Serial (Slave) Address Register */
|
||||
#define TWAR _SFR_IO8(0x1E)
|
||||
|
||||
/* 2-wire Serial Data Register */
|
||||
#define TWDR _SFR_IO8(0x1F)
|
||||
|
||||
/* UART Baud Register High */
|
||||
#define UBRRH _SFR_IO8(0x20)
|
||||
#define UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* Timer/Counter2 Output Compare Register */
|
||||
#define OCR2 _SFR_IO8(0x22)
|
||||
|
||||
/* Timer/Counter2 (8-bit) */
|
||||
#define TCNT2 _SFR_IO8(0x23)
|
||||
|
||||
/* Timer/Counter1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x24)
|
||||
#define ICR1L _SFR_IO8(0x24)
|
||||
#define ICR1H _SFR_IO8(0x25)
|
||||
|
||||
/* Asynchronous mode StatuS Register */
|
||||
#define ASSR _SFR_IO8(0x26)
|
||||
|
||||
/* Timer/Counter2 Control Register */
|
||||
#define TCCR2 _SFR_IO8(0x27)
|
||||
|
||||
/* Timer/Counter1 Output Compare RegisterB */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare RegisterA */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter1 Control Register B */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter1 Control Register A */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Special Function IO Register */
|
||||
#define SFIOR _SFR_IO8(0x30)
|
||||
|
||||
/* Timer/Counter0 Output Compare Register */
|
||||
#define OCR0 _SFR_IO8(0x31)
|
||||
|
||||
/* Timer/Counter0 (8-bit) */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* 0x34 reserved */
|
||||
|
||||
/* MCU Control/Status Register */
|
||||
#define MCUR _SFR_IO8(0x35)
|
||||
|
||||
/* 2-wire Serial Control Register */
|
||||
#define TWCR _SFR_IO8(0x36)
|
||||
|
||||
/* 0x37 reserved */
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK Register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* Software Control Register */
|
||||
#define SFTCR _SFR_IO8(0x3A)
|
||||
|
||||
/* External Interrupt Mask/Flag Register */
|
||||
#define EIMF _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3C reserved */
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */
|
||||
#define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */
|
||||
#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */
|
||||
#define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */
|
||||
#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */
|
||||
#define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */
|
||||
#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */
|
||||
#define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */
|
||||
#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */
|
||||
#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */
|
||||
#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */
|
||||
#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */
|
||||
#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */
|
||||
#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */
|
||||
#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */
|
||||
#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */
|
||||
#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */
|
||||
#define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */
|
||||
#define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */
|
||||
#define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */
|
||||
#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */
|
||||
#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */
|
||||
#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */
|
||||
#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */
|
||||
#define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */
|
||||
#define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */
|
||||
#define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */
|
||||
#define SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */
|
||||
#define SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */
|
||||
#define SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */
|
||||
#define SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */
|
||||
#define SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */
|
||||
|
||||
#define _VECTORS_SIZE 144
|
||||
|
||||
/* Bit numbers (SFRs alphabetically sorted) */
|
||||
|
||||
/* ASSR */
|
||||
#define AS2 3
|
||||
#define TCN2UB 2
|
||||
#define OCR2UB 1
|
||||
#define TCR2UB 0
|
||||
|
||||
/* DDRD */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* DDRE */
|
||||
#define DDE7 7
|
||||
#define DDE6 6
|
||||
#define DDE5 5
|
||||
#define DDE4 4
|
||||
#define DDE3 3
|
||||
#define DDE2 2
|
||||
#define DDE1 1
|
||||
#define DDE0 0
|
||||
|
||||
/* EIMF */
|
||||
#define INTF3 7
|
||||
#define INTF2 6
|
||||
#define INTF1 5
|
||||
#define INTF0 4
|
||||
#define INT3 3
|
||||
#define INT2 2
|
||||
#define INT1 1
|
||||
#define INT0 0
|
||||
|
||||
/* FISCR */
|
||||
#define FIADR 7
|
||||
#define XFIS1 1
|
||||
#define XFIS0 0
|
||||
|
||||
/* FISUA */
|
||||
#define FIF3 7
|
||||
#define FIF2 6
|
||||
#define FIF1 5
|
||||
#define FIF0 4
|
||||
#define FINT3 3
|
||||
#define FINT2 2
|
||||
#define FINT1 1
|
||||
#define FINT0 0
|
||||
|
||||
/* FISUB */
|
||||
#define FIF7 7
|
||||
#define FIF6 6
|
||||
#define FIF5 5
|
||||
#define FIF4 4
|
||||
#define FINT7 3
|
||||
#define FINT6 2
|
||||
#define FINT5 1
|
||||
#define FINT4 0
|
||||
|
||||
/* FISUC */
|
||||
#define FIF11 7
|
||||
#define FIF10 6
|
||||
#define FIF9 5
|
||||
#define FIF8 4
|
||||
#define FINT11 3
|
||||
#define FINT10 2
|
||||
#define FINT9 1
|
||||
#define FINT8 0
|
||||
|
||||
/* FISUD */
|
||||
#define FIF15 7
|
||||
#define FIF14 6
|
||||
#define FIF13 5
|
||||
#define FIF12 4
|
||||
#define FINT15 3
|
||||
#define FINT14 2
|
||||
#define FINT13 1
|
||||
#define FINT12 0
|
||||
|
||||
/* MCUR */
|
||||
#define JTRF 7
|
||||
#define JTD 6
|
||||
#define SE 5
|
||||
#define SM1 4
|
||||
#define SM0 3
|
||||
#define PORF 2
|
||||
#define WDRF 1
|
||||
#define EXTRF 0
|
||||
|
||||
/* OCDR (reserved) */
|
||||
#define IDRD 7
|
||||
|
||||
/* PIND */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* PINE */
|
||||
#define PINE7 7
|
||||
#define PINE6 6
|
||||
#define PINE5 5
|
||||
#define PINE4 4
|
||||
#define PINE3 3
|
||||
#define PINE2 2
|
||||
#define PINE1 1
|
||||
#define PINE0 0
|
||||
|
||||
/* PORTD */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* PORTE */
|
||||
/*
|
||||
PE7 = IC1 / INT3 (alternate)
|
||||
PE6 = OC1A / INT2 (alternate)
|
||||
PE5 = OC1B / INT1 (alternate)
|
||||
PE4 = ET11 / INT0 (alternate)
|
||||
PE3 = OC2 / RX1 (alternate)
|
||||
PE2 = / TX1 (alternate)
|
||||
PE1 = OC0 / RX0 (alternate)
|
||||
PE0 = ET0 / TX0 (alternate)
|
||||
*/
|
||||
#define PE7 7
|
||||
#define PE6 6
|
||||
#define PE5 5
|
||||
#define PE4 4
|
||||
#define PE3 3
|
||||
#define PE2 2
|
||||
#define PE1 1
|
||||
#define PE0 0
|
||||
|
||||
/* SFIOR */
|
||||
#define PSR2 1
|
||||
#define PSR10 0
|
||||
|
||||
/* SFTCR */
|
||||
#define FMXOR 3
|
||||
#define WDTS 2
|
||||
#define DBG 1
|
||||
#define SRST 0
|
||||
|
||||
/* TCCR0 */
|
||||
#define FOC0 7
|
||||
#define PWM0 6
|
||||
#define COM01 5
|
||||
#define COM00 4
|
||||
#define CTC0 3
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* TCCR1A */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define FOC1A 3
|
||||
#define FOC1B 2
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* TCCR1B */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define ICPE 5
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* TCCR2 */
|
||||
#define FOC2 7
|
||||
#define PWM2 6
|
||||
#define COM21 5
|
||||
#define COM20 4
|
||||
#define CTC2 3
|
||||
#define CS22 2
|
||||
#define CS21 1
|
||||
#define CS20 0
|
||||
|
||||
/* TIFR */
|
||||
#define TOV1 7
|
||||
#define OCF1A 6
|
||||
#define OCF1B 5
|
||||
#define TOV2 4
|
||||
#define ICF1 3
|
||||
#define OCF2 2
|
||||
#define TOV0 1
|
||||
#define OCF0 0
|
||||
|
||||
/* TIMSK */
|
||||
#define TOIE1 7
|
||||
#define OCIE1A 6
|
||||
#define OCIE1B 5
|
||||
#define TOIE2 4
|
||||
#define TICIE1 3
|
||||
#define OCIE2 2
|
||||
#define TOIE0 1
|
||||
#define OCIE0 0
|
||||
|
||||
/* TWAR */
|
||||
/* #define TWA 1 */ /* TWA is bits 7:1 */
|
||||
#define TWGCE 0
|
||||
|
||||
/* TWCR */
|
||||
#define TWINT 7
|
||||
#define TWEA 6
|
||||
#define TWSTA 5
|
||||
#define TWSTO 4
|
||||
#define TWWC 3
|
||||
#define TWEN 2
|
||||
#define TWIE 0
|
||||
|
||||
/* TWSR */
|
||||
#define TWS7 7
|
||||
#define TWS6 6
|
||||
#define TWS5 5
|
||||
#define TWS4 4
|
||||
#define TWS3 3
|
||||
|
||||
/* UBRRHI
|
||||
Bits 11..8 of UART1 are bits 7..4 of UBRRHI.
|
||||
Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */
|
||||
/* #define UBRRHI1 4 */
|
||||
/* #define UBRRHI0 0 */
|
||||
|
||||
/* UCSR0A */
|
||||
#define RXC0 7
|
||||
#define TXC0 6
|
||||
#define UDRE0 5
|
||||
#define FE0 4
|
||||
#define OR0 3
|
||||
#define U2X0 1
|
||||
#define MPCM0 0
|
||||
|
||||
/* UCSR0B */
|
||||
#define RXCIE0 7
|
||||
#define TXCIE0 6
|
||||
#define UDRIE0 5
|
||||
#define RXEN0 4
|
||||
#define TXEN0 3
|
||||
#define CHR90 2
|
||||
#define RXB80 1
|
||||
#define TXB80 0
|
||||
|
||||
/* UCSR1A */
|
||||
#define RXC1 7
|
||||
#define TXC1 6
|
||||
#define UDRE1 5
|
||||
#define FE1 4
|
||||
#define OR1 3
|
||||
#define U2X1 1
|
||||
#define MPCM1 0
|
||||
|
||||
/* UCSR1B */
|
||||
#define RXCIE1 7
|
||||
#define TXCIE1 6
|
||||
#define UDRIE1 5
|
||||
#define RXEN1 4
|
||||
#define TXEN1 3
|
||||
#define CHR91 2
|
||||
#define RXB81 1
|
||||
#define TXB81 0
|
||||
|
||||
/* WDTCR */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/*
|
||||
Last memory addresses - depending on configuration, it is possible
|
||||
to have 20K-32K of program memory and 4K-16K of data memory
|
||||
(all in the same 36K total of SRAM, loaded from external EEPROM).
|
||||
*/
|
||||
|
||||
#ifndef RAMEND
|
||||
#define RAMEND 0x0FFF
|
||||
#endif
|
||||
|
||||
#ifndef XRAMEND
|
||||
#define XRAMEND RAMEND
|
||||
#endif
|
||||
|
||||
#define E2END 0
|
||||
|
||||
#ifndef FLASHEND
|
||||
#define FLASHEND 0x7FFF
|
||||
#endif
|
||||
|
||||
#endif /* _AVR_IOAT94K_H_ */
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/* Copyright (c) 2004,2005, Colin O'Flynn <coflynn@newae.com>
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iocan128.h,v 1.17.2.5 2008/10/17 23:27:46 arcanum Exp $ */
|
||||
|
||||
/* iocan128.h - definitions for CAN128 */
|
||||
|
||||
#ifndef _AVR_IOCAN128_H_
|
||||
#define _AVR_IOCAN128_H_ 1
|
||||
|
||||
#include <avr/iocanxx.h>
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 256
|
||||
#define RAMEND 0x10FF /* Last On-Chip SRAM Location */
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0x0FFF
|
||||
#define E2PAGESIZE 8
|
||||
#define FLASHEND 0x1FFFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 3
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
||||
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
||||
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
||||
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
||||
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
||||
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
||||
|
||||
/* High Fuse Byte */
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
||||
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
||||
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
||||
#define FUSE_WDTON (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
||||
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
||||
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
||||
|
||||
/* Extended Fuse Byte */
|
||||
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
|
||||
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
|
||||
#define EFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x97
|
||||
#define SIGNATURE_2 0x81
|
||||
|
||||
|
||||
#endif /* _AVR_IOCAN128_H_ */
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iocan32.h,v 1.2.2.5 2008/10/17 23:27:46 arcanum Exp $ */
|
||||
|
||||
/* iocan32.h - definitions for CAN32 */
|
||||
|
||||
#ifndef _AVR_IOCAN32_H_
|
||||
#define _AVR_IOCAN32_H_ 1
|
||||
|
||||
#include <avr/iocanxx.h>
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 256
|
||||
#define RAMEND 0x08FF /* Last On-Chip SRAM Location */
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0x03FF
|
||||
#define E2PAGESIZE 8
|
||||
#define FLASHEND 0x7FFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 3
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
||||
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
||||
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
||||
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
||||
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
||||
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
||||
|
||||
/* High Fuse Byte */
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
||||
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
||||
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
||||
#define FUSE_WDTON (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
||||
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
||||
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
||||
|
||||
/* Extended Fuse Byte */
|
||||
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
|
||||
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
|
||||
#define EFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x95
|
||||
#define SIGNATURE_2 0x81
|
||||
|
||||
|
||||
#endif /* _AVR_IOCAN32_H_ */
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iocan64.h,v 1.2.2.5 2008/10/17 23:27:46 arcanum Exp $ */
|
||||
|
||||
/* iocan64.h - definitions for CAN64 */
|
||||
|
||||
#ifndef _AVR_IOCAN64_H_
|
||||
#define _AVR_IOCAN64_H_ 1
|
||||
|
||||
#include <avr/iocanxx.h>
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 256
|
||||
#define RAMEND 0x10FF /* Last On-Chip SRAM Location */
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0x07FF
|
||||
#define E2PAGESIZE 8
|
||||
#define FLASHEND 0xFFFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 3
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
||||
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
||||
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
||||
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
||||
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
||||
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
||||
|
||||
/* High Fuse Byte */
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
||||
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
||||
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
||||
#define FUSE_WDTON (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
||||
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
||||
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
||||
|
||||
/* Extended Fuse Byte */
|
||||
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
|
||||
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
|
||||
#define EFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x96
|
||||
#define SIGNATURE_2 0x81
|
||||
|
||||
|
||||
#endif /* _AVR_IOCAN64_H_ */
|
||||
1978
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iocanxx.h
Normal file
1978
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iocanxx.h
Normal file
File diff suppressed because it is too large
Load diff
675
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom103.h
Normal file
675
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom103.h
Normal file
|
|
@ -0,0 +1,675 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iom103.h,v 1.9.4.3 2008/08/14 00:08:00 arcanum Exp $ */
|
||||
|
||||
/* avr/iom103.h - definitions for ATmega103 */
|
||||
|
||||
#ifndef _AVR_IOM103_H_
|
||||
#define _AVR_IOM103_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "iom103.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* Input Pins, Port F */
|
||||
#define PINF _SFR_IO8(0x00)
|
||||
|
||||
/* Input Pins, Port E */
|
||||
#define PINE _SFR_IO8(0x01)
|
||||
|
||||
/* Data Direction Register, Port E */
|
||||
#define DDRE _SFR_IO8(0x02)
|
||||
|
||||
/* Data Register, Port E */
|
||||
#define PORTE _SFR_IO8(0x03)
|
||||
|
||||
/* ADC Data Register */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x04)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x04)
|
||||
#define ADCL _SFR_IO8(0x04)
|
||||
#define ADCH _SFR_IO8(0x05)
|
||||
|
||||
/* ADC Control and status register */
|
||||
#define ADCSR _SFR_IO8(0x06)
|
||||
|
||||
/* ADC Multiplexer select */
|
||||
#define ADMUX _SFR_IO8(0x07)
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART Baud Rate Register */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
|
||||
/* UART Control Register */
|
||||
#define UCR _SFR_IO8(0x0A)
|
||||
|
||||
/* UART Status Register */
|
||||
#define USR _SFR_IO8(0x0B)
|
||||
|
||||
/* UART I/O Data Register */
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO16(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
#define EEARH _SFR_IO8(0x1F)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* Timer2 Output Compare Register */
|
||||
#define OCR2 _SFR_IO8(0x23)
|
||||
|
||||
/* Timer/Counter 2 */
|
||||
#define TCNT2 _SFR_IO8(0x24)
|
||||
|
||||
/* Timer/Counter 2 Control register */
|
||||
#define TCCR2 _SFR_IO8(0x25)
|
||||
|
||||
/* T/C 1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x26)
|
||||
#define ICR1L _SFR_IO8(0x26)
|
||||
#define ICR1H _SFR_IO8(0x27)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register B */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare Register A */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter 1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Timer/Counter 0 Asynchronous Control & Status Register */
|
||||
#define ASSR _SFR_IO8(0x30)
|
||||
|
||||
/* Output Compare Register 0 */
|
||||
#define OCR0 _SFR_IO8(0x31)
|
||||
|
||||
/* Timer/Counter 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU Status Register */
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define TIFR _SFR_IO8(0x36)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define TIMSK _SFR_IO8(0x37)
|
||||
|
||||
/* Èxternal Interrupt Flag Register */
|
||||
#define EIFR _SFR_IO8(0x38)
|
||||
|
||||
/* External Interrupt MaSK register */
|
||||
#define EIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* External Interrupt Control Register */
|
||||
#define EICR _SFR_IO8(0x3A)
|
||||
|
||||
/* RAM Page Z select register */
|
||||
#define RAMPZ _SFR_IO8(0x3B)
|
||||
|
||||
/* XDIV Divide control register */
|
||||
#define XDIV _SFR_IO8(0x3C)
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* External Interrupt 2 */
|
||||
#define INT2_vect _VECTOR(3)
|
||||
#define SIG_INTERRUPT2 _VECTOR(3)
|
||||
|
||||
/* External Interrupt 3 */
|
||||
#define INT3_vect _VECTOR(4)
|
||||
#define SIG_INTERRUPT3 _VECTOR(4)
|
||||
|
||||
/* External Interrupt 4 */
|
||||
#define INT4_vect _VECTOR(5)
|
||||
#define SIG_INTERRUPT4 _VECTOR(5)
|
||||
|
||||
/* External Interrupt 5 */
|
||||
#define INT5_vect _VECTOR(6)
|
||||
#define SIG_INTERRUPT5 _VECTOR(6)
|
||||
|
||||
/* External Interrupt 6 */
|
||||
#define INT6_vect _VECTOR(7)
|
||||
#define SIG_INTERRUPT6 _VECTOR(7)
|
||||
|
||||
/* External Interrupt 7 */
|
||||
#define INT7_vect _VECTOR(8)
|
||||
#define SIG_INTERRUPT7 _VECTOR(8)
|
||||
|
||||
/* Timer/Counter2 Compare Match */
|
||||
#define TIMER2_COMP_vect _VECTOR(9)
|
||||
#define SIG_OUTPUT_COMPARE2 _VECTOR(9)
|
||||
|
||||
/* Timer/Counter2 Overflow */
|
||||
#define TIMER2_OVF_vect _VECTOR(10)
|
||||
#define SIG_OVERFLOW2 _VECTOR(10)
|
||||
|
||||
/* Timer/Counter1 Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(11)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(11)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(12)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(12)
|
||||
|
||||
/* Timer/Counter1 Compare Match B */
|
||||
#define TIMER1_COMPB_vect _VECTOR(13)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(13)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(14)
|
||||
#define SIG_OVERFLOW1 _VECTOR(14)
|
||||
|
||||
/* Timer/Counter0 Compare Match */
|
||||
#define TIMER0_COMP_vect _VECTOR(15)
|
||||
#define SIG_OUTPUT_COMPARE0 _VECTOR(15)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(16)
|
||||
#define SIG_OVERFLOW0 _VECTOR(16)
|
||||
|
||||
/* SPI Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(17)
|
||||
#define SIG_SPI _VECTOR(17)
|
||||
|
||||
/* UART, Rx Complete */
|
||||
#define UART_RX_vect _VECTOR(18)
|
||||
#define SIG_UART_RECV _VECTOR(18)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(19)
|
||||
#define SIG_UART_DATA _VECTOR(19)
|
||||
|
||||
/* UART, Tx Complete */
|
||||
#define UART_TX_vect _VECTOR(20)
|
||||
#define SIG_UART_TRANS _VECTOR(20)
|
||||
|
||||
/* ADC Conversion Complete */
|
||||
#define ADC_vect _VECTOR(21)
|
||||
#define SIG_ADC _VECTOR(21)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_READY_vect _VECTOR(22)
|
||||
#define SIG_EEPROM_READY _VECTOR(22)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANALOG_COMP_vect _VECTOR(23)
|
||||
#define SIG_COMPARATOR _VECTOR(23)
|
||||
|
||||
#define _VECTORS_SIZE 96
|
||||
|
||||
/*
|
||||
The Register Bit names are represented by their bit number (0-7).
|
||||
*/
|
||||
|
||||
/* XDIV Divide control register*/
|
||||
#define XDIVEN 7
|
||||
#define XDIV6 6
|
||||
#define XDIV5 5
|
||||
#define XDIV4 4
|
||||
#define XDIV3 3
|
||||
#define XDIV2 2
|
||||
#define XDIV1 1
|
||||
#define XDIV0 0
|
||||
|
||||
/* RAM Page Z select register */
|
||||
#define RAMPZ0 0
|
||||
|
||||
/* External Interrupt Control Register */
|
||||
#define ISC71 7
|
||||
#define ISC70 6
|
||||
#define ISC61 5
|
||||
#define ISC60 4
|
||||
#define ISC51 3
|
||||
#define ISC50 2
|
||||
#define ISC41 1
|
||||
#define ISC40 0
|
||||
|
||||
/* External Interrupt MaSK register */
|
||||
#define INT7 7
|
||||
#define INT6 6
|
||||
#define INT5 5
|
||||
#define INT4 4
|
||||
#define INT3 3
|
||||
#define INT2 2
|
||||
#define INT1 1
|
||||
#define INT0 0
|
||||
|
||||
/* Èxternal Interrupt Flag Register */
|
||||
#define INTF7 7
|
||||
#define INTF6 6
|
||||
#define INTF5 5
|
||||
#define INTF4 4
|
||||
|
||||
/* Timer/Counter Interrupt MaSK register */
|
||||
#define OCIE2 7
|
||||
#define TOIE2 6
|
||||
#define TICIE1 5
|
||||
#define OCIE1A 4
|
||||
#define OCIE1B 3
|
||||
#define TOIE1 2
|
||||
#define OCIE0 1
|
||||
#define TOIE0 0
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define OCF2 7
|
||||
#define TOV2 6
|
||||
#define ICF1 5
|
||||
#define OCF1A 4
|
||||
#define OCF1B 3
|
||||
#define TOV1 2
|
||||
#define OCF0 1
|
||||
#define TOV0 0
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define SRE 7
|
||||
#define SRW 6
|
||||
#define SE 5
|
||||
#define SM1 4
|
||||
#define SM0 3
|
||||
|
||||
/* MCU Status Register */
|
||||
#define EXTRF 1
|
||||
#define PORF 0
|
||||
|
||||
/* Timer/Counter 0 Control Register */
|
||||
#define PWM0 6
|
||||
#define COM01 5
|
||||
#define COM00 4
|
||||
#define CTC0 3
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* Timer/Counter 0 Asynchronous Control & Status Register */
|
||||
#define AS0 3
|
||||
#define TCN0UB 2
|
||||
#define OCR0UB 1
|
||||
#define TCR0UB 0
|
||||
|
||||
/* Timer/Counter 1 Control Register */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* Timer/Counter 1 Control and Status Register */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* Timer/Counter 2 Control register */
|
||||
#define PWM2 6
|
||||
#define COM21 5
|
||||
#define COM20 4
|
||||
#define CTC2 3
|
||||
#define CS22 2
|
||||
#define CS21 1
|
||||
#define CS20 0
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* Data Register, Port E */
|
||||
#define PE7 7
|
||||
#define PE6 6
|
||||
#define PE5 5
|
||||
#define PE4 4
|
||||
#define PE3 3
|
||||
#define PE2 2
|
||||
#define PE1 1
|
||||
#define PE0 0
|
||||
|
||||
/* Data Direction Register, Port E */
|
||||
#define DDE7 7
|
||||
#define DDE6 6
|
||||
#define DDE5 5
|
||||
#define DDE4 4
|
||||
#define DDE3 3
|
||||
#define DDE2 2
|
||||
#define DDE1 1
|
||||
#define DDE0 0
|
||||
|
||||
/* Input Pins, Port E */
|
||||
#define PINE7 7
|
||||
#define PINE6 6
|
||||
#define PINE5 5
|
||||
#define PINE4 4
|
||||
#define PINE3 3
|
||||
#define PINE2 2
|
||||
#define PINE1 1
|
||||
#define PINE0 0
|
||||
|
||||
/* Input Pins, Port F */
|
||||
#define PINF7 7
|
||||
#define PINF6 6
|
||||
#define PINF5 5
|
||||
#define PINF4 4
|
||||
#define PINF3 3
|
||||
#define PINF2 2
|
||||
#define PINF1 1
|
||||
#define PINF0 0
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* UART Status Register */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
|
||||
/* UART Control Register */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACD 7
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* ADC Control and status register */
|
||||
#define ADEN 7
|
||||
#define ADSC 6
|
||||
#define ADFR 5
|
||||
#define ADIF 4
|
||||
#define ADIE 3
|
||||
#define ADPS2 2
|
||||
#define ADPS1 1
|
||||
#define ADPS0 0
|
||||
|
||||
/* ADC Multiplexer select */
|
||||
#define MUX2 2
|
||||
#define MUX1 1
|
||||
#define MUX0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define RAMEND 0x0FFF /*Last On-Chip SRAM Location*/
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0x0FFF
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x1FFFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
|
||||
#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
|
||||
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
|
||||
#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */
|
||||
#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */
|
||||
#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x97
|
||||
#define SIGNATURE_2 0x01
|
||||
|
||||
|
||||
#endif /* _AVR_IOM103_H_ */
|
||||
1203
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom128.h
Normal file
1203
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom128.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,94 @@
|
|||
/* Copyright (c) 2005 Anatoly Sokolov
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iom1280.h,v 1.2.2.5 2008/10/17 23:27:46 arcanum Exp $ */
|
||||
|
||||
/* avr/iom1280.h - definitions for ATmega1280 */
|
||||
|
||||
#ifndef _AVR_IOM1280_H_
|
||||
#define _AVR_IOM1280_H_ 1
|
||||
|
||||
#include <avr/iomxx0_1.h>
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 256
|
||||
#define RAMEND 0x21FF
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0xFFF
|
||||
#define E2PAGESIZE 8
|
||||
#define FLASHEND 0x1FFFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 3
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
||||
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
||||
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
||||
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
||||
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
||||
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
||||
|
||||
/* High Fuse Byte */
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
||||
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
||||
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
||||
#define FUSE_WDTON (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
||||
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
||||
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
||||
|
||||
/* Extended Fuse Byte */
|
||||
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
|
||||
#define EFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x97
|
||||
#define SIGNATURE_2 0x03
|
||||
|
||||
|
||||
#endif /* _AVR_IOM1280_H_ */
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/* Copyright (c) 2005 Anatoly Sokolov
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iom1281.h,v 1.2.2.5 2008/10/17 23:27:47 arcanum Exp $ */
|
||||
|
||||
/* avr/iom1281.h - definitions for ATmega1281 */
|
||||
|
||||
#ifndef _AVR_IOM1281_H_
|
||||
#define _AVR_IOM1281_H_ 1
|
||||
|
||||
#include <avr/iomxx0_1.h>
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 256
|
||||
#define RAMEND 0x21FF
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0xFFF
|
||||
#define E2PAGESIZE 8
|
||||
#define FLASHEND 0x1FFFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 3
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
||||
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
||||
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
||||
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
||||
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
||||
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
||||
|
||||
/* High Fuse Byte */
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
||||
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
||||
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
||||
#define FUSE_WDTON (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
||||
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
||||
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
||||
|
||||
/* Extended Fuse Byte */
|
||||
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
|
||||
#define EFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x97
|
||||
#define SIGNATURE_2 0x04
|
||||
|
||||
|
||||
#endif /* _AVR_IOM1281_H_ */
|
||||
1132
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom1284p.h
Normal file
1132
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom1284p.h
Normal file
File diff suppressed because it is too large
Load diff
614
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom16.h
Normal file
614
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom16.h
Normal file
|
|
@ -0,0 +1,614 @@
|
|||
/* Copyright (c) 2004 Eric B. Weddington
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iom16.h,v 1.14.2.5 2008/10/17 23:27:47 arcanum Exp $ */
|
||||
|
||||
/* avr/iom16.h - definitions for ATmega16 */
|
||||
|
||||
#ifndef _AVR_IOM16_H_
|
||||
#define _AVR_IOM16_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "iom16.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* Registers and associated bit numbers */
|
||||
|
||||
#define TWBR _SFR_IO8(0x00)
|
||||
|
||||
#define TWSR _SFR_IO8(0x01)
|
||||
#define TWPS0 0
|
||||
#define TWPS1 1
|
||||
#define TWS3 3
|
||||
#define TWS4 4
|
||||
#define TWS5 5
|
||||
#define TWS6 6
|
||||
#define TWS7 7
|
||||
|
||||
#define TWAR _SFR_IO8(0x02)
|
||||
#define TWGCE 0
|
||||
#define TWA0 1
|
||||
#define TWA1 2
|
||||
#define TWA2 3
|
||||
#define TWA3 4
|
||||
#define TWA4 5
|
||||
#define TWA5 6
|
||||
#define TWA6 7
|
||||
|
||||
#define TWDR _SFR_IO8(0x03)
|
||||
|
||||
/* Combine ADCL and ADCH */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x04)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x04)
|
||||
#define ADCL _SFR_IO8(0x04)
|
||||
#define ADCH _SFR_IO8(0x05)
|
||||
|
||||
#define ADCSRA _SFR_IO8(0x06)
|
||||
#define ADPS0 0
|
||||
#define ADPS1 1
|
||||
#define ADPS2 2
|
||||
#define ADIE 3
|
||||
#define ADIF 4
|
||||
#define ADATE 5
|
||||
#define ADSC 6
|
||||
#define ADEN 7
|
||||
|
||||
#define ADMUX _SFR_IO8(0x07)
|
||||
#define MUX0 0
|
||||
#define MUX1 1
|
||||
#define MUX2 2
|
||||
#define MUX3 3
|
||||
#define MUX4 4
|
||||
#define ADLAR 5
|
||||
#define REFS0 6
|
||||
#define REFS1 7
|
||||
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
#define ACIS0 0
|
||||
#define ACIS1 1
|
||||
#define ACIC 2
|
||||
#define ACIE 3
|
||||
#define ACI 4
|
||||
#define ACO 5
|
||||
#define ACBG 6
|
||||
#define ACD 7
|
||||
|
||||
#define UBRRL _SFR_IO8(0x09)
|
||||
|
||||
#define UCSRB _SFR_IO8(0x0A)
|
||||
#define TXB8 0
|
||||
#define RXB8 1
|
||||
#define UCSZ2 2
|
||||
#define TXEN 3
|
||||
#define RXEN 4
|
||||
#define UDRIE 5
|
||||
#define TXCIE 6
|
||||
#define RXCIE 7
|
||||
|
||||
#define UCSRA _SFR_IO8(0x0B)
|
||||
#define MPCM 0
|
||||
#define U2X 1
|
||||
#define PE 2
|
||||
#define DOR 3
|
||||
#define FE 4
|
||||
#define UDRE 5
|
||||
#define TXC 6
|
||||
#define RXC 7
|
||||
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
#define SPR0 0
|
||||
#define SPR1 1
|
||||
#define CPHA 2
|
||||
#define CPOL 3
|
||||
#define MSTR 4
|
||||
#define DORD 5
|
||||
#define SPE 6
|
||||
#define SPIE 7
|
||||
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
#define SPI2X 0
|
||||
#define WCOL 6
|
||||
#define SPIF 7
|
||||
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
#define PIND0 0
|
||||
#define PIND1 1
|
||||
#define PIND2 2
|
||||
#define PIND3 3
|
||||
#define PIND4 4
|
||||
#define PIND5 5
|
||||
#define PIND6 6
|
||||
#define PIND7 7
|
||||
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
#define DDD0 0
|
||||
#define DDD1 1
|
||||
#define DDD2 2
|
||||
#define DDD3 3
|
||||
#define DDD4 4
|
||||
#define DDD5 5
|
||||
#define DDD6 6
|
||||
#define DDD7 7
|
||||
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
#define PD0 0
|
||||
#define PD1 1
|
||||
#define PD2 2
|
||||
#define PD3 3
|
||||
#define PD4 4
|
||||
#define PD5 5
|
||||
#define PD6 6
|
||||
#define PD7 7
|
||||
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
#define PINC0 0
|
||||
#define PINC1 1
|
||||
#define PINC2 2
|
||||
#define PINC3 3
|
||||
#define PINC4 4
|
||||
#define PINC5 5
|
||||
#define PINC6 6
|
||||
#define PINC7 7
|
||||
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
#define DDC0 0
|
||||
#define DDC1 1
|
||||
#define DDC2 2
|
||||
#define DDC3 3
|
||||
#define DDC4 4
|
||||
#define DDC5 5
|
||||
#define DDC6 6
|
||||
#define DDC7 7
|
||||
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
#define PC0 0
|
||||
#define PC1 1
|
||||
#define PC2 2
|
||||
#define PC3 3
|
||||
#define PC4 4
|
||||
#define PC5 5
|
||||
#define PC6 6
|
||||
#define PC7 7
|
||||
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
#define PINB0 0
|
||||
#define PINB1 1
|
||||
#define PINB2 2
|
||||
#define PINB3 3
|
||||
#define PINB4 4
|
||||
#define PINB5 5
|
||||
#define PINB6 6
|
||||
#define PINB7 7
|
||||
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
#define DDB0 0
|
||||
#define DDB1 1
|
||||
#define DDB2 2
|
||||
#define DDB3 3
|
||||
#define DDB4 4
|
||||
#define DDB5 5
|
||||
#define DDB6 6
|
||||
#define DDB7 7
|
||||
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
#define PB0 0
|
||||
#define PB1 1
|
||||
#define PB2 2
|
||||
#define PB3 3
|
||||
#define PB4 4
|
||||
#define PB5 5
|
||||
#define PB6 6
|
||||
#define PB7 7
|
||||
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
#define PINA0 0
|
||||
#define PINA1 1
|
||||
#define PINA2 2
|
||||
#define PINA3 3
|
||||
#define PINA4 4
|
||||
#define PINA5 5
|
||||
#define PINA6 6
|
||||
#define PINA7 7
|
||||
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
#define DDA0 0
|
||||
#define DDA1 1
|
||||
#define DDA2 2
|
||||
#define DDA3 3
|
||||
#define DDA4 4
|
||||
#define DDA5 5
|
||||
#define DDA6 6
|
||||
#define DDA7 7
|
||||
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
#define PA0 0
|
||||
#define PA1 1
|
||||
#define PA2 2
|
||||
#define PA3 3
|
||||
#define PA4 4
|
||||
#define PA5 5
|
||||
#define PA6 6
|
||||
#define PA7 7
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
#define EERE 0
|
||||
#define EEWE 1
|
||||
#define EEMWE 2
|
||||
#define EERIE 3
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO16(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
#define EEARH _SFR_IO8(0x1F)
|
||||
|
||||
#define UCSRC _SFR_IO8(0x20)
|
||||
#define UCPOL 0
|
||||
#define UCSZ0 1
|
||||
#define UCSZ1 2
|
||||
#define USBS 3
|
||||
#define UPM0 4
|
||||
#define UPM1 5
|
||||
#define UMSEL 6
|
||||
#define URSEL 7
|
||||
|
||||
#define UBRRH _SFR_IO8(0x20)
|
||||
#define URSEL 7
|
||||
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
#define WDP0 0
|
||||
#define WDP1 1
|
||||
#define WDP2 2
|
||||
#define WDE 3
|
||||
#define WDTOE 4
|
||||
|
||||
#define ASSR _SFR_IO8(0x22)
|
||||
#define TCR2UB 0
|
||||
#define OCR2UB 1
|
||||
#define TCN2UB 2
|
||||
#define AS2 3
|
||||
|
||||
#define OCR2 _SFR_IO8(0x23)
|
||||
|
||||
#define TCNT2 _SFR_IO8(0x24)
|
||||
|
||||
#define TCCR2 _SFR_IO8(0x25)
|
||||
#define CS20 0
|
||||
#define CS21 1
|
||||
#define CS22 2
|
||||
#define WGM21 3
|
||||
#define COM20 4
|
||||
#define COM21 5
|
||||
#define WGM20 6
|
||||
#define FOC2 7
|
||||
|
||||
/* Combine ICR1L and ICR1H */
|
||||
#define ICR1 _SFR_IO16(0x26)
|
||||
|
||||
#define ICR1L _SFR_IO8(0x26)
|
||||
#define ICR1H _SFR_IO8(0x27)
|
||||
|
||||
/* Combine OCR1BL and OCR1BH */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Combine OCR1AL and OCR1AH */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Combine TCNT1L and TCNT1H */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
#define CS10 0
|
||||
#define CS11 1
|
||||
#define CS12 2
|
||||
#define WGM12 3
|
||||
#define WGM13 4
|
||||
#define ICES1 6
|
||||
#define ICNC1 7
|
||||
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
#define WGM10 0
|
||||
#define WGM11 1
|
||||
#define FOC1B 2
|
||||
#define FOC1A 3
|
||||
#define COM1B0 4
|
||||
#define COM1B1 5
|
||||
#define COM1A0 6
|
||||
#define COM1A1 7
|
||||
|
||||
/*
|
||||
The ADHSM bit has been removed from all documentation,
|
||||
as being not needed at all since the comparator has proven
|
||||
to be fast enough even without feeding it more power.
|
||||
*/
|
||||
|
||||
#define SFIOR _SFR_IO8(0x30)
|
||||
#define PSR10 0
|
||||
#define PSR2 1
|
||||
#define PUD 2
|
||||
#define ACME 3
|
||||
#define ADTS0 5
|
||||
#define ADTS1 6
|
||||
#define ADTS2 7
|
||||
|
||||
#define OSCCAL _SFR_IO8(0x31)
|
||||
|
||||
#define OCDR _SFR_IO8(0x31)
|
||||
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
#define CS00 0
|
||||
#define CS01 1
|
||||
#define CS02 2
|
||||
#define WGM01 3
|
||||
#define COM00 4
|
||||
#define COM01 5
|
||||
#define WGM00 6
|
||||
#define FOC0 7
|
||||
|
||||
#define MCUCSR _SFR_IO8(0x34)
|
||||
#define PORF 0
|
||||
#define EXTRF 1
|
||||
#define BORF 2
|
||||
#define WDRF 3
|
||||
#define JTRF 4
|
||||
#define ISC2 6
|
||||
#define JTD 7
|
||||
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
#define ISC00 0
|
||||
#define ISC01 1
|
||||
#define ISC10 2
|
||||
#define ISC11 3
|
||||
#define SM0 4
|
||||
#define SM1 5
|
||||
#define SE 6
|
||||
#define SM2 7
|
||||
|
||||
#define TWCR _SFR_IO8(0x36)
|
||||
#define TWIE 0
|
||||
#define TWEN 2
|
||||
#define TWWC 3
|
||||
#define TWSTO 4
|
||||
#define TWSTA 5
|
||||
#define TWEA 6
|
||||
#define TWINT 7
|
||||
|
||||
#define SPMCR _SFR_IO8(0x37)
|
||||
#define SPMEN 0
|
||||
#define PGERS 1
|
||||
#define PGWRT 2
|
||||
#define BLBSET 3
|
||||
#define RWWSRE 4
|
||||
#define RWWSB 6
|
||||
#define SPMIE 7
|
||||
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
#define TOV0 0
|
||||
#define OCF0 1
|
||||
#define TOV1 2
|
||||
#define OCF1B 3
|
||||
#define OCF1A 4
|
||||
#define ICF1 5
|
||||
#define TOV2 6
|
||||
#define OCF2 7
|
||||
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
#define TOIE0 0
|
||||
#define OCIE0 1
|
||||
#define TOIE1 2
|
||||
#define OCIE1B 3
|
||||
#define OCIE1A 4
|
||||
#define TICIE1 5
|
||||
#define TOIE2 6
|
||||
#define OCIE2 7
|
||||
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
#define INTF2 5
|
||||
#define INTF0 6
|
||||
#define INTF1 7
|
||||
|
||||
#define GICR _SFR_IO8(0x3B)
|
||||
#define IVCE 0
|
||||
#define IVSEL 1
|
||||
#define INT2 5
|
||||
#define INT0 6
|
||||
#define INT1 7
|
||||
|
||||
#define OCR0 _SFR_IO8(0x3C)
|
||||
|
||||
/* SP [0x3D..0x3E] */
|
||||
/* SREG [0x3F] */
|
||||
|
||||
|
||||
/* Interrupt vectors */
|
||||
/* Vector 0 is the reset vector. */
|
||||
/* External Interrupt Request 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt Request 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter2 Compare Match */
|
||||
#define TIMER2_COMP_vect _VECTOR(3)
|
||||
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter2 Overflow */
|
||||
#define TIMER2_OVF_vect _VECTOR(4)
|
||||
#define SIG_OVERFLOW2 _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(5)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(6)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
|
||||
|
||||
/* Timer/Counter1 Compare Match B */
|
||||
#define TIMER1_COMPB_vect _VECTOR(7)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(8)
|
||||
#define SIG_OVERFLOW1 _VECTOR(8)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(9)
|
||||
#define SIG_OVERFLOW0 _VECTOR(9)
|
||||
|
||||
/* Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(10)
|
||||
#define SIG_SPI _VECTOR(10)
|
||||
|
||||
/* USART, Rx Complete */
|
||||
#define USART_RXC_vect _VECTOR(11)
|
||||
#define SIG_USART_RECV _VECTOR(11)
|
||||
#define SIG_UART_RECV _VECTOR(11)
|
||||
|
||||
/* USART Data Register Empty */
|
||||
#define USART_UDRE_vect _VECTOR(12)
|
||||
#define SIG_USART_DATA _VECTOR(12)
|
||||
#define SIG_UART_DATA _VECTOR(12)
|
||||
|
||||
/* USART, Tx Complete */
|
||||
#define USART_TXC_vect _VECTOR(13)
|
||||
#define SIG_USART_TRANS _VECTOR(13)
|
||||
#define SIG_UART_TRANS _VECTOR(13)
|
||||
|
||||
/* ADC Conversion Complete */
|
||||
#define ADC_vect _VECTOR(14)
|
||||
#define SIG_ADC _VECTOR(14)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_RDY_vect _VECTOR(15)
|
||||
#define SIG_EEPROM_READY _VECTOR(15)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(16)
|
||||
#define SIG_COMPARATOR _VECTOR(16)
|
||||
|
||||
/* 2-wire Serial Interface */
|
||||
#define TWI_vect _VECTOR(17)
|
||||
#define SIG_2WIRE_SERIAL _VECTOR(17)
|
||||
|
||||
/* External Interrupt Request 2 */
|
||||
#define INT2_vect _VECTOR(18)
|
||||
#define SIG_INTERRUPT2 _VECTOR(18)
|
||||
|
||||
/* Timer/Counter0 Compare Match */
|
||||
#define TIMER0_COMP_vect _VECTOR(19)
|
||||
#define SIG_OUTPUT_COMPARE0 _VECTOR(19)
|
||||
|
||||
/* Store Program Memory Ready */
|
||||
#define SPM_RDY_vect _VECTOR(20)
|
||||
#define SIG_SPM_READY _VECTOR(20)
|
||||
|
||||
#define _VECTORS_SIZE 84
|
||||
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 128
|
||||
#define RAMEND 0x45F
|
||||
#define XRAMEND 0x45F
|
||||
#define E2END 0x1FF
|
||||
#define E2PAGESIZE 4
|
||||
#define FLASHEND 0x3FFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 2
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
||||
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
||||
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
||||
#define FUSE_BODEN (unsigned char)~_BV(6)
|
||||
#define FUSE_BODLEVEL (unsigned char)~_BV(7)
|
||||
#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
|
||||
|
||||
/* High Fuse Byte */
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
||||
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
||||
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
||||
#define FUSE_CKOPT (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
||||
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
||||
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x94
|
||||
#define SIGNATURE_2 0x03
|
||||
|
||||
|
||||
#endif /* _AVR_IOM16_H_ */
|
||||
673
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom161.h
Normal file
673
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom161.h
Normal file
|
|
@ -0,0 +1,673 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iom161.h,v 1.10.2.5 2008/10/17 23:27:47 arcanum Exp $ */
|
||||
|
||||
/* avr/iom161.h - definitions for ATmega161 */
|
||||
|
||||
#ifndef _AVR_IOM161_H_
|
||||
#define _AVR_IOM161_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "iom161.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
/* UART1 Baud Rate Register */
|
||||
#define UBRR1 _SFR_IO8(0x00)
|
||||
|
||||
/* UART1 Control and Status Registers */
|
||||
#define UCSR1B _SFR_IO8(0x01)
|
||||
#define UCSR1A _SFR_IO8(0x02)
|
||||
|
||||
/* UART1 I/O Data Register */
|
||||
#define UDR1 _SFR_IO8(0x03)
|
||||
|
||||
/* 0x04 reserved */
|
||||
|
||||
/* Input Pins, Port E */
|
||||
#define PINE _SFR_IO8(0x05)
|
||||
|
||||
/* Data Direction Register, Port E */
|
||||
#define DDRE _SFR_IO8(0x06)
|
||||
|
||||
/* Data Register, Port E */
|
||||
#define PORTE _SFR_IO8(0x07)
|
||||
|
||||
/* Analog Comparator Control and Status Register */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART0 Baud Rate Register */
|
||||
#define UBRR0 _SFR_IO8(0x09)
|
||||
|
||||
/* UART0 Control and Status Registers */
|
||||
#define UCSR0B _SFR_IO8(0x0A)
|
||||
#define UCSR0A _SFR_IO8(0x0B)
|
||||
|
||||
/* UART0 I/O Data Register */
|
||||
#define UDR0 _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI Control Register */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
|
||||
/* SPI Status Register */
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
|
||||
/* SPI I/O Data Register */
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Input Pins, Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
|
||||
/* Data Direction Register, Port D */
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
|
||||
/* Data Register, Port D */
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Input Pins, Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
|
||||
/* Data Direction Register, Port C */
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
|
||||
/* Data Register, Port C */
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Input Pins, Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
|
||||
/* Data Direction Register, Port B */
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
|
||||
/* Data Register, Port B */
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Input Pins, Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
|
||||
/* Data Direction Register, Port A */
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
|
||||
/* Data Register, Port A */
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO16(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
#define EEARH _SFR_IO8(0x1F)
|
||||
|
||||
/* UART Baud Register HIgh */
|
||||
#define UBRRH _SFR_IO8(0x20)
|
||||
|
||||
/* Watchdog Timer Control Register */
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
/* Timer/Counter2 Output Compare Register */
|
||||
#define OCR2 _SFR_IO8(0x22)
|
||||
|
||||
/* Timer/Counter2 (8-bit) */
|
||||
#define TCNT2 _SFR_IO8(0x23)
|
||||
|
||||
/* Timer/Counter1 Input Capture Register */
|
||||
#define ICR1 _SFR_IO16(0x24)
|
||||
#define ICR1L _SFR_IO8(0x24)
|
||||
#define ICR1H _SFR_IO8(0x25)
|
||||
|
||||
/* ASynchronous mode Status Register */
|
||||
#define ASSR _SFR_IO8(0x26)
|
||||
|
||||
/* Timer/Counter2 Control Register */
|
||||
#define TCCR2 _SFR_IO8(0x27)
|
||||
|
||||
/* Timer/Counter1 Output Compare RegisterB */
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
|
||||
/* Timer/Counter1 Output Compare RegisterA */
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
|
||||
/* Timer/Counter1 */
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
|
||||
/* Timer/Counter1 Control Register B */
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
|
||||
/* Timer/Counter1 Control Register A */
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
/* Special Function IO Register */
|
||||
#define SFIOR _SFR_IO8(0x30)
|
||||
|
||||
/* Timer/Counter0 Output Compare Register */
|
||||
#define OCR0 _SFR_IO8(0x31)
|
||||
|
||||
/* Timer/Counter0 (8-bit) */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
|
||||
/* Timer/Counter0 Control Register */
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
/* MCU general Status Register */
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
|
||||
/* MCU general Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
/* Extended MCU general Control Register */
|
||||
#define EMCUCR _SFR_IO8(0x36)
|
||||
|
||||
/* Store Program Memory Control Register */
|
||||
#define SPMCR _SFR_IO8(0x37)
|
||||
|
||||
/* Timer/Counter Interrupt Flag Register */
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
|
||||
/* Timer/Counter Interrupt MaSK Register */
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
/* General Interrupt Flag Register */
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
|
||||
/* General Interrupt MaSK register */
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3C reserved */
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* External Interrupt 2 */
|
||||
#define INT2_vect _VECTOR(3)
|
||||
#define SIG_INTERRUPT2 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter2 Compare Match */
|
||||
#define TIMER2_COMP_vect _VECTOR(4)
|
||||
#define SIG_OUTPUT_COMPARE2 _VECTOR(4)
|
||||
|
||||
/* Timer/Counter2 Overflow */
|
||||
#define TIMER2_OVF_vect _VECTOR(5)
|
||||
#define SIG_OVERFLOW2 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter1 Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(6)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(6)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(7)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(7)
|
||||
|
||||
/* Timer/Counter1 Compare Match B */
|
||||
#define TIMER1_COMPB_vect _VECTOR(8)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(8)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(9)
|
||||
#define SIG_OVERFLOW1 _VECTOR(9)
|
||||
|
||||
/* Timer/Counter0 Compare Match */
|
||||
#define TIMER0_COMP_vect _VECTOR(10)
|
||||
#define SIG_OUTPUT_COMPARE0 _VECTOR(10)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(11)
|
||||
#define SIG_OVERFLOW0 _VECTOR(11)
|
||||
|
||||
/* Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(12)
|
||||
#define SIG_SPI _VECTOR(12)
|
||||
|
||||
/* UART0, Rx Complete */
|
||||
#define UART0_RX_vect _VECTOR(13)
|
||||
#define SIG_UART0_RECV _VECTOR(13)
|
||||
|
||||
/* UART1, Rx Complete */
|
||||
#define UART1_RX_vect _VECTOR(14)
|
||||
#define SIG_UART1_RECV _VECTOR(14)
|
||||
|
||||
/* UART0 Data Register Empty */
|
||||
#define UART0_UDRE_vect _VECTOR(15)
|
||||
#define SIG_UART0_DATA _VECTOR(15)
|
||||
|
||||
/* UART1 Data Register Empty */
|
||||
#define UART1_UDRE_vect _VECTOR(16)
|
||||
#define SIG_UART1_DATA _VECTOR(16)
|
||||
|
||||
/* UART0, Tx Complete */
|
||||
#define UART0_TX_vect _VECTOR(17)
|
||||
#define SIG_UART0_TRANS _VECTOR(17)
|
||||
|
||||
/* UART1, Tx Complete */
|
||||
#define UART1_TX_vect _VECTOR(18)
|
||||
#define SIG_UART1_TRANS _VECTOR(18)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_RDY_vect _VECTOR(19)
|
||||
#define SIG_EEPROM_READY _VECTOR(19)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(20)
|
||||
#define SIG_COMPARATOR _VECTOR(20)
|
||||
|
||||
#define _VECTORS_SIZE 84
|
||||
|
||||
/* Bit numbers */
|
||||
|
||||
/* GIMSK */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
#define INT2 5
|
||||
|
||||
/* GIFR */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
#define INTF2 5
|
||||
|
||||
/* TIMSK */
|
||||
#define TOIE1 7
|
||||
#define OCIE1A 6
|
||||
#define OCIE1B 5
|
||||
#define TOIE2 4
|
||||
#define TICIE1 3
|
||||
#define OCIE2 2
|
||||
#define TOIE0 1
|
||||
#define OCIE0 0
|
||||
|
||||
/* TIFR */
|
||||
#define TOV1 7
|
||||
#define OCF1A 6
|
||||
#define OCF1B 5
|
||||
#define TOV2 4
|
||||
#define ICF1 3
|
||||
#define OCF2 2
|
||||
#define TOV0 1
|
||||
#define OCF0 0
|
||||
|
||||
/* MCUCR */
|
||||
#define SRE 7
|
||||
#define SRW10 6
|
||||
#define SE 5
|
||||
#define SM1 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* EMCUCR */
|
||||
#define SM0 7
|
||||
#define SRL2 6
|
||||
#define SRL1 5
|
||||
#define SRL0 4
|
||||
#define SRW01 3
|
||||
#define SRW00 2
|
||||
#define SRW11 1
|
||||
#define ISC2 0
|
||||
|
||||
/* SPMCR */
|
||||
#define BLBSET 3
|
||||
#define PGWRT 2
|
||||
#define PGERS 1
|
||||
#define SPMEN 0
|
||||
|
||||
/* SFIOR */
|
||||
#define PSR2 1
|
||||
#define PSR10 0
|
||||
|
||||
/* TCCR0 */
|
||||
#define FOC0 7
|
||||
#define PWM0 6
|
||||
#define COM01 5
|
||||
#define COM00 4
|
||||
#define CTC0 3
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* TCCR2 */
|
||||
#define FOC2 7
|
||||
#define PWM2 6
|
||||
#define COM21 5
|
||||
#define COM20 4
|
||||
#define CTC2 3
|
||||
#define CS22 2
|
||||
#define CS21 1
|
||||
#define CS20 0
|
||||
|
||||
/* ASSR */
|
||||
#define AS2 3
|
||||
#define TCN2UB 2
|
||||
#define OCR2UB 1
|
||||
#define TCR2UB 0
|
||||
|
||||
/* TCCR1A */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define FOC1A 3
|
||||
#define FOC1B 2
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* TCCR1B */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* WDTCR */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* PORTA */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* DDRA */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* PINA */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/*
|
||||
PB7 = SCK
|
||||
PB6 = MISO
|
||||
PB5 = MOSI
|
||||
PB4 = SS#
|
||||
PB3 = TXD1 / AIN1
|
||||
PB2 = RXD1 / AIN0
|
||||
PB1 = OC2 / T1
|
||||
PB0 = OC0 / T0
|
||||
*/
|
||||
|
||||
/* PORTB */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* DDRB */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* PINB */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/* PORTC */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* DDRC */
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* PINC */
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/*
|
||||
PD7 = RD#
|
||||
PD6 = WR#
|
||||
PD5 = TOSC2 / OC1A
|
||||
PD4 = TOSC1
|
||||
PD3 = INT1
|
||||
PD2 = INT0
|
||||
PD1 = TXD0
|
||||
PD0 = RXD0
|
||||
*/
|
||||
|
||||
/* PORTD */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* DDRD */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* PIND */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/*
|
||||
PE2 = ALE
|
||||
PE1 = OC1B
|
||||
PE0 = ICP / INT2
|
||||
*/
|
||||
|
||||
/* PORTE */
|
||||
#define PE2 2
|
||||
#define PE1 1
|
||||
#define PE0 0
|
||||
|
||||
/* DDRE */
|
||||
#define DDE2 2
|
||||
#define DDE1 1
|
||||
#define DDE0 0
|
||||
|
||||
/* PINE */
|
||||
#define PINE2 2
|
||||
#define PINE1 1
|
||||
#define PINE0 0
|
||||
|
||||
/* SPSR */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
#define SPI2X 0
|
||||
|
||||
/* SPCR */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* UCSR0A, UCSR1A */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
#define U2X 1
|
||||
#define MPCM 0
|
||||
|
||||
/* UCSR0B, UCSR1B */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* ACSR */
|
||||
#define ACD 7
|
||||
#define AINBG 6
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 128
|
||||
#define RAMEND 0x45F
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0x1FF
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x3FFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 1
|
||||
|
||||
/* Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_SUT (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(6)
|
||||
#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x94
|
||||
#define SIGNATURE_2 0x01
|
||||
|
||||
|
||||
#endif /* _AVR_IOM161_H_ */
|
||||
951
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom162.h
Normal file
951
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom162.h
Normal file
|
|
@ -0,0 +1,951 @@
|
|||
/* Copyright (c) 2002, Nils Kristian Strom <nilsst@omegav.ntnu.no>
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iom162.h,v 1.13.2.5 2008/10/17 23:27:47 arcanum Exp $ */
|
||||
|
||||
/* iom162.h - definitions for ATmega162 */
|
||||
|
||||
#ifndef _AVR_IOM162_H_
|
||||
#define _AVR_IOM162_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "iom162.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* Memory mapped I/O registers */
|
||||
|
||||
/* Timer/Counter3 Control Register A */
|
||||
#define TCCR3A _SFR_MEM8(0x8B)
|
||||
|
||||
/* Timer/Counter3 Control Register B */
|
||||
#define TCCR3B _SFR_MEM8(0x8A)
|
||||
|
||||
/* Timer/Counter3 - Counter Register */
|
||||
#define TCNT3H _SFR_MEM8(0x89)
|
||||
#define TCNT3L _SFR_MEM8(0x88)
|
||||
#define TCNT3 _SFR_MEM16(0x88)
|
||||
|
||||
/* Timer/Counter3 - Output Compare Register A */
|
||||
#define OCR3AH _SFR_MEM8(0x87)
|
||||
#define OCR3AL _SFR_MEM8(0x86)
|
||||
#define OCR3A _SFR_MEM16(0x86)
|
||||
|
||||
/* Timer/Counter3 - Output Compare Register B */
|
||||
#define OCR3BH _SFR_MEM8(0x85)
|
||||
#define OCR3BL _SFR_MEM8(0x84)
|
||||
#define OCR3B _SFR_MEM16(0x84)
|
||||
|
||||
/* Timer/Counter3 - Input Capture Register */
|
||||
#define ICR3H _SFR_MEM8(0x81)
|
||||
#define ICR3L _SFR_MEM8(0x80)
|
||||
#define ICR3 _SFR_MEM16(0x80)
|
||||
|
||||
/* Extended Timer/Counter Interrupt Mask */
|
||||
#define ETIMSK _SFR_MEM8(0x7D)
|
||||
|
||||
/* Extended Timer/Counter Interrupt Flag Register */
|
||||
#define ETIFR _SFR_MEM8(0x7C)
|
||||
|
||||
/* Pin Change Mask Register 1 */
|
||||
#define PCMSK1 _SFR_MEM8(0x6C)
|
||||
|
||||
/* Pin Change Mask Register 0 */
|
||||
#define PCMSK0 _SFR_MEM8(0x6B)
|
||||
|
||||
/* Clock PRescale */
|
||||
#define CLKPR _SFR_MEM8(0x61)
|
||||
|
||||
|
||||
/* Standard I/O registers */
|
||||
|
||||
/* 0x3F SREG */
|
||||
/* 0x3D..0x3E SP */
|
||||
#define UBRR1H _SFR_IO8(0x3C) /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */
|
||||
#define UCSR1C _SFR_IO8(0x3C) /* USART 1 Control and Status Register, Shared with UBRR1H */
|
||||
#define GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */
|
||||
#define GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */
|
||||
#define TIMSK _SFR_IO8(0x39) /* Timer Interrupt Mask */
|
||||
#define TIFR _SFR_IO8(0x38) /* Timer Interrupt Flag Register */
|
||||
#define SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */
|
||||
#define EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */
|
||||
#define MCUCR _SFR_IO8(0x35) /* MCU Control Register */
|
||||
#define MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */
|
||||
#define TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */
|
||||
#define TCNT0 _SFR_IO8(0x32) /* TImer/Counter 0 */
|
||||
#define OCR0 _SFR_IO8(0x31) /* Output Compare Register 0 */
|
||||
#define SFIOR _SFR_IO8(0x30) /* Special Function I/O Register */
|
||||
#define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register A */
|
||||
#define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register A */
|
||||
#define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 High Byte */
|
||||
#define TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 Low Byte */
|
||||
#define TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 */
|
||||
#define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 Output Compare Register A High Byte */
|
||||
#define OCR1AL _SFR_IO8(0x2A) /* Timer/Counter 1 Output Compare Register A Low Byte */
|
||||
#define OCR1A _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */
|
||||
#define OCR1BH _SFR_IO8(0x29) /* Timer/Counter 1 Output Compare Register B High Byte */
|
||||
#define OCR1BL _SFR_IO8(0x28) /* Timer/Counter 1 Output Compare Register B Low Byte */
|
||||
#define OCR1B _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */
|
||||
#define TCCR2 _SFR_IO8(0x27) /* Timer/Counter 2 Control Register */
|
||||
#define ASSR _SFR_IO8(0x26) /* Asynchronous Status Register */
|
||||
#define ICR1H _SFR_IO8(0x25) /* Input Capture Register 1 High Byte */
|
||||
#define ICR1L _SFR_IO8(0x24) /* Input Capture Register 1 Low Byte */
|
||||
#define ICR1 _SFR_IO16(0x24) /* Input Capture Register 1 */
|
||||
#define TCNT2 _SFR_IO8(0x23) /* Timer/Counter 2 */
|
||||
#define OCR2 _SFR_IO8(0x22) /* Timer/Counter 2 Output Compare Register */
|
||||
#define WDTCR _SFR_IO8(0x21) /* Watchdow Timer Control Register */
|
||||
#define UBRR0H _SFR_IO8(0x20) /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */
|
||||
#define UCSR0C _SFR_IO8(0x20) /* USART 0 Control and Status Register C, Shared with UBRR0H */
|
||||
#define EEARH _SFR_IO8(0x1F) /* EEPROM Address Register High Byte */
|
||||
#define EEARL _SFR_IO8(0x1E) /* EEPROM Address Register Low Byte */
|
||||
#define EEAR _SFR_IO16(0x1E) /* EEPROM Address Register */
|
||||
#define EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */
|
||||
#define EECR _SFR_IO8(0x1C) /* EEPROM Control Register */
|
||||
#define PORTA _SFR_IO8(0x1B) /* Port A */
|
||||
#define DDRA _SFR_IO8(0x1A) /* Port A Data Direction Register */
|
||||
#define PINA _SFR_IO8(0x19) /* Port A Pin Register */
|
||||
#define PORTB _SFR_IO8(0x18) /* Port B */
|
||||
#define DDRB _SFR_IO8(0x17) /* Port B Data Direction Register */
|
||||
#define PINB _SFR_IO8(0x16) /* Port B Pin Register */
|
||||
#define PORTC _SFR_IO8(0x15) /* Port C */
|
||||
#define DDRC _SFR_IO8(0x14) /* Port C Data Direction Register */
|
||||
#define PINC _SFR_IO8(0x13) /* Port C Pin Register */
|
||||
#define PORTD _SFR_IO8(0x12) /* Port D */
|
||||
#define DDRD _SFR_IO8(0x11) /* Port D Data Direction Register */
|
||||
#define PIND _SFR_IO8(0x10) /* Port D Pin Register */
|
||||
#define SPDR _SFR_IO8(0x0F) /* SPI Data Register */
|
||||
#define SPSR _SFR_IO8(0x0E) /* SPI Status Register */
|
||||
#define SPCR _SFR_IO8(0x0D) /* SPI Control Register */
|
||||
#define UDR0 _SFR_IO8(0x0C) /* USART 0 Data Register */
|
||||
#define UCSR0A _SFR_IO8(0x0B) /* USART 0 Control and Status Register A */
|
||||
#define UCSR0B _SFR_IO8(0x0A) /* USART 0 Control and Status Register B */
|
||||
#define UBRR0L _SFR_IO8(0x09) /* USART 0 Baud-Rate Register Low Byte */
|
||||
#define ACSR _SFR_IO8(0x08) /* Analog Comparator Status Register */
|
||||
#define PORTE _SFR_IO8(0x07) /* Port E */
|
||||
#define DDRE _SFR_IO8(0x06) /* Port E Data Direction Register */
|
||||
#define PINE _SFR_IO8(0x05) /* Port E Pin Register */
|
||||
#define OSCCAL _SFR_IO8(0x04) /* Oscillator Calibration, Shared with OCDR */
|
||||
#define OCDR _SFR_IO8(0x04) /* On-Chip Debug Register, Shared with OSCCAL */
|
||||
#define UDR1 _SFR_IO8(0x03) /* USART 1 Data Register */
|
||||
#define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */
|
||||
#define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */
|
||||
#define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */
|
||||
|
||||
|
||||
/* Interrupt vectors (byte addresses) */
|
||||
|
||||
/* External Interrupt Request 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt Request 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* External Interrupt Request 2 */
|
||||
#define INT2_vect _VECTOR(3)
|
||||
#define SIG_INTERRUPT2 _VECTOR(3)
|
||||
|
||||
/* Pin Change Interrupt Request 0 */
|
||||
#define PCINT0_vect _VECTOR(4)
|
||||
#define SIG_PIN_CHANGE0 _VECTOR(4)
|
||||
|
||||
/* Pin Change Interrupt Request 1 */
|
||||
#define PCINT1_vect _VECTOR(5)
|
||||
#define SIG_PIN_CHANGE1 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter3 Capture Event */
|
||||
#define TIMER3_CAPT_vect _VECTOR(6)
|
||||
#define SIG_INPUT_CAPTURE3 _VECTOR(6)
|
||||
|
||||
/* Timer/Counter3 Compare Match A */
|
||||
#define TIMER3_COMPA_vect _VECTOR(7)
|
||||
#define SIG_OUTPUT_COMPARE3A _VECTOR(7)
|
||||
|
||||
/* Timer/Counter3 Compare Match B */
|
||||
#define TIMER3_COMPB_vect _VECTOR(8)
|
||||
#define SIG_OUTPUT_COMPARE3B _VECTOR(8)
|
||||
|
||||
/* Timer/Counter3 Overflow */
|
||||
#define TIMER3_OVF_vect _VECTOR(9)
|
||||
#define SIG_OVERFLOW3 _VECTOR(9)
|
||||
|
||||
/* Timer/Counter2 Compare Match */
|
||||
#define TIMER2_COMP_vect _VECTOR(10)
|
||||
#define SIG_OUTPUT_COMPARE2 _VECTOR(10)
|
||||
|
||||
/* Timer/Counter2 Overflow */
|
||||
#define TIMER2_OVF_vect _VECTOR(11)
|
||||
#define SIG_OVERFLOW2 _VECTOR(11)
|
||||
|
||||
/* Timer/Counter1 Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(12)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(12)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(13)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(13)
|
||||
|
||||
/* Timer/Counter Compare Match B */
|
||||
#define TIMER1_COMPB_vect _VECTOR(14)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(14)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(15)
|
||||
#define SIG_OVERFLOW1 _VECTOR(15)
|
||||
|
||||
/* Timer/Counter0 Compare Match */
|
||||
#define TIMER0_COMP_vect _VECTOR(16)
|
||||
#define SIG_OUTPUT_COMPARE0 _VECTOR(16)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(17)
|
||||
#define SIG_OVERFLOW0 _VECTOR(17)
|
||||
|
||||
/* SPI Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(18)
|
||||
#define SIG_SPI _VECTOR(18)
|
||||
|
||||
/* USART0, Rx Complete */
|
||||
#define USART0_RXC_vect _VECTOR(19)
|
||||
#define SIG_USART0_RECV _VECTOR(19)
|
||||
|
||||
/* USART1, Rx Complete */
|
||||
#define USART1_RXC_vect _VECTOR(20)
|
||||
#define SIG_USART1_RECV _VECTOR(20)
|
||||
|
||||
/* USART0 Data register Empty */
|
||||
#define USART0_UDRE_vect _VECTOR(21)
|
||||
#define SIG_USART0_DATA _VECTOR(21)
|
||||
|
||||
/* USART1, Data register Empty */
|
||||
#define USART1_UDRE_vect _VECTOR(22)
|
||||
#define SIG_USART1_DATA _VECTOR(22)
|
||||
|
||||
/* USART0, Tx Complete */
|
||||
#define USART0_TXC_vect _VECTOR(23)
|
||||
#define SIG_USART0_TRANS _VECTOR(23)
|
||||
|
||||
/* USART1, Tx Complete */
|
||||
#define USART1_TXC_vect _VECTOR(24)
|
||||
#define SIG_USART1_TRANS _VECTOR(24)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_RDY_vect _VECTOR(25)
|
||||
#define SIG_EEPROM_READY _VECTOR(25)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(26)
|
||||
#define SIG_COMPARATOR _VECTOR(26)
|
||||
|
||||
/* Store Program Memory Read */
|
||||
#define SPM_RDY_vect _VECTOR(27)
|
||||
#define SIG_SPM_READY _VECTOR(27)
|
||||
|
||||
#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* TCCR3B bit definitions, memory mapped I/O */
|
||||
|
||||
#define ICNC3 7
|
||||
#define ICES3 6
|
||||
#define WGM33 4
|
||||
#define WGM32 3
|
||||
#define CS32 2
|
||||
#define CS31 1
|
||||
#define CS30 0
|
||||
|
||||
|
||||
|
||||
/* TCCR3A bit definitions, memory mapped I/O */
|
||||
|
||||
#define COM3A1 7
|
||||
#define COM3A0 6
|
||||
#define COM3B1 5
|
||||
#define COM3B0 4
|
||||
#define FOC3A 3
|
||||
#define FOC3B 2
|
||||
#define WGM31 1
|
||||
#define WGM30 0
|
||||
|
||||
|
||||
|
||||
/* ETIMSK bit definitions, memory mapped I/O */
|
||||
|
||||
#define TICIE3 5
|
||||
#define OCIE3A 4
|
||||
#define OCIE3B 3
|
||||
#define TOIE3 2
|
||||
|
||||
|
||||
|
||||
/* ETIFR bit definitions, memory mapped I/O */
|
||||
|
||||
#define ICF3 5
|
||||
#define OCF3A 4
|
||||
#define OCF3B 3
|
||||
#define TOV3 2
|
||||
|
||||
|
||||
|
||||
/* PCMSK1 bit definitions, memory mapped I/O */
|
||||
#define PCINT15 7
|
||||
#define PCINT14 6
|
||||
#define PCINT13 5
|
||||
#define PCINT12 4
|
||||
#define PCINT11 3
|
||||
#define PCINT10 2
|
||||
#define PCINT9 1
|
||||
#define PCINT8 0
|
||||
|
||||
|
||||
|
||||
/* PCMSK0 bit definitions, memory mapped I/O */
|
||||
|
||||
#define PCINT7 7
|
||||
#define PCINT6 6
|
||||
#define PCINT5 5
|
||||
#define PCINT4 4
|
||||
#define PCINT3 3
|
||||
#define PCINT2 2
|
||||
#define PCINT1 1
|
||||
#define PCINT0 0
|
||||
|
||||
|
||||
|
||||
/* CLKPR bit definitions, memory mapped I/O */
|
||||
|
||||
#define CLKPCE 7
|
||||
#define CLKPS3 3
|
||||
#define CLKPS2 2
|
||||
#define CLKPS1 1
|
||||
#define CLKPS0 0
|
||||
|
||||
|
||||
|
||||
/* SPH bit definitions */
|
||||
|
||||
#define SP15 15
|
||||
#define SP14 14
|
||||
#define SP13 13
|
||||
#define SP12 12
|
||||
#define SP11 11
|
||||
#define SP10 10
|
||||
#define SP9 9
|
||||
#define SP8 8
|
||||
|
||||
|
||||
|
||||
/* SPL bit definitions */
|
||||
|
||||
#define SP7 7
|
||||
#define SP6 6
|
||||
#define SP5 5
|
||||
#define SP4 4
|
||||
#define SP3 3
|
||||
#define SP2 2
|
||||
#define SP1 1
|
||||
#define SP0 0
|
||||
|
||||
|
||||
|
||||
/* UBRR1H bit definitions */
|
||||
|
||||
#define URSEL1 7
|
||||
#define UBRR111 3
|
||||
#define UBRR110 2
|
||||
#define UBRR19 1
|
||||
#define UBRR18 0
|
||||
|
||||
|
||||
|
||||
/* UCSR1C bit definitions */
|
||||
|
||||
#define URSEL1 7
|
||||
#define UMSEL1 6
|
||||
#define UPM11 5
|
||||
#define UPM10 4
|
||||
#define USBS1 3
|
||||
#define UCSZ11 2
|
||||
#define UCSZ10 1
|
||||
#define UCPOL1 0
|
||||
|
||||
|
||||
|
||||
/* GICR bit definitions */
|
||||
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
#define INT2 5
|
||||
#define PCIE1 4
|
||||
#define PCIE0 3
|
||||
#define IVSEL 1
|
||||
#define IVCE 0
|
||||
|
||||
|
||||
|
||||
/* GIFR bit definitions */
|
||||
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
#define INTF2 5
|
||||
#define PCIF1 4
|
||||
#define PCIF0 3
|
||||
|
||||
|
||||
|
||||
/* TIMSK bit definitions */
|
||||
|
||||
#define TOIE1 7
|
||||
#define OCIE1A 6
|
||||
#define OCIE1B 5
|
||||
#define OCIE2 4
|
||||
#define TICIE1 3
|
||||
#define TOIE2 2
|
||||
#define TOIE0 1
|
||||
#define OCIE0 0
|
||||
|
||||
|
||||
|
||||
/* TIFR bit definitions */
|
||||
|
||||
#define TOV1 7
|
||||
#define OCF1A 6
|
||||
#define OCF1B 5
|
||||
#define OCF2 4
|
||||
#define ICF1 3
|
||||
#define TOV2 2
|
||||
#define TOV0 1
|
||||
#define OCF0 0
|
||||
|
||||
|
||||
|
||||
/* SPMCR bit definitions */
|
||||
|
||||
#define SPMIE 7
|
||||
#define RWWSB 6
|
||||
#define RWWSRE 4
|
||||
#define BLBSET 3
|
||||
#define PGWRT 2
|
||||
#define PGERS 1
|
||||
#define SPMEN 0
|
||||
|
||||
|
||||
|
||||
/* EMCUCR bit definitions */
|
||||
|
||||
#define SM0 7
|
||||
#define SRL2 6
|
||||
#define SRL1 5
|
||||
#define SRL0 4
|
||||
#define SRW01 3
|
||||
#define SRW00 2
|
||||
#define SRW11 1
|
||||
#define ISC2 0
|
||||
|
||||
|
||||
|
||||
/* MCUCR bit definitions */
|
||||
|
||||
#define SRE 7
|
||||
#define SRW10 6
|
||||
#define SE 5
|
||||
#define SM1 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
|
||||
|
||||
/* MCUCSR bit definitions */
|
||||
|
||||
#define JTD 7
|
||||
#define SM2 5
|
||||
#define JTRF 4
|
||||
#define WDRF 3
|
||||
#define BORF 2
|
||||
#define EXTRF 1
|
||||
#define PORF 0
|
||||
|
||||
|
||||
|
||||
/* TCCR0 bit definitions */
|
||||
|
||||
#define FOC0 7
|
||||
#define WGM00 6
|
||||
#define COM01 5
|
||||
#define COM00 4
|
||||
#define WGM01 3
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
|
||||
|
||||
/* SFIOR bit definitions */
|
||||
|
||||
#define TSM 7
|
||||
#define XMBK 6
|
||||
#define XMM2 5
|
||||
#define XMM1 4
|
||||
#define XMM0 3
|
||||
#define PUD 2
|
||||
#define PSR2 1
|
||||
#define PSR310 0
|
||||
|
||||
|
||||
|
||||
/* TCCR1A bit definitions */
|
||||
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define FOC1A 3
|
||||
#define FOC1B 2
|
||||
#define WGM11 1
|
||||
#define WGM10 0
|
||||
|
||||
|
||||
|
||||
|
||||
/* TCCR1B bit definitions */
|
||||
|
||||
#define ICNC1 7 /* Input Capture Noise Canceler */
|
||||
#define ICES1 6 /* Input Capture Edge Select */
|
||||
#define WGM13 4 /* Waveform Generation Mode 3 */
|
||||
#define WGM12 3 /* Waveform Generation Mode 2 */
|
||||
#define CS12 2 /* Clock Select 2 */
|
||||
#define CS11 1 /* Clock Select 1 */
|
||||
#define CS10 0 /* Clock Select 0 */
|
||||
|
||||
|
||||
|
||||
/* TCCR2 bit definitions */
|
||||
|
||||
#define FOC2 7
|
||||
#define WGM20 6
|
||||
#define COM21 5
|
||||
#define COM20 4
|
||||
#define WGM21 3
|
||||
#define CS22 2
|
||||
#define CS21 1
|
||||
#define CS20 0
|
||||
|
||||
|
||||
|
||||
/* ASSR bit definitions */
|
||||
|
||||
#define AS2 3
|
||||
#define TCON2UB 2
|
||||
#define OCR2UB 1
|
||||
#define TCR2UB 0
|
||||
|
||||
|
||||
|
||||
/* WDTCR bit definitions */
|
||||
|
||||
#define WDCE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
|
||||
|
||||
/* UBRR0H bif definitions */
|
||||
|
||||
#define URSEL0 7
|
||||
#define UBRR011 3
|
||||
#define UBRR010 2
|
||||
#define UBRR09 1
|
||||
#define UBRR08 0
|
||||
|
||||
|
||||
|
||||
/* UCSR0C bit definitions */
|
||||
|
||||
#define URSEL0 7
|
||||
#define UMSEL0 6
|
||||
#define UPM01 5
|
||||
#define UPM00 4
|
||||
#define USBS0 3
|
||||
#define UCSZ01 2
|
||||
#define UCSZ00 1
|
||||
#define UCPOL0 0
|
||||
|
||||
|
||||
|
||||
/* EEARH bit definitions */
|
||||
|
||||
#define EEAR8 0
|
||||
|
||||
|
||||
|
||||
/* EECR bit definitions */
|
||||
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
|
||||
|
||||
/* PORTA bit definitions */
|
||||
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
|
||||
|
||||
/* DDRA bit definitions */
|
||||
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
|
||||
|
||||
/* PINA bit definitions */
|
||||
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
|
||||
/* PORTB bit definitions */
|
||||
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
|
||||
|
||||
/* DDRB bit definitions */
|
||||
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
|
||||
|
||||
/* PINB bit definitions */
|
||||
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
|
||||
|
||||
/* PORTC bit definitions */
|
||||
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
|
||||
|
||||
/* DDRC bit definitions */
|
||||
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
|
||||
|
||||
/* PINC bit definitions */
|
||||
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
|
||||
|
||||
/* PORTD bit definitions */
|
||||
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
|
||||
|
||||
/* DDRD bit definitions */
|
||||
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
|
||||
|
||||
/* PIND bit definitions */
|
||||
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
|
||||
|
||||
/* SPSR bit definitions */
|
||||
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
#define SPI2X 0
|
||||
|
||||
|
||||
|
||||
/* SPCR bit definitions */
|
||||
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
|
||||
|
||||
/* UCSR0A bit definitions */
|
||||
|
||||
#define RXC0 7
|
||||
#define TXC0 6
|
||||
#define UDRE0 5
|
||||
#define FE0 4
|
||||
#define DOR0 3
|
||||
#define UPE0 2
|
||||
#define U2X0 1
|
||||
#define MPCM0 0
|
||||
|
||||
|
||||
|
||||
/* UCSR0B bit definitions */
|
||||
|
||||
#define RXCIE0 7
|
||||
#define TXCIE0 6
|
||||
#define UDRIE0 5
|
||||
#define RXEN0 4
|
||||
#define TXEN0 3
|
||||
#define UCSZ02 2
|
||||
#define RXB80 1
|
||||
#define TXB80 0
|
||||
|
||||
|
||||
|
||||
/* ACSR bit definitions */
|
||||
|
||||
#define ACD 7
|
||||
#define ACBG 6
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
|
||||
|
||||
/* PORTE bit definitions */
|
||||
|
||||
#define PE2 2
|
||||
#define PE1 1
|
||||
#define PE0 0
|
||||
|
||||
|
||||
|
||||
/* DDRE bit definitions */
|
||||
|
||||
#define DDE2 2
|
||||
#define DDE1 1
|
||||
#define DDE0 0
|
||||
|
||||
|
||||
|
||||
/* PINE bit definitions */
|
||||
|
||||
#define PINE2 2
|
||||
#define PINE1 1
|
||||
#define PINE0 0
|
||||
|
||||
|
||||
|
||||
/* UCSR1A bit definitions */
|
||||
|
||||
#define RXC1 7
|
||||
#define TXC1 6
|
||||
#define UDRE1 5
|
||||
#define FE1 4
|
||||
#define DOR1 3
|
||||
#define UPE1 2
|
||||
#define U2X1 1
|
||||
#define MPCM1 0
|
||||
|
||||
|
||||
|
||||
/* UCSR1B bit definitions */
|
||||
|
||||
#define RXCIE1 7
|
||||
#define TXCIE1 6
|
||||
#define UDRIE1 5
|
||||
#define RXEN1 4
|
||||
#define TXEN1 3
|
||||
#define UCSZ12 2
|
||||
#define RXB81 1
|
||||
#define TXB81 0
|
||||
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 128
|
||||
#define RAMEND 0x4FF
|
||||
#define XRAMEND 0xFFFF
|
||||
#define E2END 0x1FF
|
||||
#define E2PAGESIZE 4
|
||||
#define FLASHEND 0x3FFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 3
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
||||
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
||||
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
||||
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
||||
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
||||
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
||||
|
||||
/* High Fuse Byte */
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
||||
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
||||
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
||||
#define FUSE_WDTON (unsigned char)~_BV(4)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
||||
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
||||
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
||||
|
||||
/* Extended Fuse Byte */
|
||||
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
|
||||
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
|
||||
#define FUSE_M161C (unsigned char)~_BV(4)
|
||||
#define EFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x94
|
||||
#define SIGNATURE_2 0x04
|
||||
|
||||
|
||||
#endif /* _AVR_IOM162_H_ */
|
||||
639
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom163.h
Normal file
639
arduino-0018-windows/hardware/tools/avr/avr/include/avr/iom163.h
Normal file
|
|
@ -0,0 +1,639 @@
|
|||
/* Copyright (c) 2002, Marek Michalkiewicz
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
* Neither the name of the copyright holders nor the names of
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
/* $Id: iom163.h,v 1.14.2.5 2008/10/17 23:27:47 arcanum Exp $ */
|
||||
|
||||
/* avr/iom163.h - definitions for ATmega163 */
|
||||
|
||||
#ifndef _AVR_IOM163_H_
|
||||
#define _AVR_IOM163_H_ 1
|
||||
|
||||
/* This file should only be included from <avr/io.h>, never directly. */
|
||||
|
||||
#ifndef _AVR_IO_H_
|
||||
# error "Include <avr/io.h> instead of this file."
|
||||
#endif
|
||||
|
||||
#ifndef _AVR_IOXXX_H_
|
||||
# define _AVR_IOXXX_H_ "iom163.h"
|
||||
#else
|
||||
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
||||
#endif
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
#define TWBR _SFR_IO8(0x00)
|
||||
#define TWSR _SFR_IO8(0x01)
|
||||
#define TWAR _SFR_IO8(0x02)
|
||||
#define TWDR _SFR_IO8(0x03)
|
||||
|
||||
/* ADC */
|
||||
#ifndef __ASSEMBLER__
|
||||
#define ADC _SFR_IO16(0x04)
|
||||
#endif
|
||||
#define ADCW _SFR_IO16(0x04)
|
||||
#define ADCL _SFR_IO8(0x04)
|
||||
#define ADCH _SFR_IO8(0x05)
|
||||
#define ADCSR _SFR_IO8(0x06)
|
||||
#define ADMUX _SFR_IO8(0x07)
|
||||
|
||||
/* analog comparator */
|
||||
#define ACSR _SFR_IO8(0x08)
|
||||
|
||||
/* UART */
|
||||
#define UBRR _SFR_IO8(0x09)
|
||||
#define UCSRB _SFR_IO8(0x0A)
|
||||
#define UCSRA _SFR_IO8(0x0B)
|
||||
#define UDR _SFR_IO8(0x0C)
|
||||
|
||||
/* SPI */
|
||||
#define SPCR _SFR_IO8(0x0D)
|
||||
#define SPSR _SFR_IO8(0x0E)
|
||||
#define SPDR _SFR_IO8(0x0F)
|
||||
|
||||
/* Port D */
|
||||
#define PIND _SFR_IO8(0x10)
|
||||
#define DDRD _SFR_IO8(0x11)
|
||||
#define PORTD _SFR_IO8(0x12)
|
||||
|
||||
/* Port C */
|
||||
#define PINC _SFR_IO8(0x13)
|
||||
#define DDRC _SFR_IO8(0x14)
|
||||
#define PORTC _SFR_IO8(0x15)
|
||||
|
||||
/* Port B */
|
||||
#define PINB _SFR_IO8(0x16)
|
||||
#define DDRB _SFR_IO8(0x17)
|
||||
#define PORTB _SFR_IO8(0x18)
|
||||
|
||||
/* Port A */
|
||||
#define PINA _SFR_IO8(0x19)
|
||||
#define DDRA _SFR_IO8(0x1A)
|
||||
#define PORTA _SFR_IO8(0x1B)
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EECR _SFR_IO8(0x1C)
|
||||
|
||||
/* EEPROM Data Register */
|
||||
#define EEDR _SFR_IO8(0x1D)
|
||||
|
||||
/* EEPROM Address Register */
|
||||
#define EEAR _SFR_IO16(0x1E)
|
||||
#define EEARL _SFR_IO8(0x1E)
|
||||
#define EEARH _SFR_IO8(0x1F)
|
||||
|
||||
#define UBRRHI _SFR_IO8(0x20)
|
||||
|
||||
#define WDTCR _SFR_IO8(0x21)
|
||||
|
||||
#define ASSR _SFR_IO8(0x22)
|
||||
|
||||
/* Timer 2 */
|
||||
#define OCR2 _SFR_IO8(0x23)
|
||||
#define TCNT2 _SFR_IO8(0x24)
|
||||
#define TCCR2 _SFR_IO8(0x25)
|
||||
|
||||
/* Timer 1 */
|
||||
#define ICR1 _SFR_IO16(0x26)
|
||||
#define ICR1L _SFR_IO8(0x26)
|
||||
#define ICR1H _SFR_IO8(0x27)
|
||||
#define OCR1B _SFR_IO16(0x28)
|
||||
#define OCR1BL _SFR_IO8(0x28)
|
||||
#define OCR1BH _SFR_IO8(0x29)
|
||||
#define OCR1A _SFR_IO16(0x2A)
|
||||
#define OCR1AL _SFR_IO8(0x2A)
|
||||
#define OCR1AH _SFR_IO8(0x2B)
|
||||
#define TCNT1 _SFR_IO16(0x2C)
|
||||
#define TCNT1L _SFR_IO8(0x2C)
|
||||
#define TCNT1H _SFR_IO8(0x2D)
|
||||
#define TCCR1B _SFR_IO8(0x2E)
|
||||
#define TCCR1A _SFR_IO8(0x2F)
|
||||
|
||||
#define SFIOR _SFR_IO8(0x30)
|
||||
|
||||
#define OSCCAL _SFR_IO8(0x31)
|
||||
|
||||
/* Timer 0 */
|
||||
#define TCNT0 _SFR_IO8(0x32)
|
||||
#define TCCR0 _SFR_IO8(0x33)
|
||||
|
||||
#define MCUSR _SFR_IO8(0x34)
|
||||
#define MCUCR _SFR_IO8(0x35)
|
||||
|
||||
#define TWCR _SFR_IO8(0x36)
|
||||
|
||||
#define SPMCR _SFR_IO8(0x37)
|
||||
|
||||
#define TIFR _SFR_IO8(0x38)
|
||||
#define TIMSK _SFR_IO8(0x39)
|
||||
|
||||
#define GIFR _SFR_IO8(0x3A)
|
||||
#define GIMSK _SFR_IO8(0x3B)
|
||||
|
||||
/* 0x3C reserved */
|
||||
|
||||
/* 0x3D..0x3E SP */
|
||||
|
||||
/* 0x3F SREG */
|
||||
|
||||
/* Interrupt vectors */
|
||||
|
||||
/* External Interrupt 0 */
|
||||
#define INT0_vect _VECTOR(1)
|
||||
#define SIG_INTERRUPT0 _VECTOR(1)
|
||||
|
||||
/* External Interrupt 1 */
|
||||
#define INT1_vect _VECTOR(2)
|
||||
#define SIG_INTERRUPT1 _VECTOR(2)
|
||||
|
||||
/* Timer/Counter2 Compare Match */
|
||||
#define TIMER2_COMP_vect _VECTOR(3)
|
||||
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
|
||||
|
||||
/* Timer/Counter2 Overflow */
|
||||
#define TIMER2_OVF_vect _VECTOR(4)
|
||||
#define SIG_OVERFLOW2 _VECTOR(4)
|
||||
|
||||
/* Timer/Counter1 Capture Event */
|
||||
#define TIMER1_CAPT_vect _VECTOR(5)
|
||||
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
|
||||
|
||||
/* Timer/Counter1 Compare Match A */
|
||||
#define TIMER1_COMPA_vect _VECTOR(6)
|
||||
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
|
||||
|
||||
/* Timer/Counter1 Compare Match B */
|
||||
#define TIMER1_COMPB_vect _VECTOR(7)
|
||||
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
|
||||
|
||||
/* Timer/Counter1 Overflow */
|
||||
#define TIMER1_OVF_vect _VECTOR(8)
|
||||
#define SIG_OVERFLOW1 _VECTOR(8)
|
||||
|
||||
/* Timer/Counter0 Overflow */
|
||||
#define TIMER0_OVF_vect _VECTOR(9)
|
||||
#define SIG_OVERFLOW0 _VECTOR(9)
|
||||
|
||||
/* SPI Serial Transfer Complete */
|
||||
#define SPI_STC_vect _VECTOR(10)
|
||||
#define SIG_SPI _VECTOR(10)
|
||||
|
||||
/* UART, RX Complete */
|
||||
#define UART_RX_vect _VECTOR(11)
|
||||
#define SIG_UART_RECV _VECTOR(11)
|
||||
|
||||
/* UART Data Register Empty */
|
||||
#define UART_UDRE_vect _VECTOR(12)
|
||||
#define SIG_UART_DATA _VECTOR(12)
|
||||
|
||||
/* UART, TX Complete */
|
||||
#define UART_TX_vect _VECTOR(13)
|
||||
#define SIG_UART_TRANS _VECTOR(13)
|
||||
|
||||
/* ADC Conversion Complete */
|
||||
#define ADC_vect _VECTOR(14)
|
||||
#define SIG_ADC _VECTOR(14)
|
||||
|
||||
/* EEPROM Ready */
|
||||
#define EE_RDY_vect _VECTOR(15)
|
||||
#define SIG_EEPROM_READY _VECTOR(15)
|
||||
|
||||
/* Analog Comparator */
|
||||
#define ANA_COMP_vect _VECTOR(16)
|
||||
#define SIG_COMPARATOR _VECTOR(16)
|
||||
|
||||
/* 2-Wire Serial Interface */
|
||||
#define TWI_vect _VECTOR(17)
|
||||
#define SIG_2WIRE_SERIAL _VECTOR(17)
|
||||
|
||||
#define _VECTORS_SIZE 72
|
||||
|
||||
/* Bit numbers */
|
||||
|
||||
/* GIMSK */
|
||||
#define INT1 7
|
||||
#define INT0 6
|
||||
/* bit 5 reserved, undefined */
|
||||
/* bits 4-0 reserved */
|
||||
|
||||
/* GIFR */
|
||||
#define INTF1 7
|
||||
#define INTF0 6
|
||||
/* bits 5-0 reserved */
|
||||
|
||||
/* TIMSK */
|
||||
#define OCIE2 7
|
||||
#define TOIE2 6
|
||||
#define TICIE1 5
|
||||
#define OCIE1A 4
|
||||
#define OCIE1B 3
|
||||
#define TOIE1 2
|
||||
/* bit 1 reserved */
|
||||
#define TOIE0 0
|
||||
|
||||
/* TIFR */
|
||||
#define OCF2 7
|
||||
#define TOV2 6
|
||||
#define ICF1 5
|
||||
#define OCF1A 4
|
||||
#define OCF1B 3
|
||||
#define TOV1 2
|
||||
/* bit 1 reserved, undefined */
|
||||
#define TOV0 0
|
||||
|
||||
/* SPMCR */
|
||||
/* bit 7 reserved */
|
||||
#define ASB 6
|
||||
/* bit 5 reserved */
|
||||
#define ASRE 4
|
||||
#define BLBSET 3
|
||||
#define PGWRT 2
|
||||
#define PGERS 1
|
||||
#define SPMEN 0
|
||||
|
||||
/* TWCR */
|
||||
#define TWINT 7
|
||||
#define TWEA 6
|
||||
#define TWSTA 5
|
||||
#define TWSTO 4
|
||||
#define TWWC 3
|
||||
#define TWEN 2
|
||||
/* bit 1 reserved */
|
||||
#define TWIE 0
|
||||
|
||||
/* TWAR */
|
||||
#define TWGCE 0
|
||||
|
||||
/* TWSR */
|
||||
#define TWS7 7
|
||||
#define TWS6 6
|
||||
#define TWS5 5
|
||||
#define TWS4 4
|
||||
#define TWS3 3
|
||||
/* bits 2-0 reserved */
|
||||
|
||||
/* MCUCR */
|
||||
/* bit 7 reserved */
|
||||
#define SE 6
|
||||
#define SM1 5
|
||||
#define SM0 4
|
||||
#define ISC11 3
|
||||
#define ISC10 2
|
||||
#define ISC01 1
|
||||
#define ISC00 0
|
||||
|
||||
/* MCUSR */
|
||||
/* bits 7-4 reserved */
|
||||
#define WDRF 3
|
||||
#define BORF 2
|
||||
#define EXTRF 1
|
||||
#define PORF 0
|
||||
|
||||
/* SFIOR */
|
||||
/* bits 7-4 reserved */
|
||||
#define ACME 3
|
||||
#define PUD 2
|
||||
#define PSR2 1
|
||||
#define PSR10 0
|
||||
|
||||
/* TCCR0 */
|
||||
/* bits 7-3 reserved */
|
||||
#define CS02 2
|
||||
#define CS01 1
|
||||
#define CS00 0
|
||||
|
||||
/* TCCR2 */
|
||||
#define FOC2 7
|
||||
#define PWM2 6
|
||||
#define COM21 5
|
||||
#define COM20 4
|
||||
#define CTC2 3
|
||||
#define CS22 2
|
||||
#define CS21 1
|
||||
#define CS20 0
|
||||
|
||||
/* ASSR */
|
||||
/* bits 7-4 reserved */
|
||||
#define AS2 3
|
||||
#define TCN2UB 2
|
||||
#define OCR2UB 1
|
||||
#define TCR2UB 0
|
||||
|
||||
/* TCCR1A */
|
||||
#define COM1A1 7
|
||||
#define COM1A0 6
|
||||
#define COM1B1 5
|
||||
#define COM1B0 4
|
||||
#define FOC1A 3
|
||||
#define FOC1B 2
|
||||
#define PWM11 1
|
||||
#define PWM10 0
|
||||
|
||||
/* TCCR1B */
|
||||
#define ICNC1 7
|
||||
#define ICES1 6
|
||||
/* bits 5-4 reserved */
|
||||
#define CTC1 3
|
||||
#define CS12 2
|
||||
#define CS11 1
|
||||
#define CS10 0
|
||||
|
||||
/* WDTCR */
|
||||
/* bits 7-5 reserved */
|
||||
#define WDTOE 4
|
||||
#define WDE 3
|
||||
#define WDP2 2
|
||||
#define WDP1 1
|
||||
#define WDP0 0
|
||||
|
||||
/* PA7-PA0 = ADC7-ADC0 */
|
||||
/* PORTA */
|
||||
#define PA7 7
|
||||
#define PA6 6
|
||||
#define PA5 5
|
||||
#define PA4 4
|
||||
#define PA3 3
|
||||
#define PA2 2
|
||||
#define PA1 1
|
||||
#define PA0 0
|
||||
|
||||
/* DDRA */
|
||||
#define DDA7 7
|
||||
#define DDA6 6
|
||||
#define DDA5 5
|
||||
#define DDA4 4
|
||||
#define DDA3 3
|
||||
#define DDA2 2
|
||||
#define DDA1 1
|
||||
#define DDA0 0
|
||||
|
||||
/* PINA */
|
||||
#define PINA7 7
|
||||
#define PINA6 6
|
||||
#define PINA5 5
|
||||
#define PINA4 4
|
||||
#define PINA3 3
|
||||
#define PINA2 2
|
||||
#define PINA1 1
|
||||
#define PINA0 0
|
||||
|
||||
/*
|
||||
PB7 = SCK
|
||||
PB6 = MISO
|
||||
PB5 = MOSI
|
||||
PB4 = SS#
|
||||
PB3 = AIN1
|
||||
PB2 = AIN0
|
||||
PB1 = T1
|
||||
PB0 = T0
|
||||
*/
|
||||
|
||||
/* PORTB */
|
||||
#define PB7 7
|
||||
#define PB6 6
|
||||
#define PB5 5
|
||||
#define PB4 4
|
||||
#define PB3 3
|
||||
#define PB2 2
|
||||
#define PB1 1
|
||||
#define PB0 0
|
||||
|
||||
/* DDRB */
|
||||
#define DDB7 7
|
||||
#define DDB6 6
|
||||
#define DDB5 5
|
||||
#define DDB4 4
|
||||
#define DDB3 3
|
||||
#define DDB2 2
|
||||
#define DDB1 1
|
||||
#define DDB0 0
|
||||
|
||||
/* PINB */
|
||||
#define PINB7 7
|
||||
#define PINB6 6
|
||||
#define PINB5 5
|
||||
#define PINB4 4
|
||||
#define PINB3 3
|
||||
#define PINB2 2
|
||||
#define PINB1 1
|
||||
#define PINB0 0
|
||||
|
||||
/*
|
||||
PC7 = TOSC2
|
||||
PC6 = TOSC1
|
||||
PC1 = SDA
|
||||
PC0 = SCL
|
||||
*/
|
||||
/* PORTC */
|
||||
#define PC7 7
|
||||
#define PC6 6
|
||||
#define PC5 5
|
||||
#define PC4 4
|
||||
#define PC3 3
|
||||
#define PC2 2
|
||||
#define PC1 1
|
||||
#define PC0 0
|
||||
|
||||
/* DDRC */
|
||||
#define DDC7 7
|
||||
#define DDC6 6
|
||||
#define DDC5 5
|
||||
#define DDC4 4
|
||||
#define DDC3 3
|
||||
#define DDC2 2
|
||||
#define DDC1 1
|
||||
#define DDC0 0
|
||||
|
||||
/* PINC */
|
||||
#define PINC7 7
|
||||
#define PINC6 6
|
||||
#define PINC5 5
|
||||
#define PINC4 4
|
||||
#define PINC3 3
|
||||
#define PINC2 2
|
||||
#define PINC1 1
|
||||
#define PINC0 0
|
||||
|
||||
/*
|
||||
PD7 = OC2
|
||||
PD6 = ICP
|
||||
PD5 = OC1A
|
||||
PD4 = OC1B
|
||||
PD3 = INT1
|
||||
PD2 = INT0
|
||||
PD1 = TXD
|
||||
PD0 = RXD
|
||||
*/
|
||||
|
||||
/* PORTD */
|
||||
#define PD7 7
|
||||
#define PD6 6
|
||||
#define PD5 5
|
||||
#define PD4 4
|
||||
#define PD3 3
|
||||
#define PD2 2
|
||||
#define PD1 1
|
||||
#define PD0 0
|
||||
|
||||
/* DDRD */
|
||||
#define DDD7 7
|
||||
#define DDD6 6
|
||||
#define DDD5 5
|
||||
#define DDD4 4
|
||||
#define DDD3 3
|
||||
#define DDD2 2
|
||||
#define DDD1 1
|
||||
#define DDD0 0
|
||||
|
||||
/* PIND */
|
||||
#define PIND7 7
|
||||
#define PIND6 6
|
||||
#define PIND5 5
|
||||
#define PIND4 4
|
||||
#define PIND3 3
|
||||
#define PIND2 2
|
||||
#define PIND1 1
|
||||
#define PIND0 0
|
||||
|
||||
/* SPSR */
|
||||
#define SPIF 7
|
||||
#define WCOL 6
|
||||
/* bits 5-1 reserved */
|
||||
#define SPI2X 0
|
||||
|
||||
/* SPCR */
|
||||
#define SPIE 7
|
||||
#define SPE 6
|
||||
#define DORD 5
|
||||
#define MSTR 4
|
||||
#define CPOL 3
|
||||
#define CPHA 2
|
||||
#define SPR1 1
|
||||
#define SPR0 0
|
||||
|
||||
/* UCSRA */
|
||||
#define RXC 7
|
||||
#define TXC 6
|
||||
#define UDRE 5
|
||||
#define FE 4
|
||||
#define DOR 3
|
||||
/* bit 2 reserved */
|
||||
#define U2X 1
|
||||
#define MPCM 0
|
||||
|
||||
/* UCSRB */
|
||||
#define RXCIE 7
|
||||
#define TXCIE 6
|
||||
#define UDRIE 5
|
||||
#define RXEN 4
|
||||
#define TXEN 3
|
||||
#define CHR9 2
|
||||
#define RXB8 1
|
||||
#define TXB8 0
|
||||
|
||||
/* ACSR */
|
||||
#define ACD 7
|
||||
#define AINBG 6
|
||||
#define ACO 5
|
||||
#define ACI 4
|
||||
#define ACIE 3
|
||||
#define ACIC 2
|
||||
#define ACIS1 1
|
||||
#define ACIS0 0
|
||||
|
||||
/* ADCSR */
|
||||
#define ADEN 7
|
||||
#define ADSC 6
|
||||
#define ADFR 5
|
||||
#define ADIF 4
|
||||
#define ADIE 3
|
||||
#define ADPS2 2
|
||||
#define ADPS1 1
|
||||
#define ADPS0 0
|
||||
|
||||
/* ADMUX */
|
||||
#define REFS1 7
|
||||
#define REFS0 6
|
||||
#define ADLAR 5
|
||||
#define MUX4 4
|
||||
#define MUX3 3
|
||||
#define MUX2 2
|
||||
#define MUX1 1
|
||||
#define MUX0 0
|
||||
|
||||
/* EEPROM Control Register */
|
||||
#define EERIE 3
|
||||
#define EEMWE 2
|
||||
#define EEWE 1
|
||||
#define EERE 0
|
||||
|
||||
/* Constants */
|
||||
#define SPM_PAGESIZE 128
|
||||
#define RAMEND 0x45F
|
||||
#define XRAMEND 0x45F
|
||||
#define E2END 0x1FF
|
||||
#define E2PAGESIZE 0
|
||||
#define FLASHEND 0x3FFF
|
||||
|
||||
|
||||
/* Fuses */
|
||||
|
||||
#define FUSE_MEMORY_SIZE 2
|
||||
|
||||
/* Low Fuse Byte */
|
||||
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
||||
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
||||
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
||||
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
||||
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
||||
#define FUSE_BODEN (unsigned char)~_BV(6)
|
||||
#define FUSE_BODLEVEL (unsigned char)~_BV(7)
|
||||
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN)
|
||||
|
||||
/* High Fuse Byte */
|
||||
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
||||
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
||||
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
||||
#define HFUSE_DEFAULT (0xFF)
|
||||
|
||||
|
||||
/* Lock Bits */
|
||||
#define __LOCK_BITS_EXIST
|
||||
#define __BOOT_LOCK_BITS_0_EXIST
|
||||
#define __BOOT_LOCK_BITS_1_EXIST
|
||||
|
||||
|
||||
/* Signature */
|
||||
#define SIGNATURE_0 0x1E
|
||||
#define SIGNATURE_1 0x94
|
||||
#define SIGNATURE_2 0x02
|
||||
|
||||
|
||||
#endif /* _AVR_IOM163_H_ */
|
||||
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