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<h3 class="section">7.2 <code>.ABORT</code> (COFF)</h3>
<p><a name="index-_0040code_007bABORT_007d-directive-274"></a>When producing COFF output, <span class="command">as</span> accepts this directive as a
synonym for <span class="samp">.abort</span>.
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<h4 class="subsection">9.2.4 ARC Machine Directives</h4>
<p><a name="index-machine-directives_002c-ARC-548"></a><a name="index-ARC-machine-directives-549"></a>The ARC version of <code>as</code> supports the following additional
machine directives:
<a name="index-_0040code_007b2byte_007d-directive_002c-ARC-550"></a>
<dl><dt><code>.2byte </code><var>expressions</var><dd>*TODO*
<p><a name="index-_0040code_007b3byte_007d-directive_002c-ARC-551"></a><br><dt><code>.3byte </code><var>expressions</var><dd>*TODO*
<p><a name="index-_0040code_007b4byte_007d-directive_002c-ARC-552"></a><br><dt><code>.4byte </code><var>expressions</var><dd>*TODO*
<p><a name="index-_0040code_007bextAuxRegister_007d-directive_002c-ARC-553"></a><br><dt><code>.extAuxRegister </code><var>name</var><code>,</code><var>address</var><code>,</code><var>mode</var><dd>The ARCtangent A4 has extensible auxiliary register space. The
auxiliary registers can be defined in the assembler source code by
using this directive. The first parameter is the <var>name</var> of the
new auxiallry register. The second parameter is the <var>address</var> of
the register in the auxiliary register memory map for the variant of
the ARC. The third parameter specifies the <var>mode</var> in which the
register can be operated is and it can be one of:
<dl>
<dt><code>r (readonly)</code><br><dt><code>w (write only)</code><br><dt><code>r|w (read or write)</code><dd></dl>
<p>For example:
<pre class="smallexample"> .extAuxRegister mulhi,0x12,w
</pre>
<p>This specifies an extension auxiliary register called <em>mulhi</em>
which is at address 0x12 in the memory space and which is only
writable.
<p><a name="index-_0040code_007bextCondCode_007d-directive_002c-ARC-554"></a><br><dt><code>.extCondCode </code><var>suffix</var><code>,</code><var>value</var><dd>The condition codes on the ARCtangent A4 are extensible and can be
specified by means of this assembler directive. They are specified
by the suffix and the value for the condition code. They can be used to
specify extra condition codes with any values. For example:
<pre class="smallexample"> .extCondCode is_busy,0x14
add.is_busy r1,r2,r3
bis_busy _main
</pre>
<p><a name="index-_0040code_007bextCoreRegister_007d-directive_002c-ARC-555"></a><br><dt><code>.extCoreRegister </code><var>name</var><code>,</code><var>regnum</var><code>,</code><var>mode</var><code>,</code><var>shortcut</var><dd>Specifies an extension core register <var>name</var> for the application.
This allows a register <var>name</var> with a valid <var>regnum</var> between 0
and 60, with the following as valid values for <var>mode</var>
<dl>
<dt><em>r</em><span class="samp"> (readonly)</span><br><dt><em>w</em><span class="samp"> (write only)</span><br><dt><em>r|w</em><span class="samp"> (read or write)</span><dd></dl>
<p>The other parameter gives a description of the register having a
<var>shortcut</var> in the pipeline. The valid values are:
<dl>
<dt><code>can_shortcut</code><br><dt><code>cannot_shortcut</code><dd></dl>
<p>For example:
<pre class="smallexample"> .extCoreRegister mlo,57,r,can_shortcut
</pre>
<p>This defines an extension core register mlo with the value 57 which
can shortcut the pipeline.
<p><a name="index-_0040code_007bextInstruction_007d-directive_002c-ARC-556"></a><br><dt><code>.extInstruction </code><var>name</var><code>,</code><var>opcode</var><code>,</code><var>subopcode</var><code>,</code><var>suffixclass</var><code>,</code><var>syntaxclass</var><dd>The ARCtangent A4 allows the user to specify extension instructions.
The extension instructions are not macros. The assembler creates
encodings for use of these instructions according to the specification
by the user. The parameters are:
<dl>
<dt>&bull;<var>name</var><dd>Name of the extension instruction
<br><dt>&bull;<var>opcode</var><dd>Opcode to be used. (Bits 27:31 in the encoding). Valid values
0x10-0x1f or 0x03
<br><dt>&bull;<var>subopcode</var><dd>Subopcode to be used. Valid values are from 0x09-0x3f. However the
correct value also depends on <var>syntaxclass</var>
<br><dt>&bull;<var>suffixclass</var><dd>Determines the kinds of suffixes to be allowed. Valid values are
<code>SUFFIX_NONE</code>, <code>SUFFIX_COND</code>,
<code>SUFFIX_FLAG</code> which indicates the absence or presence of
conditional suffixes and flag setting by the extension instruction.
It is also possible to specify that an instruction sets the flags and
is conditional by using <code>SUFFIX_CODE</code> | <code>SUFFIX_FLAG</code>.
<br><dt>&bull;<var>syntaxclass</var><dd>Determines the syntax class for the instruction. It can have the
following values:
<dl>
<dt><code>SYNTAX_2OP:</code><dd>2 Operand Instruction
<br><dt><code>SYNTAX_3OP:</code><dd>3 Operand Instruction
</dl>
<p>In addition there could be modifiers for the syntax class as described
below:
<ul>
Syntax Class Modifiers are:
<li><code>OP1_MUST_BE_IMM</code>:
Modifies syntax class SYNTAX_3OP, specifying that the first operand
of a three-operand instruction must be an immediate (i.e., the result
is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
SYNTAX_3OP as given in the example below. This could usually be used
to set the flags using specific instructions and not retain results.
<li><code>OP1_IMM_IMPLIED</code>:
Modifies syntax class SYNTAX_20P, it specifies that there is an
implied immediate destination operand which does not appear in the
syntax. For example, if the source code contains an instruction like:
<pre class="smallexample"> inst r1,r2
</pre>
<p>it really means that the first argument is an implied immediate (that
is, the result is discarded). This is the same as though the source
code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
with SYNTAX_20P.
</ul>
</dl>
<p>For example, defining 64-bit multiplier with immediate operands:
<pre class="smallexample"> .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
SYNTAX_3OP|OP1_MUST_BE_IMM
</pre>
<p>The above specifies an extension instruction called mp64 which has 3 operands,
sets the flags, can be used with a condition code, for which the
first operand is an immediate. (Equivalent to discarding the result
of the operation).
<pre class="smallexample"> .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
</pre>
<p>This describes a 2 operand instruction with an implicit first
immediate operand. The result of this operation would be discarded.
<p><a name="index-_0040code_007bhalf_007d-directive_002c-ARC-557"></a><br><dt><code>.half </code><var>expressions</var><dd>*TODO*
<p><a name="index-_0040code_007blong_007d-directive_002c-ARC-558"></a><br><dt><code>.long </code><var>expressions</var><dd>*TODO*
<p><a name="index-_0040code_007boption_007d-directive_002c-ARC-559"></a><br><dt><code>.option </code><var>arc|arc5|arc6|arc7|arc8</var><dd>The <code>.option</code> directive must be followed by the desired core
version. Again <code>arc</code> is an alias for
<code>arc6</code>.
<p>Note: the <code>.option</code> directive overrides the command line option
<code>-marc</code>; a warning is emitted when the version is not consistent
between the two - even for the implicit default core version
(arc6).
<p><a name="index-_0040code_007bshort_007d-directive_002c-ARC-560"></a><br><dt><code>.short </code><var>expressions</var><dd>*TODO*
<p><a name="index-_0040code_007bword_007d-directive_002c-ARC-561"></a><br><dt><code>.word </code><var>expressions</var><dd>*TODO*
</dl>
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<h4 class="subsection">9.2.3 Floating Point</h4>
<p><a name="index-floating-point_002c-ARC-_0028_0040sc_007bieee_007d_0029-546"></a><a name="index-ARC-floating-point-_0028_0040sc_007bieee_007d_0029-547"></a>The ARC core does not currently have hardware floating point
support. Software floating point support is provided by <code>GCC</code>
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<h4 class="subsection">9.2.5 Opcodes</h4>
<p><a name="index-ARC-opcodes-562"></a><a name="index-opcodes-for-ARC-563"></a>
For information on the ARC instruction set, see <cite>ARC Programmers
Reference Manual</cite>, ARC International (www.arc.com)
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<h4 class="subsection">9.2.1 Options</h4>
<p><a name="index-ARC-options-_0028none_0029-533"></a><a name="index-options-for-ARC-_0028none_0029-534"></a>
<a name="index-_0040code_007b_002dmarc_005b5_007c6_007c7_007c8_005d_007d-command-line-option_002c-ARC-535"></a>
<dl><dt><code>-marc[5|6|7|8]</code><dd>This option selects the core processor variant. Using
<code>-marc</code> is the same as <code>-marc6</code>, which
is also the default.
<a name="index-_0040code_007barc5_007d-arc5_002c-ARC-536"></a>
<dl><dt><code>arc5</code><dd>Base instruction set.
<p><a name="index-_0040code_007barc6_007d-arc6_002c-ARC-537"></a><br><dt><code>arc6</code><dd>Jump-and-link (jl) instruction. No requirement of an instruction between
setting flags and conditional jump. For example:
<pre class="smallexample"> mov.f r0,r1
beq foo
</pre>
<p><a name="index-_0040code_007barc7_007d-arc7_002c-ARC-538"></a><br><dt><code>arc7</code><dd>Break (brk) and sleep (sleep) instructions.
<p><a name="index-_0040code_007barc8_007d-arc8_002c-ARC-539"></a><br><dt><code>arc8</code><dd>Software interrupt (swi) instruction.
</dl>
<p>Note: the <code>.option</code> directive can to be used to select a core
variant from within assembly code.
<p><a name="index-_0040code_007b_002dEB_007d-command-line-option_002c-ARC-540"></a><br><dt><code>-EB</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
<p><a name="index-_0040code_007b_002dEL_007d-command-line-option_002c-ARC-541"></a><br><dt><code>-EL</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor - this is the
default.
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<h4 class="subsection">9.2.2 Syntax</h4>
<ul class="menu">
<li><a accesskey="1" href="ARC_002dChars.html#ARC_002dChars">ARC-Chars</a>: Special Characters
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<h5 class="subsubsection">9.2.2.1 Special Characters</h5>
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<h5 class="subsubsection">9.2.2.2 Register Names</h5>
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<h4 class="subsection">9.3.4 ARM Machine Directives</h4>
<p><a name="index-machine-directives_002c-ARM-600"></a><a name="index-ARM-machine-directives-601"></a>
<a name="index-_0040code_007balign_007d-directive_002c-ARM-602"></a>
<dl><dt><code>.align </code><var>expression</var><code> [, </code><var>expression</var><code>]</code><dd>This is the generic <var>.align</var> directive. For the ARM however if the
first argument is zero (ie no alignment is needed) the assembler will
behave as if the argument had been 2 (ie pad to the next four byte
boundary). This is for compatibility with ARM's own assembler.
<p><a name="index-_0040code_007breq_007d-directive_002c-ARM-603"></a><br><dt><var>name</var><code> .req </code><var>register name</var><dd>This creates an alias for <var>register name</var> called <var>name</var>. For
example:
<pre class="smallexample"> foo .req r0
</pre>
<p><a name="index-_0040code_007bunreq_007d-directive_002c-ARM-604"></a><br><dt><code>.unreq </code><var>alias-name</var><dd>This undefines a register alias which was previously defined using the
<code>req</code>, <code>dn</code> or <code>qn</code> directives. For example:
<pre class="smallexample"> foo .req r0
.unreq foo
</pre>
<p>An error occurs if the name is undefined. Note - this pseudo op can
be used to delete builtin in register name aliases (eg 'r0'). This
should only be done if it is really necessary.
<p><a name="index-_0040code_007bdn_007d-and-_0040code_007bqn_007d-directives_002c-ARM-605"></a><br><dt><var>name</var><code> .dn </code><var>register name</var><code> [</code><var>.type</var><code>] [[</code><var>index</var><code>]]</code><br><dt><var>name</var><code> .qn </code><var>register name</var><code> [</code><var>.type</var><code>] [[</code><var>index</var><code>]]</code><dd>
The <code>dn</code> and <code>qn</code> directives are used to create typed
and/or indexed register aliases for use in Advanced SIMD Extension
(Neon) instructions. The former should be used to create aliases
of double-precision registers, and the latter to create aliases of
quad-precision registers.
<p>If these directives are used to create typed aliases, those aliases can
be used in Neon instructions instead of writing types after the mnemonic
or after each operand. For example:
<pre class="smallexample"> x .dn d2.f32
y .dn d3.f32
z .dn d4.f32[1]
vmul x,y,z
</pre>
<p>This is equivalent to writing the following:
<pre class="smallexample"> vmul.f32 d2,d3,d4[1]
</pre>
<p>Aliases created using <code>dn</code> or <code>qn</code> can be destroyed using
<code>unreq</code>.
<p><a name="index-_0040code_007bcode_007d-directive_002c-ARM-606"></a><br><dt><code>.code [16|32]</code><dd>This directive selects the instruction set being generated. The value 16
selects Thumb, with the value 32 selecting ARM.
<p><a name="index-_0040code_007bthumb_007d-directive_002c-ARM-607"></a><br><dt><code>.thumb</code><dd>This performs the same action as <var>.code 16</var>.
<p><a name="index-_0040code_007barm_007d-directive_002c-ARM-608"></a><br><dt><code>.arm</code><dd>This performs the same action as <var>.code 32</var>.
<p><a name="index-_0040code_007bforce_005fthumb_007d-directive_002c-ARM-609"></a><br><dt><code>.force_thumb</code><dd>This directive forces the selection of Thumb instructions, even if the
target processor does not support those instructions
<p><a name="index-_0040code_007bthumb_005ffunc_007d-directive_002c-ARM-610"></a><br><dt><code>.thumb_func</code><dd>This directive specifies that the following symbol is the name of a
Thumb encoded function. This information is necessary in order to allow
the assembler and linker to generate correct code for interworking
between Arm and Thumb instructions and should be used even if
interworking is not going to be performed. The presence of this
directive also implies <code>.thumb</code>
<p>This directive is not neccessary when generating EABI objects. On these
targets the encoding is implicit when generating Thumb code.
<p><a name="index-_0040code_007bthumb_005fset_007d-directive_002c-ARM-611"></a><br><dt><code>.thumb_set</code><dd>This performs the equivalent of a <code>.set</code> directive in that it
creates a symbol which is an alias for another symbol (possibly not yet
defined). This directive also has the added property in that it marks
the aliased symbol as being a thumb function entry point, in the same
way that the <code>.thumb_func</code> directive does.
<p><a name="index-_0040code_007b_002eltorg_007d-directive_002c-ARM-612"></a><br><dt><code>.ltorg</code><dd>This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
<code>GAS</code> maintains a separate literal pool for each section and each
sub-section. The <code>.ltorg</code> directive will only affect the literal
pool of the current section and sub-section. At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
<p>Note - older versions of <code>GAS</code> would dump the current literal
pool any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
<p><a name="index-_0040code_007b_002epool_007d-directive_002c-ARM-613"></a><br><dt><code>.pool</code><dd>This is a synonym for .ltorg.
<p><a name="arm_005ffnstart"></a>
<a name="index-_0040code_007b_002efnstart_007d-directive_002c-ARM-614"></a><br><dt><code>.fnstart</code><dd>Marks the start of a function with an unwind table entry.
<p><a name="arm_005ffnend"></a>
<a name="index-_0040code_007b_002efnend_007d-directive_002c-ARM-615"></a><br><dt><code>.fnend</code><dd>Marks the end of a function with an unwind table entry. The unwind index
table entry is created when this directive is processed.
<p>If no personality routine has been specified then standard personality
routine 0 or 1 will be used, depending on the number of unwind opcodes
required.
<p><a name="index-_0040code_007b_002ecantunwind_007d-directive_002c-ARM-616"></a><br><dt><code>.cantunwind</code><dd>Prevents unwinding through the current function. No personality routine
or exception table data is required or permitted.
<p><a name="index-_0040code_007b_002epersonality_007d-directive_002c-ARM-617"></a><br><dt><code>.personality </code><var>name</var><dd>Sets the personality routine for the current function to <var>name</var>.
<p><a name="index-_0040code_007b_002epersonalityindex_007d-directive_002c-ARM-618"></a><br><dt><code>.personalityindex </code><var>index</var><dd>Sets the personality routine for the current function to the EABI standard
routine number <var>index</var>
<p><a name="index-_0040code_007b_002ehandlerdata_007d-directive_002c-ARM-619"></a><br><dt><code>.handlerdata</code><dd>Marks the end of the current function, and the start of the exception table
entry for that function. Anything between this directive and the
<code>.fnend</code> directive will be added to the exception table entry.
<p>Must be preceded by a <code>.personality</code> or <code>.personalityindex</code>
directive.
<p><a name="arm_005fsave"></a>
<a name="index-_0040code_007b_002esave_007d-directive_002c-ARM-620"></a><br><dt><code>.save </code><var>reglist</var><dd>Generate unwinder annotations to restore the registers in <var>reglist</var>.
The format of <var>reglist</var> is the same as the corresponding store-multiple
instruction.
<pre class="smallexample"> <br><em>core registers</em><br>
.save {r4, r5, r6, lr}
stmfd sp!, {r4, r5, r6, lr}
<br><em>FPA registers</em><br>
.save f4, 2
sfmfd f4, 2, [sp]!
<br><em>VFP registers</em><br>
.save {d8, d9, d10}
fstmdx sp!, {d8, d9, d10}
<br><em>iWMMXt registers</em><br>
.save {wr10, wr11}
wstrd wr11, [sp, #-8]!
wstrd wr10, [sp, #-8]!
or
.save wr11
wstrd wr11, [sp, #-8]!
.save wr10
wstrd wr10, [sp, #-8]!
</pre>
<p><a name="index-_0040code_007b_002evsave_007d-directive_002c-ARM-621"></a><br><dt><code>.vsave </code><var>vfp-reglist</var><dd>Generate unwinder annotations to restore the VFP registers in <var>vfp-reglist</var>
using FLDMD. Also works for VFPv3 registers
that are to be restored using VLDM.
The format of <var>vfp-reglist</var> is the same as the corresponding store-multiple
instruction.
<pre class="smallexample"> <br><em>VFP registers</em><br>
.vsave {d8, d9, d10}
fstmdd sp!, {d8, d9, d10}
<br><em>VFPv3 registers</em><br>
.vsave {d15, d16, d17}
vstm sp!, {d15, d16, d17}
</pre>
<p>Since FLDMX and FSTMX are now deprecated, this directive should be
used in favour of <code>.save</code> for saving VFP registers for ARMv6 and above.
<p><a name="arm_005fpad"></a>
<a name="index-_0040code_007b_002epad_007d-directive_002c-ARM-622"></a><br><dt><code>.pad #</code><var>count</var><dd>Generate unwinder annotations for a stack adjustment of <var>count</var> bytes.
A positive value indicates the function prologue allocated stack space by
decrementing the stack pointer.
<p><a name="arm_005fmovsp"></a>
<a name="index-_0040code_007b_002emovsp_007d-directive_002c-ARM-623"></a><br><dt><code>.movsp </code><var>reg</var><code> [, #</code><var>offset</var><code>]</code><dd>Tell the unwinder that <var>reg</var> contains an offset from the current
stack pointer. If <var>offset</var> is not specified then it is assumed to be
zero.
<p><a name="arm_005fsetfp"></a>
<a name="index-_0040code_007b_002esetfp_007d-directive_002c-ARM-624"></a><br><dt><code>.setfp </code><var>fpreg</var><code>, </code><var>spreg</var><code> [, #</code><var>offset</var><code>]</code><dd>Make all unwinder annotations relaive to a frame pointer. Without this
the unwinder will use offsets from the stack pointer.
<p>The syntax of this directive is the same as the <code>sub</code> or <code>mov</code>
instruction used to set the frame pointer. <var>spreg</var> must be either
<code>sp</code> or mentioned in a previous <code>.movsp</code> directive.
<pre class="smallexample"> .movsp ip
mov ip, sp
...
.setfp fp, ip, #4
sub fp, ip, #4
</pre>
<p><a name="index-_0040code_007b_002eunwind_005fraw_007d-directive_002c-ARM-625"></a><br><dt><code>.raw </code><var>offset</var><code>, </code><var>byte1</var><code>, ...</code><dd>Insert one of more arbitary unwind opcode bytes, which are known to adjust
the stack pointer by <var>offset</var> bytes.
<p>For example <code>.unwind_raw 4, 0xb1, 0x01</code> is equivalent to
<code>.save {r0}</code>
<p><a name="index-_0040code_007b_002ecpu_007d-directive_002c-ARM-626"></a><br><dt><code>.cpu </code><var>name</var><dd>Select the target processor. Valid values for <var>name</var> are the same as
for the <span class="option">-mcpu</span> commandline option.
<p><a name="index-_0040code_007b_002earch_007d-directive_002c-ARM-627"></a><br><dt><code>.arch </code><var>name</var><dd>Select the target architecture. Valid values for <var>name</var> are the same as
for the <span class="option">-march</span> commandline option.
<p><a name="index-_0040code_007b_002eobject_005farch_007d-directive_002c-ARM-628"></a><br><dt><code>.object_arch </code><var>name</var><dd>Override the architecture recorded in the EABI object attribute section.
Valid values for <var>name</var> are the same as for the <code>.arch</code> directive.
Typically this is useful when code uses runtime detection of CPU features.
<p><a name="index-_0040code_007b_002efpu_007d-directive_002c-ARM-629"></a><br><dt><code>.fpu </code><var>name</var><dd>Select the floating point unit to assemble for. Valid values for <var>name</var>
are the same as for the <span class="option">-mfpu</span> commandline option.
<p><a name="index-_0040code_007b_002eeabi_005fattribute_007d-directive_002c-ARM-630"></a><br><dt><code>.eabi_attribute </code><var>tag</var><code>, </code><var>value</var><dd>Set the EABI object attribute number <var>tag</var> to <var>value</var>. The value
is either a <code>number</code>, <code>"string"</code>, or <code>number, "string"</code>
depending on the tag.
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<h4 class="subsection">9.3.3 Floating Point</h4>
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<h4 class="subsection">9.3.6 Mapping Symbols</h4>
<p>The ARM ELF specification requires that special symbols be inserted
into object files to mark certain features:
<a name="index-_0040code_007b_0024a_007d-637"></a>
<dl><dt><code>$a</code><dd>At the start of a region of code containing ARM instructions.
<p><a name="index-_0040code_007b_0024t_007d-638"></a><br><dt><code>$t</code><dd>At the start of a region of code containing THUMB instructions.
<p><a name="index-_0040code_007b_0024d_007d-639"></a><br><dt><code>$d</code><dd>At the start of a region of data.
</dl>
<p>The assembler will automatically insert these symbols for you - there
is no need to code them yourself. Support for tagging symbols ($b,
$f, $p and $m) which is also mentioned in the current ARM ELF
specification is not implemented. This is because they have been
dropped from the new EABI and so tools cannot rely upon their
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Previous:&nbsp;<a rel="previous" accesskey="p" href="ARM-Directives.html#ARM-Directives">ARM Directives</a>,
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<h4 class="subsection">9.3.5 Opcodes</h4>
<p><a name="index-ARM-opcodes-631"></a><a name="index-opcodes-for-ARM-632"></a><code>as</code> implements all the standard ARM opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
<a name="index-_0040code_007bNOP_007d-pseudo-op_002c-ARM-633"></a>
<dl><dt><code>NOP</code><dd>
<pre class="smallexample"> nop
</pre>
<p>This pseudo op will always evaluate to a legal ARM instruction that does
nothing. Currently it will evaluate to MOV r0, r0.
<p><a name="index-_0040code_007bLDR-reg_002c_003d_003clabel_003e_007d-pseudo-op_002c-ARM-634"></a><br><dt><code>LDR</code><dd>
<pre class="smallexample"> ldr &lt;register&gt; , = &lt;expression&gt;
</pre>
<p>If expression evaluates to a numeric constant then a MOV or MVN
instruction will be used in place of the LDR instruction, if the
constant can be generated by either of these instructions. Otherwise
the constant will be placed into the nearest literal pool (if it not
already there) and a PC relative LDR instruction will be generated.
<p><a name="index-_0040code_007bADR-reg_002c_003clabel_003e_007d-pseudo-op_002c-ARM-635"></a><br><dt><code>ADR</code><dd>
<pre class="smallexample"> adr &lt;register&gt; &lt;label&gt;
</pre>
<p>This instruction will load the address of <var>label</var> into the indicated
register. The instruction will evaluate to a PC relative ADD or SUB
instruction depending upon where the label is located. If the label is
out of range, or if it is not defined in the same file (and section) as
the ADR instruction, then an error will be generated. This instruction
will not make use of the literal pool.
<p><a name="index-_0040code_007bADRL-reg_002c_003clabel_003e_007d-pseudo-op_002c-ARM-636"></a><br><dt><code>ADRL</code><dd>
<pre class="smallexample"> adrl &lt;register&gt; &lt;label&gt;
</pre>
<p>This instruction will load the address of <var>label</var> into the indicated
register. The instruction will evaluate to one or two PC relative ADD
or SUB instructions depending upon where the label is located. If a
second instruction is not needed a NOP instruction will be generated in
its place, so that this instruction is always 8 bytes long.
<p>If the label is out of range, or if it is not defined in the same file
(and section) as the ADRL instruction, then an error will be generated.
This instruction will not make use of the literal pool.
</dl>
<p>For information on the ARM or Thumb instruction sets, see <cite>ARM
Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines
Ltd.
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<h4 class="subsection">9.3.1 Options</h4>
<p><a name="index-ARM-options-_0028none_0029-566"></a><a name="index-options-for-ARM-_0028none_0029-567"></a>
<a name="index-_0040code_007b_002dmcpu_003d_007d-command-line-option_002c-ARM-568"></a>
<dl><dt><code>-mcpu=</code><var>processor</var><code>[+</code><var>extension</var><code>...]</code><dd>This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
<code>arm1</code>,
<code>arm2</code>,
<code>arm250</code>,
<code>arm3</code>,
<code>arm6</code>,
<code>arm60</code>,
<code>arm600</code>,
<code>arm610</code>,
<code>arm620</code>,
<code>arm7</code>,
<code>arm7m</code>,
<code>arm7d</code>,
<code>arm7dm</code>,
<code>arm7di</code>,
<code>arm7dmi</code>,
<code>arm70</code>,
<code>arm700</code>,
<code>arm700i</code>,
<code>arm710</code>,
<code>arm710t</code>,
<code>arm720</code>,
<code>arm720t</code>,
<code>arm740t</code>,
<code>arm710c</code>,
<code>arm7100</code>,
<code>arm7500</code>,
<code>arm7500fe</code>,
<code>arm7t</code>,
<code>arm7tdmi</code>,
<code>arm7tdmi-s</code>,
<code>arm8</code>,
<code>arm810</code>,
<code>strongarm</code>,
<code>strongarm1</code>,
<code>strongarm110</code>,
<code>strongarm1100</code>,
<code>strongarm1110</code>,
<code>arm9</code>,
<code>arm920</code>,
<code>arm920t</code>,
<code>arm922t</code>,
<code>arm940t</code>,
<code>arm9tdmi</code>,
<code>fa526</code> (Faraday FA526 processor),
<code>fa626</code> (Faraday FA626 processor),
<code>arm9e</code>,
<code>arm926e</code>,
<code>arm926ej-s</code>,
<code>arm946e-r0</code>,
<code>arm946e</code>,
<code>arm946e-s</code>,
<code>arm966e-r0</code>,
<code>arm966e</code>,
<code>arm966e-s</code>,
<code>arm968e-s</code>,
<code>arm10t</code>,
<code>arm10tdmi</code>,
<code>arm10e</code>,
<code>arm1020</code>,
<code>arm1020t</code>,
<code>arm1020e</code>,
<code>arm1022e</code>,
<code>arm1026ej-s</code>,
<code>fa626te</code> (Faraday FA626TE processor),
<code>fa726te</code> (Faraday FA726TE processor),
<code>arm1136j-s</code>,
<code>arm1136jf-s</code>,
<code>arm1156t2-s</code>,
<code>arm1156t2f-s</code>,
<code>arm1176jz-s</code>,
<code>arm1176jzf-s</code>,
<code>mpcore</code>,
<code>mpcorenovfp</code>,
<code>cortex-a8</code>,
<code>cortex-a9</code>,
<code>cortex-r4</code>,
<code>cortex-m3</code>,
<code>ep9312</code> (ARM920 with Cirrus Maverick coprocessor),
<code>i80200</code> (Intel XScale processor)
<code>iwmmxt</code> (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
and
<code>xscale</code>.
The special name <code>all</code> may be used to allow the
assembler to accept instructions valid for any ARM processor.
<p>In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, <code>-mcpu=arm920+maverick</code>
is equivalent to specifying <code>-mcpu=ep9312</code>. The following extensions
are currently supported:
<code>+maverick</code>
<code>+iwmmxt</code>
and
<code>+xscale</code>.
<p><a name="index-_0040code_007b_002dmarch_003d_007d-command-line-option_002c-ARM-569"></a><br><dt><code>-march=</code><var>architecture</var><code>[+</code><var>extension</var><code>...]</code><dd>This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
will not execute on the target architecture. The following architecture
names are recognized:
<code>armv1</code>,
<code>armv2</code>,
<code>armv2a</code>,
<code>armv2s</code>,
<code>armv3</code>,
<code>armv3m</code>,
<code>armv4</code>,
<code>armv4xm</code>,
<code>armv4t</code>,
<code>armv4txm</code>,
<code>armv5</code>,
<code>armv5t</code>,
<code>armv5txm</code>,
<code>armv5te</code>,
<code>armv5texp</code>,
<code>armv6</code>,
<code>armv6j</code>,
<code>armv6k</code>,
<code>armv6z</code>,
<code>armv6zk</code>,
<code>armv7</code>,
<code>armv7-a</code>,
<code>armv7-r</code>,
<code>armv7-m</code>,
<code>iwmmxt</code>
and
<code>xscale</code>.
If both <code>-mcpu</code> and
<code>-march</code> are specified, the assembler will use
the setting for <code>-mcpu</code>.
<p>The architecture option can be extended with the same instruction set
extension options as the <code>-mcpu</code> option.
<p><a name="index-_0040code_007b_002dmfpu_003d_007d-command-line-option_002c-ARM-570"></a><br><dt><code>-mfpu=</code><var>floating-point-format</var><dd>
This option specifies the floating point format to assemble for. The
assembler will issue an error message if an attempt is made to assemble
an instruction which will not execute on the target floating point unit.
The following format options are recognized:
<code>softfpa</code>,
<code>fpe</code>,
<code>fpe2</code>,
<code>fpe3</code>,
<code>fpa</code>,
<code>fpa10</code>,
<code>fpa11</code>,
<code>arm7500fe</code>,
<code>softvfp</code>,
<code>softvfp+vfp</code>,
<code>vfp</code>,
<code>vfp10</code>,
<code>vfp10-r0</code>,
<code>vfp9</code>,
<code>vfpxd</code>,
<code>vfpv2</code>
<code>vfpv3</code>
<code>vfpv3-d16</code>
<code>arm1020t</code>,
<code>arm1020e</code>,
<code>arm1136jf-s</code>,
<code>maverick</code>
and
<code>neon</code>.
<p>In addition to determining which instructions are assembled, this option
also affects the way in which the <code>.double</code> assembler directive behaves
when assembling little-endian code.
<p>The default is dependent on the processor selected. For Architecture 5 or
later, the default is to assembler for VFP instructions; for earlier
architectures the default is to assemble for FPA instructions.
<p><a name="index-_0040code_007b_002dmthumb_007d-command-line-option_002c-ARM-571"></a><br><dt><code>-mthumb</code><dd>This option specifies that the assembler should start assembling Thumb
instructions; that is, it should behave as though the file starts with a
<code>.code 16</code> directive.
<p><a name="index-_0040code_007b_002dmthumb_002dinterwork_007d-command-line-option_002c-ARM-572"></a><br><dt><code>-mthumb-interwork</code><dd>This option specifies that the output generated by the assembler should
be marked as supporting interworking.
<p><a name="index-_0040code_007b_002dmapcs_007d-command-line-option_002c-ARM-573"></a><br><dt><code>-mapcs [26|32]</code><dd>This option specifies that the output generated by the assembler should
be marked as supporting the indicated version of the Arm Procedure.
Calling Standard.
<p><a name="index-_0040code_007b_002dmatpcs_007d-command-line-option_002c-ARM-574"></a><br><dt><code>-matpcs</code><dd>This option specifies that the output generated by the assembler should
be marked as supporting the Arm/Thumb Procedure Calling Standard. If
enabled this option will cause the assembler to create an empty
debugging section in the object file called .arm.atpcs. Debuggers can
use this to determine the ABI being used by.
<p><a name="index-_0040code_007b_002dmapcs_002dfloat_007d-command-line-option_002c-ARM-575"></a><br><dt><code>-mapcs-float</code><dd>This indicates the floating point variant of the APCS should be
used. In this variant floating point arguments are passed in FP
registers rather than integer registers.
<p><a name="index-_0040code_007b_002dmapcs_002dreentrant_007d-command-line-option_002c-ARM-576"></a><br><dt><code>-mapcs-reentrant</code><dd>This indicates that the reentrant variant of the APCS should be used.
This variant supports position independent code.
<p><a name="index-_0040code_007b_002dmfloat_002dabi_003d_007d-command-line-option_002c-ARM-577"></a><br><dt><code>-mfloat-abi=</code><var>abi</var><dd>This option specifies that the output generated by the assembler should be
marked as using specified floating point ABI.
The following values are recognized:
<code>soft</code>,
<code>softfp</code>
and
<code>hard</code>.
<p><a name="index-_0040code_007b_002deabi_003d_007d-command-line-option_002c-ARM-578"></a><br><dt><code>-meabi=</code><var>ver</var><dd>This option specifies which EABI version the produced object files should
conform to.
The following values are recognized:
<code>gnu</code>,
<code>4</code>
and
<code>5</code>.
<p><a name="index-_0040code_007b_002dEB_007d-command-line-option_002c-ARM-579"></a><br><dt><code>-EB</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
<p><a name="index-_0040code_007b_002dEL_007d-command-line-option_002c-ARM-580"></a><br><dt><code>-EL</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
<p><a name="index-_0040code_007b_002dk_007d-command-line-option_002c-ARM-581"></a><a name="index-PIC-code-generation-for-ARM-582"></a><br><dt><code>-k</code><dd>This option specifies that the output of the assembler should be marked
as position-independent code (PIC).
<p><a name="index-_0040code_007b_002d_002dfix_002dv4bx_007d-command-line-option_002c-ARM-583"></a><br><dt><code>--fix-v4bx</code><dd>Allow <code>BX</code> instructions in ARMv4 code. This is intended for use with
the linker option of the same name.
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<h4 class="subsection">9.3.2 Syntax</h4>
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<p>
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Up:&nbsp;<a rel="up" accesskey="u" href="ARM_002dDependent.html#ARM_002dDependent">ARM-Dependent</a>
<hr><br>
</div>
<h4 class="subsection">9.3.7 Unwinding</h4>
<p>The ABI for the ARM Architecture specifies a standard format for
exception unwind information. This information is used when an
exception is thrown to determine where control should be transferred.
In particular, the unwind information is used to determine which
function called the function that threw the exception, and which
function called that one, and so forth. This information is also used
to restore the values of callee-saved registers in the function
catching the exception.
<p>If you are writing functions in assembly code, and those functions
call other functions that throw exceptions, you must use assembly
pseudo ops to ensure that appropriate exception unwind information is
generated. Otherwise, if one of the functions called by your assembly
code throws an exception, the run-time library will be unable to
unwind the stack through your assembly code and your program will not
behave correctly.
<p>To illustrate the use of these pseudo ops, we will examine the code
that G++ generates for the following C++ input:
<pre class="verbatim">
void callee (int *);
int
caller ()
{
int i;
callee (&amp;i);
return i;
}
</pre>
<p>This example does not show how to throw or catch an exception from
assembly code. That is a much more complex operation and should
always be done in a high-level language, such as C++, that directly
supports exceptions.
<p>The code generated by one particular version of G++ when compiling the
example above is:
<pre class="verbatim">
_Z6callerv:
.fnstart
.LFB2:
@ Function supports interworking.
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {fp, lr}
.save {fp, lr}
.LCFI0:
.setfp fp, sp, #4
add fp, sp, #4
.LCFI1:
.pad #8
sub sp, sp, #8
.LCFI2:
sub r3, fp, #8
mov r0, r3
bl _Z6calleePi
ldr r3, [fp, #-8]
mov r0, r3
sub sp, fp, #4
ldmfd sp!, {fp, lr}
bx lr
.LFE2:
.fnend
</pre>
<p>Of course, the sequence of instructions varies based on the options
you pass to GCC and on the version of GCC in use. The exact
instructions are not important since we are focusing on the pseudo ops
that are used to generate unwind information.
<p>An important assumption made by the unwinder is that the stack frame
does not change during the body of the function. In particular, since
we assume that the assembly code does not itself throw an exception,
the only point where an exception can be thrown is from a call, such
as the <code>bl</code> instruction above. At each call site, the same saved
registers (including <code>lr</code>, which indicates the return address)
must be located in the same locations relative to the frame pointer.
<p>The <code>.fnstart</code> (see <a href="arm_005ffnstart.html#arm_005ffnstart">.fnstart pseudo op</a>) pseudo
op appears immediately before the first instruction of the function
while the <code>.fnend</code> (see <a href="arm_005ffnend.html#arm_005ffnend">.fnend pseudo op</a>) pseudo
op appears immediately after the last instruction of the function.
These pseudo ops specify the range of the function.
<p>Only the order of the other pseudos ops (e.g., <code>.setfp</code> or
<code>.pad</code>) matters; their exact locations are irrelevant. In the
example above, the compiler emits the pseudo ops with particular
instructions. That makes it easier to understand the code, but it is
not required for correctness. It would work just as well to emit all
of the pseudo ops other than <code>.fnend</code> in the same order, but
immediately after <code>.fnstart</code>.
<p>The <code>.save</code> (see <a href="arm_005fsave.html#arm_005fsave">.save pseudo op</a>) pseudo op
indicates registers that have been saved to the stack so that they can
be restored before the function returns. The argument to the
<code>.save</code> pseudo op is a list of registers to save. If a register
is &ldquo;callee-saved&rdquo; (as specified by the ABI) and is modified by the
function you are writing, then your code must save the value before it
is modified and restore the original value before the function
returns. If an exception is thrown, the run-time library restores the
values of these registers from their locations on the stack before
returning control to the exception handler. (Of course, if an
exception is not thrown, the function that contains the <code>.save</code>
pseudo op restores these registers in the function epilogue, as is
done with the <code>ldmfd</code> instruction above.)
<p>You do not have to save callee-saved registers at the very beginning
of the function and you do not need to use the <code>.save</code> pseudo op
immediately following the point at which the registers are saved.
However, if you modify a callee-saved register, you must save it on
the stack before modifying it and before calling any functions which
might throw an exception. And, you must use the <code>.save</code> pseudo
op to indicate that you have done so.
<p>The <code>.pad</code> (see <a href="arm_005fpad.html#arm_005fpad">.pad</a>) pseudo op indicates a
modification of the stack pointer that does not save any registers.
The argument is the number of bytes (in decimal) that are subtracted
from the stack pointer. (On ARM CPUs, the stack grows downwards, so
subtracting from the stack pointer increases the size of the stack.)
<p>The <code>.setfp</code> (see <a href="arm_005fsetfp.html#arm_005fsetfp">.setfp pseudo op</a>) pseudo op
indicates the register that contains the frame pointer. The first
argument is the register that is set, which is typically <code>fp</code>.
The second argument indicates the register from which the frame
pointer takes its value. The third argument, if present, is the value
(in decimal) added to the register specified by the second argument to
compute the value of the frame pointer. You should not modify the
frame pointer in the body of the function.
<p>If you do not use a frame pointer, then you should not use the
<code>.setfp</code> pseudo op. If you do not use a frame pointer, then you
should avoid modifying the stack pointer outside of the function
prologue. Otherwise, the run-time library will be unable to find
saved registers when it is unwinding the stack.
<p>The pseudo ops described above are sufficient for writing assembly
code that calls functions which may throw exceptions. If you need to
know more about the object-file format used to represent unwind
information, you may consult the <cite>Exception Handling ABI for the
ARM Architecture</cite> available from <a href="http://infocenter.arm.com">http://infocenter.arm.com</a>.
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<h5 class="subsubsection">9.3.2.1 Special Characters</h5>
<p><a name="index-line-comment-character_002c-ARM-584"></a><a name="index-ARM-line-comment-character-585"></a>The presence of a <span class="samp">@</span> on a line indicates the start of a comment
that extends to the end of the current line. If a <span class="samp">#</span> appears as
the first character of a line, the whole line is treated as a comment.
<p><a name="index-line-separator_002c-ARM-586"></a><a name="index-statement-separator_002c-ARM-587"></a><a name="index-ARM-line-separator-588"></a>The <span class="samp">;</span> character can be used instead of a newline to separate
statements.
<p><a name="index-immediate-character_002c-ARM-589"></a><a name="index-ARM-immediate-character-590"></a>Either <span class="samp">#</span> or <span class="samp">$</span> can be used to indicate immediate operands.
<p><a name="index-identifiers_002c-ARM-591"></a><a name="index-ARM-identifiers-592"></a>*TODO* Explain about /data modifier on symbols.
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<h3 class="section">9.3 ARM Dependent Features</h3>
<p><a name="index-ARM-support-564"></a><a name="index-Thumb-support-565"></a>
<ul class="menu">
<li><a accesskey="1" href="ARM-Options.html#ARM-Options">ARM Options</a>: Options
<li><a accesskey="2" href="ARM-Syntax.html#ARM-Syntax">ARM Syntax</a>: Syntax
<li><a accesskey="3" href="ARM-Floating-Point.html#ARM-Floating-Point">ARM Floating Point</a>: Floating Point
<li><a accesskey="4" href="ARM-Directives.html#ARM-Directives">ARM Directives</a>: ARM Machine Directives
<li><a accesskey="5" href="ARM-Opcodes.html#ARM-Opcodes">ARM Opcodes</a>: Opcodes
<li><a accesskey="6" href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols">ARM Mapping Symbols</a>: Mapping Symbols
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<h5 class="subsubsection">9.3.2.2 Register Names</h5>
<p><a name="index-ARM-register-names-593"></a><a name="index-register-names_002c-ARM-594"></a>*TODO* Explain about ARM register naming, and the predefined names.
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Up:&nbsp;<a rel="up" accesskey="u" href="ARM-Syntax.html#ARM-Syntax">ARM Syntax</a>
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</div>
<h5 class="subsubsection">9.3.3.1 ARM relocation generation</h5>
<p><a name="index-data-relocations_002c-ARM-597"></a><a name="index-ARM-data-relocations-598"></a>Specific data relocations can be generated by putting the relocation name
in parentheses after the symbol name. For example:
<pre class="smallexample"> .word foo(TARGET1)
</pre>
<p>This will generate an <span class="samp">R_ARM_TARGET1</span> relocation against the symbol
<var>foo</var>.
The following relocations are supported:
<code>GOT</code>,
<code>GOTOFF</code>,
<code>TARGET1</code>,
<code>TARGET2</code>,
<code>SBREL</code>,
<code>TLSGD</code>,
<code>TLSLDM</code>,
<code>TLSLDO</code>,
<code>GOTTPOFF</code>
and
<code>TPOFF</code>.
<p>For compatibility with older toolchains the assembler also accepts
<code>(PLT)</code> after branch targets. This will generate the deprecated
<span class="samp">R_ARM_PLT32</span> relocation.
<p><a name="index-MOVW-and-MOVT-relocations_002c-ARM-599"></a>Relocations for <span class="samp">MOVW</span> and <span class="samp">MOVT</span> instructions can be generated
by prefixing the value with <span class="samp">#:lower16:</span> and <span class="samp">#:upper16</span>
respectively. For example to load the 32-bit address of foo into r0:
<pre class="smallexample"> MOVW r0, #:lower16:foo
MOVT r0, #:upper16:foo
</pre>
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<h4 class="subsection">9.4.3 Opcodes</h4>
<p><a name="index-AVR-opcode-summary-657"></a><a name="index-opcode-summary_002c-AVR-658"></a><a name="index-mnemonics_002c-AVR-659"></a><a name="index-instruction-summary_002c-AVR-660"></a>For detailed information on the AVR machine instruction set, see
<a href="www.atmel.com/products/AVR">www.atmel.com/products/AVR</a>.
<p><code>as</code> implements all the standard AVR opcodes.
The following table summarizes the AVR opcodes, and their arguments.
<pre class="smallexample"> <i>Legend:</i>
r <span class="roman">any register</span>
d <span class="roman">`ldi' register (r16-r31)</span>
v <span class="roman">`movw' even register (r0, r2, ..., r28, r30)</span>
a <span class="roman">`fmul' register (r16-r23)</span>
w <span class="roman">`adiw' register (r24,r26,r28,r30)</span>
e <span class="roman">pointer registers (X,Y,Z)</span>
b <span class="roman">base pointer register and displacement ([YZ]+disp)</span>
z <span class="roman">Z pointer register (for [e]lpm Rd,Z[+])</span>
M <span class="roman">immediate value from 0 to 255</span>
n <span class="roman">immediate value from 0 to 255 ( n = ~M ). Relocation impossible</span>
s <span class="roman">immediate value from 0 to 7</span>
P <span class="roman">Port address value from 0 to 63. (in, out)</span>
p <span class="roman">Port address value from 0 to 31. (cbi, sbi, sbic, sbis)</span>
K <span class="roman">immediate value from 0 to 63 (used in `adiw', `sbiw')</span>
i <span class="roman">immediate value</span>
l <span class="roman">signed pc relative offset from -64 to 63</span>
L <span class="roman">signed pc relative offset from -2048 to 2047</span>
h <span class="roman">absolute code address (call, jmp)</span>
S <span class="roman">immediate value from 0 to 7 (S = s &lt;&lt; 4)</span>
? <span class="roman">use this opcode entry if no parameters, else use next opcode entry</span>
1001010010001000 clc
1001010011011000 clh
1001010011111000 cli
1001010010101000 cln
1001010011001000 cls
1001010011101000 clt
1001010010111000 clv
1001010010011000 clz
1001010000001000 sec
1001010001011000 seh
1001010001111000 sei
1001010000101000 sen
1001010001001000 ses
1001010001101000 set
1001010000111000 sev
1001010000011000 sez
100101001SSS1000 bclr S
100101000SSS1000 bset S
1001010100001001 icall
1001010000001001 ijmp
1001010111001000 lpm ?
1001000ddddd010+ lpm r,z
1001010111011000 elpm ?
1001000ddddd011+ elpm r,z
0000000000000000 nop
1001010100001000 ret
1001010100011000 reti
1001010110001000 sleep
1001010110011000 break
1001010110101000 wdr
1001010111101000 spm
000111rdddddrrrr adc r,r
000011rdddddrrrr add r,r
001000rdddddrrrr and r,r
000101rdddddrrrr cp r,r
000001rdddddrrrr cpc r,r
000100rdddddrrrr cpse r,r
001001rdddddrrrr eor r,r
001011rdddddrrrr mov r,r
100111rdddddrrrr mul r,r
001010rdddddrrrr or r,r
000010rdddddrrrr sbc r,r
000110rdddddrrrr sub r,r
001001rdddddrrrr clr r
000011rdddddrrrr lsl r
000111rdddddrrrr rol r
001000rdddddrrrr tst r
0111KKKKddddKKKK andi d,M
0111KKKKddddKKKK cbr d,n
1110KKKKddddKKKK ldi d,M
11101111dddd1111 ser d
0110KKKKddddKKKK ori d,M
0110KKKKddddKKKK sbr d,M
0011KKKKddddKKKK cpi d,M
0100KKKKddddKKKK sbci d,M
0101KKKKddddKKKK subi d,M
1111110rrrrr0sss sbrc r,s
1111111rrrrr0sss sbrs r,s
1111100ddddd0sss bld r,s
1111101ddddd0sss bst r,s
10110PPdddddPPPP in r,P
10111PPrrrrrPPPP out P,r
10010110KKddKKKK adiw w,K
10010111KKddKKKK sbiw w,K
10011000pppppsss cbi p,s
10011010pppppsss sbi p,s
10011001pppppsss sbic p,s
10011011pppppsss sbis p,s
111101lllllll000 brcc l
111100lllllll000 brcs l
111100lllllll001 breq l
111101lllllll100 brge l
111101lllllll101 brhc l
111100lllllll101 brhs l
111101lllllll111 brid l
111100lllllll111 brie l
111100lllllll000 brlo l
111100lllllll100 brlt l
111100lllllll010 brmi l
111101lllllll001 brne l
111101lllllll010 brpl l
111101lllllll000 brsh l
111101lllllll110 brtc l
111100lllllll110 brts l
111101lllllll011 brvc l
111100lllllll011 brvs l
111101lllllllsss brbc s,l
111100lllllllsss brbs s,l
1101LLLLLLLLLLLL rcall L
1100LLLLLLLLLLLL rjmp L
1001010hhhhh111h call h
1001010hhhhh110h jmp h
1001010rrrrr0101 asr r
1001010rrrrr0000 com r
1001010rrrrr1010 dec r
1001010rrrrr0011 inc r
1001010rrrrr0110 lsr r
1001010rrrrr0001 neg r
1001000rrrrr1111 pop r
1001001rrrrr1111 push r
1001010rrrrr0111 ror r
1001010rrrrr0010 swap r
00000001ddddrrrr movw v,v
00000010ddddrrrr muls d,d
000000110ddd0rrr mulsu a,a
000000110ddd1rrr fmul a,a
000000111ddd0rrr fmuls a,a
000000111ddd1rrr fmulsu a,a
1001001ddddd0000 sts i,r
1001000ddddd0000 lds r,i
10o0oo0dddddbooo ldd r,b
100!000dddddee-+ ld r,e
10o0oo1rrrrrbooo std b,r
100!001rrrrree-+ st e,r
1001010100011001 eicall
1001010000011001 eijmp
</pre>
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<h4 class="subsection">9.4.1 Options</h4>
<p><a name="index-AVR-options-_0028none_0029-641"></a><a name="index-options-for-AVR-_0028none_0029-642"></a>
<a name="index-_0040code_007b_002dmmcu_003d_007d-command-line-option_002c-AVR-643"></a>
<dl><dt><code>-mmcu=</code><var>mcu</var><dd>Specify ATMEL AVR instruction set or MCU type.
<p>Instruction set avr1 is for the minimal AVR core, not supported by the C
compiler, only for assembler programs (MCU types: at90s1200,
attiny11, attiny12, attiny15, attiny28).
<p>Instruction set avr2 (default) is for the classic AVR core with up to
8K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343,
attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534,
at90s8535).
<p>Instruction set avr25 is for the classic AVR core with up to 8K program memory
space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313,
attiny24, attiny44, attiny84, attiny25, attiny45, attiny85, attiny261,
attiny461, attiny861, attiny43u, attiny48, attiny88, at86rf401).
<p>Instruction set avr3 is for the classic AVR core with up to 128K program
memory space (MCU types: at43usb355, at76c711).
<p>Instruction set avr31 is for the classic AVR core with exactly 128K program
memory space (MCU types: atmega103, at43usb320).
<p>Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP
instructions (MCU types: attiny167, at90usb82, at90usb162).
<p>Instruction set avr4 is for the enhanced AVR core with up to 8K program
memory space (MCU types: atmega48, atmega48p,atmega8, atmega88, atmega88p,
atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b,
at90pwm3, at90pwm3b).
<p>Instruction set avr5 is for the enhanced AVR core with up to 128K program
memory space (MCU types: atmega16, atmega161, atmega162, atmega163, atmega164p,
atmega165, atmega165p, atmega168, atmega168p, atmega169, atmega169p, atmega32,
atmega323, atmega324p, atmega325, atmega325p, atmega3250, atmega3250p,
atmega328p, atmega329, atmega329p, atmega3290, atmega3290p, atmega406, atmega64,
atmega640, atmega644, atmega644p, atmega645, atmega6450, atmega649, atmega6490,
atmega16hva, at90can32, at90can64, at90pwm216, at90pwm316, atmega16u4,
atmega32c1, atmega32m1, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k).
<p>Instruction set avr51 is for the enhanced AVR core with exactly 128K program
memory space (MCU types: atmega128, atmega1280, atmega1281, atmega1284p,
at90can128, at90usb1286, at90usb1287).
<p>Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types:
atmega2560, atmega2561).
<p>Instruction set avrxmega4 is for the XMEGA AVR cor with up to 64K program
memory space and less than 64K data space (MCU types: atxmega64a3).
<p>Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
memory space and greater than 64K data space (MCU types: atxmega64a1).
<p>Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program
memory space and less than 64K data space (MCU types: atxmega128a3,
atxmega256a3, atxmega256a3b).
<p>Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program
memory space and greater than 64K data space (MCU types: atxmega128a1).
<p><a name="index-_0040code_007b_002dmall_002dopcodes_007d-command-line-option_002c-AVR-644"></a><br><dt><code>-mall-opcodes</code><dd>Accept all AVR opcodes, even if not supported by <code>-mmcu</code>.
<p><a name="index-_0040code_007b_002dmno_002dskip_002dbug_007d-command-line-option_002c-AVR-645"></a><br><dt><code>-mno-skip-bug</code><dd>This option disable warnings for skipping two-word instructions.
<p><a name="index-_0040code_007b_002dmno_002dwrap_007d-command-line-option_002c-AVR-646"></a><br><dt><code>-mno-wrap</code><dd>This option reject <code>rjmp/rcall</code> instructions with 8K wrap-around.
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<h4 class="subsection">9.4.2 Syntax</h4>
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<h5 class="subsubsection">9.4.2.1 Special Characters</h5>
<p><a name="index-line-comment-character_002c-AVR-647"></a><a name="index-AVR-line-comment-character-648"></a>
The presence of a <span class="samp">;</span> on a line indicates the start of a comment
that extends to the end of the current line. If a <span class="samp">#</span> appears as
the first character of a line, the whole line is treated as a comment.
<p><a name="index-line-separator_002c-AVR-649"></a><a name="index-statement-separator_002c-AVR-650"></a><a name="index-AVR-line-separator-651"></a>
The <span class="samp">$</span> character can be used instead of a newline to separate
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<h3 class="section">9.4 AVR Dependent Features</h3>
<p><a name="index-AVR-support-640"></a>
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<h5 class="subsubsection">9.4.2.3 Relocatable Expression Modifiers</h5>
<p><a name="index-AVR-modifiers-654"></a><a name="index-syntax_002c-AVR-655"></a>
The assembler supports several modifiers when using relocatable addresses
in AVR instruction operands. The general syntax is the following:
<pre class="smallexample"> modifier(relocatable-expression)
</pre>
<a name="index-symbol-modifiers-656"></a>
<dl>
<dt><code>lo8</code><dd>
This modifier allows you to use bits 0 through 7 of
an address expression as 8 bit relocatable expression.
<br><dt><code>hi8</code><dd>
This modifier allows you to use bits 7 through 15 of an address expression
as 8 bit relocatable expression. This is useful with, for example, the
AVR <span class="samp">ldi</span> instruction and <span class="samp">lo8</span> modifier.
<p>For example
<pre class="smallexample"> ldi r26, lo8(sym+10)
ldi r27, hi8(sym+10)
</pre>
<br><dt><code>hh8</code><dd>
This modifier allows you to use bits 16 through 23 of
an address expression as 8 bit relocatable expression.
Also, can be useful for loading 32 bit constants.
<br><dt><code>hlo8</code><dd>
Synonym of <span class="samp">hh8</span>.
<br><dt><code>hhi8</code><dd>
This modifier allows you to use bits 24 through 31 of
an expression as 8 bit expression. This is useful with, for example, the
AVR <span class="samp">ldi</span> instruction and <span class="samp">lo8</span>, <span class="samp">hi8</span>, <span class="samp">hlo8</span>,
<span class="samp">hhi8</span>, modifier.
<p>For example
<pre class="smallexample"> ldi r26, lo8(285774925)
ldi r27, hi8(285774925)
ldi r28, hlo8(285774925)
ldi r29, hhi8(285774925)
; r29,r28,r27,r26 = 285774925
</pre>
<br><dt><code>pm_lo8</code><dd>
This modifier allows you to use bits 0 through 7 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory. The using of <span class="samp">pm_lo8</span> similar
to <span class="samp">lo8</span>.
<br><dt><code>pm_hi8</code><dd>
This modifier allows you to use bits 8 through 15 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory.
<br><dt><code>pm_hh8</code><dd>
This modifier allows you to use bits 15 through 23 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory.
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<h5 class="subsubsection">9.4.2.2 Register Names</h5>
<p><a name="index-AVR-register-names-652"></a><a name="index-register-names_002c-AVR-653"></a>
The AVR has 32 x 8-bit general purpose working registers <span class="samp">r0</span>,
<span class="samp">r1</span>, ... <span class="samp">r31</span>.
Six of the 32 registers can be used as three 16-bit indirect address
register pointers for Data Space addressing. One of the these address
pointers can also be used as an address pointer for look up tables in
Flash program memory. These added function registers are the 16-bit
<span class="samp">X</span>, <span class="samp">Y</span> and <span class="samp">Z</span> - registers.
<pre class="smallexample"> X = <span class="roman">r26:r27</span>
Y = <span class="roman">r28:r29</span>
Z = <span class="roman">r30:r31</span>
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<h3 class="section">7.1 <code>.abort</code></h3>
<p><a name="index-_0040code_007babort_007d-directive-272"></a><a name="index-stopping-the-assembly-273"></a>This directive stops the assembly immediately. It is for
compatibility with other assemblers. The original idea was that the
assembly language source would be piped into the assembler. If the sender
of the source quit, it could use this directive tells <span class="command">as</span> to
quit also. One day <code>.abort</code> will not be supported.
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Up:&nbsp;<a rel="up" accesskey="u" href="Xtensa-Directives.html#Xtensa-Directives">Xtensa Directives</a>
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<h5 class="subsubsection">9.36.5.7 absolute-literals</h5>
<p><a name="index-_0040code_007babsolute_002dliterals_007d-directive-1893"></a><a name="index-_0040code_007bno_002dabsolute_002dliterals_007d-directive-1894"></a>
The <code>absolute-literals</code> and <code>no-absolute-literals</code>
directives control the absolute vs. PC-relative mode for <code>L32R</code>
instructions. These are relevant only for Xtensa configurations that
include the absolute addressing option for <code>L32R</code> instructions.
<pre class="smallexample"> .begin [no-]absolute-literals
.end [no-]absolute-literals
</pre>
<p>These directives do not change the <code>L32R</code> mode&mdash;they only cause
the assembler to emit the appropriate kind of relocation for <code>L32R</code>
instructions and to place the literal values in the appropriate section.
To change the <code>L32R</code> mode, the program must write the
<code>LITBASE</code> special register. It is the programmer's responsibility
to keep track of the mode and indicate to the assembler which mode is
used in each region of code.
<p>If the Xtensa configuration includes the absolute <code>L32R</code> addressing
option, the default is to assume absolute <code>L32R</code> addressing unless
the <span class="samp">--no-absolute-literals</span> command-line option is specified.
Otherwise, the default is to assume PC-relative <code>L32R</code> addressing.
The <code>absolute-literals</code> directive can then be used to override
the default determined by the command-line options.
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Previous:&nbsp;<a rel="previous" accesskey="p" href="Reporting-Bugs.html#Reporting-Bugs">Reporting Bugs</a>,
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<hr><br>
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<h2 class="chapter">11 Acknowledgements</h2>
<p>If you have contributed to GAS and your name isn't listed here,
it is not meant as a slight. We just don't know about it. Send mail to the
maintainer, and we'll correct the situation. Currently
<!-- (January 1994), -->
the maintainer is Ken Raeburn (email address <code>raeburn@cygnus.com</code>).
<p>Dean Elsner wrote the original <span class="sc">gnu</span> assembler for the VAX.<a rel="footnote" href="#fn-1" name="fnd-1"><sup>1</sup></a>
<p>Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug
information and the 68k series machines, most of the preprocessing pass, and
extensive changes in <span class="file">messages.c</span>, <span class="file">input-file.c</span>, <span class="file">write.c</span>.
<p>K. Richard Pixley maintained GAS for a while, adding various enhancements and
many bug fixes, including merging support for several processors, breaking GAS
up to handle multiple object file format back ends (including heavy rewrite,
testing, an integration of the coff and b.out back ends), adding configuration
including heavy testing and verification of cross assemblers and file splits
and renaming, converted GAS to strictly ANSI C including full prototypes, added
support for m680[34]0 and cpu32, did considerable work on i960 including a COFF
port (including considerable amounts of reverse engineering), a SPARC opcode
file rewrite, DECstation, rs6000, and hp300hpux host ports, updated &ldquo;know&rdquo;
assertions and made them work, much other reorganization, cleanup, and lint.
<p>Ken Raeburn wrote the high-level BFD interface code to replace most of the code
in format-specific I/O modules.
<p>The original VMS support was contributed by David L. Kashtan. Eric Youngdale
has done much work with it since.
<p>The Intel 80386 machine description was written by Eliot Dresselhaus.
<p>Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
<p>The Motorola 88k machine description was contributed by Devon Bowen of Buffalo
University and Torbjorn Granlund of the Swedish Institute of Computer Science.
<p>Keith Knowles at the Open Software Foundation wrote the original MIPS back end
(<span class="file">tc-mips.c</span>, <span class="file">tc-mips.h</span>), and contributed Rose format support
(which hasn't been merged in yet). Ralph Campbell worked with the MIPS code to
support a.out format.
<p>Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
Steve Chamberlain of Cygnus Support. Steve also modified the COFF back end to
use BFD for some low-level operations, for use with the H8/300 and AMD 29k
targets.
<p>John Gilmore built the AMD 29000 support, added <code>.include</code> support, and
simplified the configuration of which versions accept which directives. He
updated the 68k machine description so that Motorola's opcodes always produced
fixed-size instructions (e.g., <code>jsr</code>), while synthetic instructions
remained shrinkable (<code>jbsr</code>). John fixed many bugs, including true tested
cross-compilation support, and one bug in relaxation that took a week and
required the proverbial one-bit fix.
<p>Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the
68k, completed support for some COFF targets (68k, i386 SVR3, and SCO Unix),
added support for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and
PowerPC assembler, and made a few other minor patches.
<p>Steve Chamberlain made GAS able to generate listings.
<p>Hewlett-Packard contributed support for the HP9000/300.
<p>Jeff Law wrote GAS and BFD support for the native HPPA object format (SOM)
along with a fairly extensive HPPA testsuite (for both SOM and ELF object
formats). This work was supported by both the Center for Software Science at
the University of Utah and Cygnus Support.
<p>Support for ELF format files has been worked on by Mark Eichin of Cygnus
Support (original, incomplete implementation for SPARC), Pete Hoogenboom and
Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open
Software Foundation (i386 mainly), and Ken Raeburn of Cygnus Support (sparc,
and some initial 64-bit support).
<p>Linas Vepstas added GAS support for the ESA/390 &ldquo;IBM 370&rdquo; architecture.
<p>Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD
support for openVMS/Alpha.
<p>Timothy Wall, Michael Hayes, and Greg Smart contributed to the various tic*
flavors.
<p>David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from Tensilica,
Inc. added support for Xtensa processors.
<p>Several engineers at Cygnus Support have also provided many small bug fixes and
configuration enhancements.
<p>Many others have contributed large or small bugfixes and enhancements. If
you have contributed significant work and are not mentioned on this list, and
want to be, let us know. Some of the history has been lost; we are not
intentionally leaving anyone out.
<!-- *-texinfo-*- -->
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<hr>
<h4>Footnotes</h4><p class="footnote"><small>[<a name="fn-1" href="#fnd-1">1</a>]</small> Any
more details?</p>
<p><hr></div>
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<h3 class="section">7.3 <code>.align </code><var>abs-expr</var><code>, </code><var>abs-expr</var><code>, </code><var>abs-expr</var></h3>
<p><a name="index-padding-the-location-counter-275"></a><a name="index-_0040code_007balign_007d-directive-276"></a>Pad the location counter (in the current subsection) to a particular storage
boundary. The first expression (which must be absolute) is the alignment
required, as described below.
<p>The second expression (also absolute) gives the fill value to be stored in the
padding bytes. It (and the comma) may be omitted. If it is omitted, the
padding bytes are normally zero. However, on some systems, if the section is
marked as containing code and the fill value is omitted, the space is filled
with no-op instructions.
<p>The third expression is also absolute, and is also optional. If it is present,
it is the maximum number of bytes that should be skipped by this alignment
directive. If doing the alignment would require skipping more bytes than the
specified maximum, then the alignment is not done at all. You can omit the
fill value (the second argument) entirely by simply using two commas after the
required alignment; this can be useful if you want the alignment to be filled
with no-op instructions when appropriate.
<p>The way the required alignment is specified varies from system to system.
For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32,
s390, sparc, tic4x, tic80 and xtensa, the first expression is the
alignment request in bytes. For example <span class="samp">.align 8</span> advances
the location counter until it is a multiple of 8. If the location counter
is already a multiple of 8, no change is needed. For the tic54x, the
first expression is the alignment request in words.
<p>For other systems, including ppc, i386 using a.out format, arm and
strongarm, it is the
number of low-order zero bits the location counter must have after
advancement. For example <span class="samp">.align 3</span> advances the location
counter until it a multiple of 8. If the location counter is already a
multiple of 8, no change is needed.
<p>This inconsistency is due to the different behaviors of the various
native assemblers for these systems which GAS must emulate.
GAS also provides <code>.balign</code> and <code>.p2align</code> directives,
described later, which have a consistent behavior across all
architectures (but are specific to GAS).
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<h4 class="subsection">9.1.5 Alpha Assembler Directives</h4>
<p><span class="command">as</span> for the Alpha supports many additional directives for
compatibility with the native assembler. This section describes them only
briefly.
<p><a name="index-Alpha_002donly-directives-531"></a>These are the additional directives in <code>as</code> for the Alpha:
<dl>
<dt><code>.arch </code><var>cpu</var><dd>Specifies the target processor. This is equivalent to the
<span class="option">-m</span><var>cpu</var> command-line option. See <a href="Alpha-Options.html#Alpha-Options">Options</a>,
for a list of values for <var>cpu</var>.
<br><dt><code>.ent </code><var>function</var><code>[, </code><var>n</var><code>]</code><dd>Mark the beginning of <var>function</var>. An optional number may follow for
compatibility with the OSF/1 assembler, but is ignored. When generating
<code>.mdebug</code> information, this will create a procedure descriptor for
the function. In ELF, it will mark the symbol as a function a-la the
generic <code>.type</code> directive.
<br><dt><code>.end </code><var>function</var><dd>Mark the end of <var>function</var>. In ELF, it will set the size of the symbol
a-la the generic <code>.size</code> directive.
<br><dt><code>.mask </code><var>mask</var><code>, </code><var>offset</var><dd>Indicate which of the integer registers are saved in the current
function's stack frame. <var>mask</var> is interpreted a bit mask in which
bit <var>n</var> set indicates that register <var>n</var> is saved. The registers
are saved in a block located <var>offset</var> bytes from the <dfn>canonical
frame address</dfn> (CFA) which is the value of the stack pointer on entry to
the function. The registers are saved sequentially, except that the
return address register (normally <code>$26</code>) is saved first.
<p>This and the other directives that describe the stack frame are
currently only used when generating <code>.mdebug</code> information. They
may in the future be used to generate DWARF2 <code>.debug_frame</code> unwind
information for hand written assembly.
<br><dt><code>.fmask </code><var>mask</var><code>, </code><var>offset</var><dd>Indicate which of the floating-point registers are saved in the current
stack frame. The <var>mask</var> and <var>offset</var> parameters are interpreted
as with <code>.mask</code>.
<br><dt><code>.frame </code><var>framereg</var><code>, </code><var>frameoffset</var><code>, </code><var>retreg</var><code>[, </code><var>argoffset</var><code>]</code><dd>Describes the shape of the stack frame. The frame pointer in use is
<var>framereg</var>; normally this is either <code>$fp</code> or <code>$sp</code>. The
frame pointer is <var>frameoffset</var> bytes below the CFA. The return
address is initially located in <var>retreg</var> until it is saved as
indicated in <code>.mask</code>. For compatibility with OSF/1 an optional
<var>argoffset</var> parameter is accepted and ignored. It is believed to
indicate the offset from the CFA to the saved argument registers.
<br><dt><code>.prologue </code><var>n</var><dd>Indicate that the stack frame is set up and all registers have been
spilled. The argument <var>n</var> indicates whether and how the function
uses the incoming <dfn>procedure vector</dfn> (the address of the called
function) in <code>$27</code>. 0 indicates that <code>$27</code> is not used; 1
indicates that the first two instructions of the function use <code>$27</code>
to perform a load of the GP register; 2 indicates that <code>$27</code> is
used in some non-standard way and so the linker cannot elide the load of
the procedure vector during relaxation.
<br><dt><code>.usepv </code><var>function</var><code>, </code><var>which</var><dd>Used to indicate the use of the <code>$27</code> register, similar to
<code>.prologue</code>, but without the other semantics of needing to
be inside an open <code>.ent</code>/<code>.end</code> block.
<p>The <var>which</var> argument should be either <code>no</code>, indicating that
<code>$27</code> is not used, or <code>std</code>, indicating that the first two
instructions of the function perform a GP load.
<p>One might use this directive instead of <code>.prologue</code> if you are
also using dwarf2 CFI directives.
<br><dt><code>.gprel32 </code><var>expression</var><dd>Computes the difference between the address in <var>expression</var> and the
GP for the current object file, and stores it in 4 bytes. In addition
to being smaller than a full 8 byte address, this also does not require
a dynamic relocation when used in a shared library.
<br><dt><code>.t_floating </code><var>expression</var><dd>Stores <var>expression</var> as an <span class="sc">ieee</span> double precision value.
<br><dt><code>.s_floating </code><var>expression</var><dd>Stores <var>expression</var> as an <span class="sc">ieee</span> single precision value.
<br><dt><code>.f_floating </code><var>expression</var><dd>Stores <var>expression</var> as a VAX F format value.
<br><dt><code>.g_floating </code><var>expression</var><dd>Stores <var>expression</var> as a VAX G format value.
<br><dt><code>.d_floating </code><var>expression</var><dd>Stores <var>expression</var> as a VAX D format value.
<br><dt><code>.set </code><var>feature</var><dd>Enables or disables various assembler features. Using the positive
name of the feature enables while using <span class="samp">no</span><var>feature</var> disables.
<dl>
<dt><code>at</code><dd>Indicates that macro expansions may clobber the <dfn>assembler
temporary</dfn> (<code>$at</code> or <code>$28</code>) register. Some macros may not be
expanded without this and will generate an error message if <code>noat</code>
is in effect. When <code>at</code> is in effect, a warning will be generated
if <code>$at</code> is used by the programmer.
<br><dt><code>macro</code><dd>Enables the expansion of macro instructions. Note that variants of real
instructions, such as <code>br label</code> vs <code>br $31,label</code> are
considered alternate forms and not macros.
<br><dt><code>move</code><dt><code>reorder</code><dt><code>volatile</code><dd>These control whether and how the assembler may re-order instructions.
Accepted for compatibility with the OSF/1 assembler, but <span class="command">as</span>
does not do instruction scheduling, so these features are ignored.
</dl>
</dl>
<p>The following directives are recognized for compatibility with the OSF/1
assembler but are ignored.
<pre class="example"> .proc .aproc
.reguse .livereg
.option .aent
.ugen .eflag
.alias .noalias
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<h4 class="subsection">9.1.4 Floating Point</h4>
<p><a name="index-floating-point_002c-Alpha-_0028_0040sc_007bieee_007d_0029-529"></a><a name="index-Alpha-floating-point-_0028_0040sc_007bieee_007d_0029-530"></a>The Alpha family uses both <span class="sc">ieee</span> and VAX floating-point numbers.
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<h4 class="subsection">9.1.1 Notes</h4>
<p><a name="index-Alpha-notes-507"></a><a name="index-notes-for-Alpha-508"></a>
The documentation here is primarily for the ELF object format.
<code>as</code> also supports the ECOFF and EVAX formats, but
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<h4 class="subsection">9.1.6 Opcodes</h4>
<p>For detailed information on the Alpha machine instruction set, see the
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<h4 class="subsection">9.1.2 Options</h4>
<p><a name="index-Alpha-options-509"></a><a name="index-options-for-Alpha-510"></a>
<a name="index-_0040code_007b_002dm_0040var_007bcpu_007d_007d-command-line-option_002c-Alpha-511"></a>
<dl><dt><span class="option">-m</span><var>cpu</var><dd>This option specifies the target processor. If an attempt is made to
assemble an instruction which will not execute on the target processor,
the assembler may either expand the instruction as a macro or issue an
error message. This option is equivalent to the <code>.arch</code> directive.
<p>The following processor names are recognized:
<code>21064</code>,
<code>21064a</code>,
<code>21066</code>,
<code>21068</code>,
<code>21164</code>,
<code>21164a</code>,
<code>21164pc</code>,
<code>21264</code>,
<code>21264a</code>,
<code>21264b</code>,
<code>ev4</code>,
<code>ev5</code>,
<code>lca45</code>,
<code>ev5</code>,
<code>ev56</code>,
<code>pca56</code>,
<code>ev6</code>,
<code>ev67</code>,
<code>ev68</code>.
The special name <code>all</code> may be used to allow the assembler to accept
instructions valid for any Alpha processor.
<p>In order to support existing practice in OSF/1 with respect to <code>.arch</code>,
and existing practice within <span class="command">MILO</span> (the Linux ARC bootloader), the
numbered processor names (e.g. 21064) enable the processor-specific PALcode
instructions, while the &ldquo;electro-vlasic&rdquo; names (e.g. <code>ev4</code>) do not.
<p><a name="index-_0040code_007b_002dmdebug_007d-command-line-option_002c-Alpha-512"></a><a name="index-_0040code_007b_002dno_002dmdebug_007d-command-line-option_002c-Alpha-513"></a><br><dt><span class="option">-mdebug</span><dt><span class="option">-no-mdebug</span><dd>Enables or disables the generation of <code>.mdebug</code> encapsulation for
stabs directives and procedure descriptors. The default is to automatically
enable <code>.mdebug</code> when the first stabs directive is seen.
<p><a name="index-_0040code_007b_002drelax_007d-command-line-option_002c-Alpha-514"></a><br><dt><span class="option">-relax</span><dd>This option forces all relocations to be put into the object file, instead
of saving space and resolving some relocations at assembly time. Note that
this option does not propagate all symbol arithmetic into the object file,
because not all symbol arithmetic can be represented. However, the option
can still be useful in specific applications.
<p><a name="index-_0040code_007b_002dg_007d-command-line-option_002c-Alpha-515"></a><br><dt><span class="option">-g</span><dd>This option is used when the compiler generates debug information. When
<span class="command">gcc</span> is using <span class="command">mips-tfile</span> to generate debug
information for ECOFF, local labels must be passed through to the object
file. Otherwise this option has no effect.
<p><a name="index-_0040code_007b_002dG_007d-command-line-option_002c-Alpha-516"></a><br><dt><span class="option">-G</span><var>size</var><dd>A local common symbol larger than <var>size</var> is placed in <code>.bss</code>,
while smaller symbols are placed in <code>.sbss</code>.
<p><a name="index-_0040code_007b_002dF_007d-command-line-option_002c-Alpha-517"></a><a name="index-_0040code_007b_002d32addr_007d-command-line-option_002c-Alpha-518"></a><br><dt><span class="option">-F</span><dt><span class="option">-32addr</span><dd>These options are ignored for backward compatibility.
</dl>
<p><a name="index-Alpha-Syntax-519"></a>
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<h4 class="subsection">9.1.3 Syntax</h4>
<p>The assembler syntax closely follow the Alpha Reference Manual;
assembler directives and general syntax closely follow the OSF/1 and
OpenVMS syntax, with a few differences for ELF.
<ul class="menu">
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<hr><br>
</div>
<h5 class="subsubsection">9.1.3.1 Special Characters</h5>
<p><a name="index-line-comment-character_002c-Alpha-520"></a><a name="index-Alpha-line-comment-character-521"></a><span class="samp">#</span> is the line comment character.
<p><a name="index-line-separator_002c-Alpha-522"></a><a name="index-statement-separator_002c-Alpha-523"></a><a name="index-Alpha-line-separator-524"></a><span class="samp">;</span> can be used instead of a newline to separate statements.
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<h3 class="section">9.1 Alpha Dependent Features</h3>
<p><a name="index-Alpha-support-506"></a>
<ul class="menu">
<li><a accesskey="1" href="Alpha-Notes.html#Alpha-Notes">Alpha Notes</a>: Notes
<li><a accesskey="2" href="Alpha-Options.html#Alpha-Options">Alpha Options</a>: Options
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<h5 class="subsubsection">9.1.3.2 Register Names</h5>
<p><a name="index-Alpha-registers-525"></a><a name="index-register-names_002c-Alpha-526"></a>
The 32 integer registers are referred to as <span class="samp">$</span><var>n</var> or
<span class="samp">$r</span><var>n</var>. In addition, registers 15, 28, 29, and 30 may
be referred to by the symbols <span class="samp">$fp</span>, <span class="samp">$at</span>, <span class="samp">$gp</span>,
and <span class="samp">$sp</span> respectively.
<p>The 32 floating-point registers are referred to as <span class="samp">$f</span><var>n</var>.
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<h5 class="subsubsection">9.1.3.3 Relocations</h5>
<p><a name="index-Alpha-relocations-527"></a><a name="index-relocations_002c-Alpha-528"></a>
Some of these relocations are available for ECOFF, but mostly
only for ELF. They are modeled after the relocation format
introduced in Digital Unix 4.0, but there are additions.
<p>The format is <span class="samp">!</span><var>tag</var> or <span class="samp">!</span><var>tag</var><span class="samp">!</span><var>number</var>
where <var>tag</var> is the name of the relocation. In some cases
<var>number</var> is used to relate specific instructions.
<p>The relocation is placed at the end of the instruction like so:
<pre class="example"> ldah $0,a($29) !gprelhigh
lda $0,a($0) !gprellow
ldq $1,b($29) !literal!100
ldl $2,0($1) !lituse_base!100
</pre>
<dl>
<dt><code>!literal</code><dt><code>!literal!</code><var>N</var><dd>Used with an <code>ldq</code> instruction to load the address of a symbol
from the GOT.
<p>A sequence number <var>N</var> is optional, and if present is used to pair
<code>lituse</code> relocations with this <code>literal</code> relocation. The
<code>lituse</code> relocations are used by the linker to optimize the code
based on the final location of the symbol.
<p>Note that these optimizations are dependent on the data flow of the
program. Therefore, if <em>any</em> <code>lituse</code> is paired with a
<code>literal</code> relocation, then <em>all</em> uses of the register set by
the <code>literal</code> instruction must also be marked with <code>lituse</code>
relocations. This is because the original <code>literal</code> instruction
may be deleted or transformed into another instruction.
<p>Also note that there may be a one-to-many relationship between
<code>literal</code> and <code>lituse</code>, but not a many-to-one. That is, if
there are two code paths that load up the same address and feed the
value to a single use, then the use may not use a <code>lituse</code>
relocation.
<br><dt><code>!lituse_base!</code><var>N</var><dd>Used with any memory format instruction (e.g. <code>ldl</code>) to indicate
that the literal is used for an address load. The offset field of the
instruction must be zero. During relaxation, the code may be altered
to use a gp-relative load.
<br><dt><code>!lituse_jsr!</code><var>N</var><dd>Used with a register branch format instruction (e.g. <code>jsr</code>) to
indicate that the literal is used for a call. During relaxation, the
code may be altered to use a direct branch (e.g. <code>bsr</code>).
<br><dt><code>!lituse_jsrdirect!</code><var>N</var><dd>Similar to <code>lituse_jsr</code>, but also that this call cannot be vectored
through a PLT entry. This is useful for functions with special calling
conventions which do not allow the normal call-clobbered registers to be
clobbered.
<br><dt><code>!lituse_bytoff!</code><var>N</var><dd>Used with a byte mask instruction (e.g. <code>extbl</code>) to indicate
that only the low 3 bits of the address are relevant. During relaxation,
the code may be altered to use an immediate instead of a register shift.
<br><dt><code>!lituse_addr!</code><var>N</var><dd>Used with any other instruction to indicate that the original address
is in fact used, and the original <code>ldq</code> instruction may not be
altered or deleted. This is useful in conjunction with <code>lituse_jsr</code>
to test whether a weak symbol is defined.
<pre class="example"> ldq $27,foo($29) !literal!1
beq $27,is_undef !lituse_addr!1
jsr $26,($27),foo !lituse_jsr!1
</pre>
<br><dt><code>!lituse_tlsgd!</code><var>N</var><dd>Used with a register branch format instruction to indicate that the
literal is the call to <code>__tls_get_addr</code> used to compute the
address of the thread-local storage variable whose descriptor was
loaded with <code>!tlsgd!</code><var>N</var>.
<br><dt><code>!lituse_tlsldm!</code><var>N</var><dd>Used with a register branch format instruction to indicate that the
literal is the call to <code>__tls_get_addr</code> used to compute the
address of the base of the thread-local storage block for the current
module. The descriptor for the module must have been loaded with
<code>!tlsldm!</code><var>N</var>.
<br><dt><code>!gpdisp!</code><var>N</var><dd>Used with <code>ldah</code> and <code>lda</code> to load the GP from the current
address, a-la the <code>ldgp</code> macro. The source register for the
<code>ldah</code> instruction must contain the address of the <code>ldah</code>
instruction. There must be exactly one <code>lda</code> instruction paired
with the <code>ldah</code> instruction, though it may appear anywhere in
the instruction stream. The immediate operands must be zero.
<pre class="example"> bsr $26,foo
ldah $29,0($26) !gpdisp!1
lda $29,0($29) !gpdisp!1
</pre>
<br><dt><code>!gprelhigh</code><dd>Used with an <code>ldah</code> instruction to add the high 16 bits of a
32-bit displacement from the GP.
<br><dt><code>!gprellow</code><dd>Used with any memory format instruction to add the low 16 bits of a
32-bit displacement from the GP.
<br><dt><code>!gprel</code><dd>Used with any memory format instruction to add a 16-bit displacement
from the GP.
<br><dt><code>!samegp</code><dd>Used with any branch format instruction to skip the GP load at the
target address. The referenced symbol must have the same GP as the
source object file, and it must be declared to either not use <code>$27</code>
or perform a standard GP load in the first two instructions via the
<code>.prologue</code> directive.
<br><dt><code>!tlsgd</code><dt><code>!tlsgd!</code><var>N</var><dd>Used with an <code>lda</code> instruction to load the address of a TLS
descriptor for a symbol in the GOT.
<p>The sequence number <var>N</var> is optional, and if present it used to
pair the descriptor load with both the <code>literal</code> loading the
address of the <code>__tls_get_addr</code> function and the <code>lituse_tlsgd</code>
marking the call to that function.
<p>For proper relaxation, both the <code>tlsgd</code>, <code>literal</code> and
<code>lituse</code> relocations must be in the same extended basic block.
That is, the relocation with the lowest address must be executed
first at runtime.
<br><dt><code>!tlsldm</code><dt><code>!tlsldm!</code><var>N</var><dd>Used with an <code>lda</code> instruction to load the address of a TLS
descriptor for the current module in the GOT.
<p>Similar in other respects to <code>tlsgd</code>.
<br><dt><code>!gotdtprel</code><dd>Used with an <code>ldq</code> instruction to load the offset of the TLS
symbol within its module's thread-local storage block. Also known
as the dynamic thread pointer offset or dtp-relative offset.
<br><dt><code>!dtprelhi</code><dt><code>!dtprello</code><dt><code>!dtprel</code><dd>Like <code>gprel</code> relocations except they compute dtp-relative offsets.
<br><dt><code>!gottprel</code><dd>Used with an <code>ldq</code> instruction to load the offset of the TLS
symbol from the thread pointer. Also known as the tp-relative offset.
<br><dt><code>!tprelhi</code><dt><code>!tprello</code><dt><code>!tprel</code><dd>Like <code>gprel</code> relocations except they compute tp-relative offsets.
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<h3 class="section">7.77 <code>.altmacro</code></h3>
<p>Enable alternate macro mode, enabling:
<dl>
<dt><code>LOCAL </code><var>name</var><code> [ , ... ]</code><a name="index-LOCAL-_0040var_007bname_007d-_005b-_002c-_0040dots_007b_007d-_005d-399"></a><dd>One additional directive, <code>LOCAL</code>, is available. It is used to
generate a string replacement for each of the <var>name</var> arguments, and
replace any instances of <var>name</var> in each macro expansion. The
replacement string is unique in the assembly, and different for each
separate macro expansion. <code>LOCAL</code> allows you to write macros that
define symbols, without fear of conflict between separate macro expansions.
<br><dt><code>String delimiters</code><a name="index-String-delimiters-400"></a><dd>You can write strings delimited in these other ways besides
<code>"</code><var>string</var><code>"</code>:
<dl>
<dt><code>'</code><var>string</var><code>'</code><dd>You can delimit strings with single-quote characters.
<br><dt><code>&lt;</code><var>string</var><code>&gt;</code><dd>You can delimit strings with matching angle brackets.
</dl>
<br><dt><code>single-character string escape</code><a name="index-single_002dcharacter-string-escape-401"></a><dd>To include any single character literally in a string (even if the
character would otherwise have some special meaning), you can prefix the
character with <span class="samp">!</span> (an exclamation mark). For example, you can
write <span class="samp">&lt;4.3 !&gt; 5.4!!&gt;</span> to get the literal text <span class="samp">4.3 &gt; 5.4!</span>.
<br><dt><code>Expression results as strings</code><a name="index-Expression-results-as-strings-402"></a><dd>You can write <span class="samp">%</span><var>expr</var> to evaluate the expression <var>expr</var>
and use the result as a string.
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<h4 class="subsection">6.2.1 Arguments</h4>
<p><a name="index-expression-arguments-248"></a><a name="index-arguments-in-expressions-249"></a><a name="index-operands-in-expressions-250"></a><a name="index-arithmetic-operands-251"></a><dfn>Arguments</dfn> are symbols, numbers or subexpressions. In other
contexts arguments are sometimes called &ldquo;arithmetic operands&rdquo;. In
this manual, to avoid confusing them with the &ldquo;instruction operands&rdquo; of
the machine language, we use the term &ldquo;argument&rdquo; to refer to parts of
expressions only, reserving the word &ldquo;operand&rdquo; to refer only to machine
instruction operands.
<p>Symbols are evaluated to yield {<var>section</var> <var>NNN</var>} where
<var>section</var> is one of text, data, bss, absolute,
or undefined. <var>NNN</var> is a signed, 2's complement 32 bit
integer.
<p>Numbers are usually integers.
<p>A number can be a flonum or bignum. In this case, you are warned
that only the low order 32 bits are used, and <span class="command">as</span> pretends
these 32 bits are an integer. You may write integer-manipulating
instructions that act on exotic constants, compatible with other
assemblers.
<p><a name="index-subexpressions-252"></a>Subexpressions are a left parenthesis <span class="samp">(</span> followed by an integer
expression, followed by a right parenthesis <span class="samp">)</span>; or a prefix
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<h3 class="section">4.3 Assembler Internal Sections</h3>
<p><a name="index-internal-assembler-sections-200"></a><a name="index-sections-in-messages_002c-internal-201"></a>These sections are meant only for the internal use of <span class="command">as</span>. They
have no meaning at run-time. You do not really need to know about these
sections for most purposes; but they can be mentioned in <span class="command">as</span>
warning messages, so it might be helpful to have an idea of their
meanings to <span class="command">as</span>. These sections are used to permit the
value of every expression in your assembly language program to be a
section-relative address.
<a name="index-assembler-internal-logic-error-202"></a>
<dl><dt><b>ASSEMBLER-INTERNAL-LOGIC-ERROR!</b><dd>An internal assembler logic error has been found. This means there is a
bug in the assembler.
<p><a name="index-expr-_0028internal-section_0029-203"></a><br><dt><b>expr section</b><dd>The assembler stores complex expression internally as combinations of
symbols. When it needs to represent an expression as a symbol, it puts
it in the expr section.
<!-- FIXME item debug -->
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<h3 class="section">7.4 <code>.ascii "</code><var>string</var><code>"</code><small class="dots">...</small></h3>
<p><a name="index-_0040code_007bascii_007d-directive-277"></a><a name="index-string-literals-278"></a><code>.ascii</code> expects zero or more string literals (see <a href="Strings.html#Strings">Strings</a>)
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<h3 class="section">7.5 <code>.asciz "</code><var>string</var><code>"</code><small class="dots">...</small></h3>
<p><a name="index-_0040code_007basciz_007d-directive-279"></a><a name="index-zero_002dterminated-strings-280"></a><a name="index-null_002dterminated-strings-281"></a><code>.asciz</code> is just like <code>.ascii</code>, but each string is followed by
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<h4 class="subsection">9.5.2 Directives</h4>
<p><a name="index-BFIN-directives-664"></a><a name="index-directives_002c-BFIN-665"></a>
The following directives are provided for compatibility with the VDSP assembler.
<dl>
<dt><code>.byte2</code><dd>Initializes a four byte data object.
<br><dt><code>.byte4</code><dd>Initializes a two byte data object.
<br><dt><code>.db</code><dd>TBD
<br><dt><code>.dd</code><dd>TBD
<br><dt><code>.dw</code><dd>TBD
<br><dt><code>.var</code><dd>Define and initialize a 32 bit data object.
</dl>
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<h4 class="subsection">9.5.1 Syntax</h4>
<p><a name="index-BFIN-syntax-662"></a><a name="index-syntax_002c-BFIN-663"></a>
<dl>
<dt><code>Special Characters</code><dd>Assembler input is free format and may appear anywhere on the line.
One instruction may extend across multiple lines or more than one
instruction may appear on the same line. White space (space, tab,
comments or newline) may appear anywhere between tokens. A token must
not have embedded spaces. Tokens include numbers, register names,
keywords, user identifiers, and also some multicharacter special
symbols like "+=", "/*" or "||".
<br><dt><code>Instruction Delimiting</code><dd>A semicolon must terminate every instruction. Sometimes a complete
instruction will consist of more than one operation. There are two
cases where this occurs. The first is when two general operations
are combined. Normally a comma separates the different parts, as in
<pre class="smallexample"> a0= r3.h * r2.l, a1 = r3.l * r2.h ;
</pre>
<p>The second case occurs when a general instruction is combined with one
or two memory references for joint issue. The latter portions are
set off by a "||" token.
<pre class="smallexample"> a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
</pre>
<br><dt><code>Register Names</code><dd>
The assembler treats register names and instruction keywords in a case
insensitive manner. User identifiers are case sensitive. Thus, R3.l,
R3.L, r3.l and r3.L are all equivalent input to the assembler.
<p>Register names are reserved and may not be used as program identifiers.
<p>Some operations (such as "Move Register") require a register pair.
Register pairs are always data registers and are denoted using a colon,
eg., R3:2. The larger number must be written firsts. Note that the
hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
<p>Some instructions (such as &ndash;SP (Push Multiple)) require a group of
adjacent registers. Adjacent registers are denoted in the syntax by
the range enclosed in parentheses and separated by a colon, eg., (R7:3).
Again, the larger number appears first.
<p>Portions of a particular register may be individually specified. This
is written with a dot (".") following the register name and then a
letter denoting the desired portion. For 32-bit registers, ".H"
denotes the most significant ("High") portion. ".L" denotes the
least-significant portion. The subdivisions of the 40-bit registers
are described later.
<br><dt><code>Accumulators</code><dd>The set of 40-bit registers A1 and A0 that normally contain data that
is being manipulated. Each accumulator can be accessed in four ways.
<dl>
<dt><code>one 40-bit register</code><dd>The register will be referred to as A1 or A0.
<br><dt><code>one 32-bit register</code><dd>The registers are designated as A1.W or A0.W.
<br><dt><code>two 16-bit registers</code><dd>The registers are designated as A1.H, A1.L, A0.H or A0.L.
<br><dt><code>one 8-bit register</code><dd>The registers are designated as A1.X or A0.X for the bits that
extend beyond bit 31.
</dl>
<br><dt><code>Data Registers</code><dd>The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
normally contain data for manipulation. These are abbreviated as
D-register or Dreg. Data registers can be accessed as 32-bit registers
or as two independent 16-bit registers. The least significant 16 bits
of each register is called the "low" half and is designated with ".L"
following the register name. The most significant 16 bits are called
the "high" half and is designated with ".H" following the name.
<pre class="smallexample"> R7.L, r2.h, r4.L, R0.H
</pre>
<br><dt><code>Pointer Registers</code><dd>The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
normally contain byte addresses of data structures. These are
abbreviated as P-register or Preg.
<pre class="smallexample"> p2, p5, fp, sp
</pre>
<br><dt><code>Stack Pointer SP</code><dd>The stack pointer contains the 32-bit address of the last occupied
byte location in the stack. The stack grows by decrementing the
stack pointer.
<br><dt><code>Frame Pointer FP</code><dd>The frame pointer contains the 32-bit address of the previous frame
pointer in the stack. It is located at the top of a frame.
<br><dt><code>Loop Top</code><dd>LT0 and LT1. These registers contain the 32-bit address of the top of
a zero overhead loop.
<br><dt><code>Loop Count</code><dd>LC0 and LC1. These registers contain the 32-bit counter of the zero
overhead loop executions.
<br><dt><code>Loop Bottom</code><dd>LB0 and LB1. These registers contain the 32-bit address of the bottom
of a zero overhead loop.
<br><dt><code>Index Registers</code><dd>The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
addresses of data structures. Abbreviated I-register or Ireg.
<br><dt><code>Modify Registers</code><dd>The set of 32-bit registers (M0, M1, M2, M3) that normally contain
offset values that are added and subracted to one of the index
registers. Abbreviated as Mreg.
<br><dt><code>Length Registers</code><dd>The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
length in bytes of the circular buffer. Abbreviated as Lreg. Clear
the Lreg to disable circular addressing for the corresponding Ireg.
<br><dt><code>Base Registers</code><dd>The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
base address in bytes of the circular buffer. Abbreviated as Breg.
<br><dt><code>Floating Point</code><dd>The Blackfin family has no hardware floating point but the .float
directive generates ieee floating point numbers for use with software
floating point libraries.
<br><dt><code>Blackfin Opcodes</code><dd>For detailed information on the Blackfin machine instruction set, see
the Blackfin(r) Processor Instruction Set Reference.
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<h3 class="section">9.5 Blackfin Dependent Features</h3>
<p><a name="index-Blackfin-support-661"></a>
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<h3 class="section">7.6 <code>.balign[wl] </code><var>abs-expr</var><code>, </code><var>abs-expr</var><code>, </code><var>abs-expr</var></h3>
<p><a name="index-padding-the-location-counter-given-number-of-bytes-282"></a><a name="index-_0040code_007bbalign_007d-directive-283"></a>Pad the location counter (in the current subsection) to a particular
storage boundary. The first expression (which must be absolute) is the
alignment request in bytes. For example <span class="samp">.balign 8</span> advances
the location counter until it is a multiple of 8. If the location counter
is already a multiple of 8, no change is needed.
<p>The second expression (also absolute) gives the fill value to be stored in the
padding bytes. It (and the comma) may be omitted. If it is omitted, the
padding bytes are normally zero. However, on some systems, if the section is
marked as containing code and the fill value is omitted, the space is filled
with no-op instructions.
<p>The third expression is also absolute, and is also optional. If it is present,
it is the maximum number of bytes that should be skipped by this alignment
directive. If doing the alignment would require skipping more bytes than the
specified maximum, then the alignment is not done at all. You can omit the
fill value (the second argument) entirely by simply using two commas after the
required alignment; this can be useful if you want the alignment to be filled
with no-op instructions when appropriate.
<p><a name="index-_0040code_007bbalignw_007d-directive-284"></a><a name="index-_0040code_007bbalignl_007d-directive-285"></a>The <code>.balignw</code> and <code>.balignl</code> directives are variants of the
<code>.balign</code> directive. The <code>.balignw</code> directive treats the fill
pattern as a two byte word value. The <code>.balignl</code> directives treats the
fill pattern as a four byte longword value. For example, <code>.balignw
4,0x368d</code> will align to a multiple of 4. If it skips two bytes, they will be
filled in with the value 0x368d (the exact placement of the bytes depends upon
the endianness of the processor). If it skips 1 or 3 bytes, the fill value is
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<h5 class="subsubsection">3.6.2.2 Bignums</h5>
<p><a name="index-bignums-179"></a><a name="index-constants_002c-bignum-180"></a>A <dfn>bignum</dfn> has the same syntax and semantics as an integer
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<h3 class="section">10.1 Have You Found a Bug?</h3>
<p><a name="index-bug-criteria-1897"></a>
If you are not sure whether you have found a bug, here are some guidelines:
<a name="index-fatal-signal-1898"></a>
<a name="index-assembler-crash-1899"></a>
<a name="index-crash-of-assembler-1900"></a>
<ul><li>If the assembler gets a fatal signal, for any input whatever, that is a
<span class="command">as</span> bug. Reliable assemblers never crash.
<p><a name="index-error-on-valid-input-1901"></a><li>If <span class="command">as</span> produces an error message for valid input, that is a bug.
<p><a name="index-invalid-input-1902"></a><li>If <span class="command">as</span> does not produce an error message for invalid input, that
is a bug. However, you should note that your idea of &ldquo;invalid input&rdquo; might
be our idea of &ldquo;an extension&rdquo; or &ldquo;support for traditional practice&rdquo;.
<li>If you are an experienced user of assemblers, your suggestions for improvement
of <span class="command">as</span> are welcome in any case.
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<h3 class="section">10.2 How to Report Bugs</h3>
<p><a name="index-bug-reports-1903"></a><a name="index-assembler-bugs_002c-reporting-1904"></a>
A number of companies and individuals offer support for <span class="sc">gnu</span> products. If
you obtained <span class="command">as</span> from a support organization, we recommend you
contact that organization first.
<p>You can find contact information for many support companies and
individuals in the file <span class="file">etc/SERVICE</span> in the <span class="sc">gnu</span> Emacs
distribution.
<p>In any event, we also recommend that you send bug reports for <span class="command">as</span>
to <a href="http://www.sourceware.org/bugzilla/">http://www.sourceware.org/bugzilla/</a>.
<p>The fundamental principle of reporting bugs usefully is this:
<strong>report all the facts</strong>. If you are not sure whether to state a
fact or leave it out, state it!
<p>Often people omit facts because they think they know what causes the problem
and assume that some details do not matter. Thus, you might assume that the
name of a symbol you use in an example does not matter. Well, probably it does
not, but one cannot be sure. Perhaps the bug is a stray memory reference which
happens to fetch from the location where that name is stored in memory;
perhaps, if the name were different, the contents of that location would fool
the assembler into doing the right thing despite the bug. Play it safe and
give a specific, complete example. That is the easiest thing for you to do,
and the most helpful.
<p>Keep in mind that the purpose of a bug report is to enable us to fix the bug if
it is new to us. Therefore, always write your bug reports on the assumption
that the bug has not been reported previously.
<p>Sometimes people give a few sketchy facts and ask, &ldquo;Does this ring a
bell?&rdquo; This cannot help us fix a bug, so it is basically useless. We
respond by asking for enough details to enable us to investigate.
You might as well expedite matters by sending them to begin with.
<p>To enable us to fix the bug, you should include all these things:
<ul>
<li>The version of <span class="command">as</span>. <span class="command">as</span> announces it if you start
it with the <span class="samp">--version</span> argument.
<p>Without this, we will not know whether there is any point in looking for
the bug in the current version of <span class="command">as</span>.
<li>Any patches you may have applied to the <span class="command">as</span> source.
<li>The type of machine you are using, and the operating system name and
version number.
<li>What compiler (and its version) was used to compile <span class="command">as</span>&mdash;e.g.
&ldquo;<code>gcc-2.7</code>&rdquo;.
<li>The command arguments you gave the assembler to assemble your example and
observe the bug. To guarantee you will not omit something important, list them
all. A copy of the Makefile (or the output from make) is sufficient.
<p>If we were to try to guess the arguments, we would probably guess wrong
and then we might not encounter the bug.
<li>A complete input file that will reproduce the bug. If the bug is observed when
the assembler is invoked via a compiler, send the assembler source, not the
high level language source. Most compilers will produce the assembler source
when run with the <span class="samp">-S</span> option. If you are using <code>gcc</code>, use
the options <span class="samp">-v --save-temps</span>; this will save the assembler source in a
file with an extension of <span class="file">.s</span>, and also show you exactly how
<span class="command">as</span> is being run.
<li>A description of what behavior you observe that you believe is
incorrect. For example, &ldquo;It gets a fatal signal.&rdquo;
<p>Of course, if the bug is that <span class="command">as</span> gets a fatal signal, then we
will certainly notice it. But if the bug is incorrect output, we might not
notice unless it is glaringly wrong. You might as well not give us a chance to
make a mistake.
<p>Even if the problem you experience is a fatal signal, you should still say so
explicitly. Suppose something strange is going on, such as, your copy of
<span class="command">as</span> is out of sync, or you have encountered a bug in the C
library on your system. (This has happened!) Your copy might crash and ours
would not. If you told us to expect a crash, then when ours fails to crash, we
would know that the bug was not happening for us. If you had not told us to
expect a crash, then we would not be able to draw any conclusion from our
observations.
<li>If you wish to suggest changes to the <span class="command">as</span> source, send us context
diffs, as generated by <code>diff</code> with the <span class="samp">-u</span>, <span class="samp">-c</span>, or <span class="samp">-p</span>
option. Always send diffs from the old file to the new file. If you even
discuss something in the <span class="command">as</span> source, refer to it by context, not
by line number.
<p>The line numbers in our development sources will not match those in your
sources. Your line numbers would convey no useful information to us.
</ul>
<p>Here are some things that are not necessary:
<ul>
<li>A description of the envelope of the bug.
<p>Often people who encounter a bug spend a lot of time investigating
which changes to the input file will make the bug go away and which
changes will not affect it.
<p>This is often time consuming and not very useful, because the way we
will find the bug is by running a single example under the debugger
with breakpoints, not by pure deduction from a series of examples.
We recommend that you save your time for something else.
<p>Of course, if you can find a simpler example to report <em>instead</em>
of the original one, that is a convenience for us. Errors in the
output will be easier to spot, running under the debugger will take
less time, and so on.
<p>However, simplification is not vital; if you do not want to do this,
report the bug anyway and send us the entire test case you used.
<li>A patch for the bug.
<p>A patch for the bug does help us if it is a good one. But do not omit
the necessary information, such as the test case, on the assumption that
a patch is all we need. We might see problems with your patch and decide
to fix the problem another way, or we might not understand it at all.
<p>Sometimes with a program as complicated as <span class="command">as</span> it is very hard to
construct an example that will make the program follow a certain path through
the code. If you do not send us the example, we will not be able to construct
one, so we will not be able to verify that the bug is fixed.
<p>And if we cannot understand what bug you are trying to fix, or why your
patch should be an improvement, we will not install it. A test case will
help us to understand.
<li>A guess about what the bug is or what it depends on.
<p>Such guesses are usually wrong. Even we cannot guess right about such
things without first using the debugger to find the facts.
</ul>
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<h3 class="section">7.7 <code>.byte </code><var>expressions</var></h3>
<p><a name="index-_0040code_007bbyte_007d-directive-286"></a><a name="index-integers_002c-one-byte-287"></a><code>.byte</code> expects zero or more expressions, separated by commas.
Each expression is assembled into the next byte.
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<h3 class="section">7.9 <code>.cfi_startproc [simple]</code></h3>
<p><a name="index-_0040code_007bcfi_005fstartproc_007d-directive-290"></a><code>.cfi_startproc</code> is used at the beginning of each function that
should have an entry in <code>.eh_frame</code>. It initializes some internal
data structures. Don't forget to close the function by
<code>.cfi_endproc</code>.
<p>Unless <code>.cfi_startproc</code> is used along with parameter <code>simple</code>
it also emits some architecture dependent initial CFI instructions.
<h3 class="section">7.10 <code>.cfi_endproc</code></h3>
<p><a name="index-_0040code_007bcfi_005fendproc_007d-directive-291"></a><code>.cfi_endproc</code> is used at the end of a function where it closes its
unwind entry previously opened by
<code>.cfi_startproc</code>, and emits it to <code>.eh_frame</code>.
<h3 class="section">7.11 <code>.cfi_personality </code><var>encoding</var><code> [, </code><var>exp</var><code>]</code></h3>
<p><code>.cfi_personality</code> defines personality routine and its encoding.
<var>encoding</var> must be a constant determining how the personality
should be encoded. If it is 255 (<code>DW_EH_PE_omit</code>), second
argument is not present, otherwise second argument should be
a constant or a symbol name. When using indirect encodings,
the symbol provided should be the location where personality
can be loaded from, not the personality routine itself.
The default after <code>.cfi_startproc</code> is <code>.cfi_personality 0xff</code>,
no personality routine.
<h3 class="section">7.12 <code>.cfi_lsda </code><var>encoding</var><code> [, </code><var>exp</var><code>]</code></h3>
<p><code>.cfi_lsda</code> defines LSDA and its encoding.
<var>encoding</var> must be a constant determining how the LSDA
should be encoded. If it is 255 (<code>DW_EH_PE_omit</code>), second
argument is not present, otherwise second argument should be a constant
or a symbol name. The default after <code>.cfi_startproc</code> is <code>.cfi_lsda 0xff</code>,
no LSDA.
<h3 class="section">7.13 <code>.cfi_def_cfa </code><var>register</var><code>, </code><var>offset</var></h3>
<p><code>.cfi_def_cfa</code> defines a rule for computing CFA as: <i>take
address from </i><var>register</var><i> and add </i><var>offset</var><i> to it</i>.
<h3 class="section">7.14 <code>.cfi_def_cfa_register </code><var>register</var></h3>
<p><code>.cfi_def_cfa_register</code> modifies a rule for computing CFA. From
now on <var>register</var> will be used instead of the old one. Offset
remains the same.
<h3 class="section">7.15 <code>.cfi_def_cfa_offset </code><var>offset</var></h3>
<p><code>.cfi_def_cfa_offset</code> modifies a rule for computing CFA. Register
remains the same, but <var>offset</var> is new. Note that it is the
absolute offset that will be added to a defined register to compute
CFA address.
<h3 class="section">7.16 <code>.cfi_adjust_cfa_offset </code><var>offset</var></h3>
<p>Same as <code>.cfi_def_cfa_offset</code> but <var>offset</var> is a relative
value that is added/substracted from the previous offset.
<h3 class="section">7.17 <code>.cfi_offset </code><var>register</var><code>, </code><var>offset</var></h3>
<p>Previous value of <var>register</var> is saved at offset <var>offset</var> from
CFA.
<h3 class="section">7.18 <code>.cfi_rel_offset </code><var>register</var><code>, </code><var>offset</var></h3>
<p>Previous value of <var>register</var> is saved at offset <var>offset</var> from
the current CFA register. This is transformed to <code>.cfi_offset</code>
using the known displacement of the CFA register from the CFA.
This is often easier to use, because the number will match the
code it's annotating.
<h3 class="section">7.19 <code>.cfi_register </code><var>register1</var><code>, </code><var>register2</var></h3>
<p>Previous value of <var>register1</var> is saved in register <var>register2</var>.
<h3 class="section">7.20 <code>.cfi_restore </code><var>register</var></h3>
<p><code>.cfi_restore</code> says that the rule for <var>register</var> is now the
same as it was at the beginning of the function, after all initial
instruction added by <code>.cfi_startproc</code> were executed.
<h3 class="section">7.21 <code>.cfi_undefined </code><var>register</var></h3>
<p>From now on the previous value of <var>register</var> can't be restored anymore.
<h3 class="section">7.22 <code>.cfi_same_value </code><var>register</var></h3>
<p>Current value of <var>register</var> is the same like in the previous frame,
i.e. no restoration needed.
<h3 class="section">7.23 <code>.cfi_remember_state</code>,</h3>
<p>First save all current rules for all registers by <code>.cfi_remember_state</code>,
then totally screw them up by subsequent <code>.cfi_*</code> directives and when
everything is hopelessly bad, use <code>.cfi_restore_state</code> to restore
the previous saved state.
<h3 class="section">7.24 <code>.cfi_return_column </code><var>register</var></h3>
<p>Change return column <var>register</var>, i.e. the return address is either
directly in <var>register</var> or can be accessed by rules for <var>register</var>.
<h3 class="section">7.25 <code>.cfi_signal_frame</code></h3>
<p>Mark current function as signal trampoline.
<h3 class="section">7.26 <code>.cfi_window_save</code></h3>
<p>SPARC register window has been saved.
<h3 class="section">7.27 <code>.cfi_escape</code> <var>expression</var>[, <small class="dots">...</small>]</h3>
<p>Allows the user to add arbitrary bytes to the unwind info. One
might use this to add OS-specific CFI opcodes, or generic CFI
opcodes that GAS does not yet support.
<h3 class="section">7.28 <code>.cfi_val_encoded_addr </code><var>register</var><code>, </code><var>encoding</var><code>, </code><var>label</var></h3>
<p>The current value of <var>register</var> is <var>label</var>. The value of <var>label</var>
will be encoded in the output file according to <var>encoding</var>; see the
description of <code>.cfi_personality</code> for details on this encoding.
<p>The usefulness of equating a register to a fixed label is probably
limited to the return address register. Here, it can be useful to
mark a code segment that has only one return address which is reached
by a direct branch and no copy of the return address exists in memory
or another register.
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<h4 class="subsection">5.5.4 Symbol Attributes for COFF</h4>
<p><a name="index-COFF-symbol-attributes-235"></a><a name="index-symbol-attributes_002c-COFF-236"></a>
The COFF format supports a multitude of auxiliary symbol attributes;
like the primary symbol attributes, they are set between <code>.def</code> and
<code>.endef</code> directives.
<h5 class="subsubsection">5.5.4.1 Primary Attributes</h5>
<p><a name="index-primary-attributes_002c-COFF-symbols-237"></a>The symbol name is set with <code>.def</code>; the value and type,
respectively, with <code>.val</code> and <code>.type</code>.
<h5 class="subsubsection">5.5.4.2 Auxiliary Attributes</h5>
<p><a name="index-auxiliary-attributes_002c-COFF-symbols-238"></a>The <span class="command">as</span> directives <code>.dim</code>, <code>.line</code>, <code>.scl</code>,
<code>.size</code>, <code>.tag</code>, and <code>.weak</code> can generate auxiliary symbol
table information for COFF.
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<h4 class="subsection">9.6.1 CR16 Operand Qualifiers</h4>
<p><a name="index-CR16-Operand-Qualifiers-667"></a>
The National Semiconductor CR16 target of <code>as</code> has a few machine dependent operand qualifiers.
<p>Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The <code>@</code> is required. CR16 architecture uses one of the following expression qualifiers:
<dl>
<dt><code>s</code><dd>- <code>Specifies expression operand type as small</code>
<br><dt><code>m</code><dd>- <code>Specifies expression operand type as medium</code>
<br><dt><code>l</code><dd>- <code>Specifies expression operand type as large</code>
<br><dt><code>c</code><dd>- <code>Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.</code>
</dl>
<p>CR16 target operand qualifiers and its size (in bits):
<dl>
<dt><span class="samp">Immediate Operand</span><dd>- s &mdash;&ndash; 4 bits
<br><dt><dd>- m &mdash;&ndash; 16 bits, for movb and movw instructions.
<br><dt><dd>- m &mdash;&ndash; 20 bits, movd instructions.
<br><dt><dd>- l &mdash;&ndash; 32 bits
<br><dt><span class="samp">Absolute Operand</span><dd>- s &mdash;&ndash; Illegal specifier for this operand.
<br><dt><dd>- m &mdash;&ndash; 20 bits, movd instructions.
<br><dt><span class="samp">Displacement Operand</span><dd>- s &mdash;&ndash; 8 bits
<br><dt><dd>- m &mdash;&ndash; 16 bits
<br><dt><dd>- l &mdash;&ndash; 24 bits
</dl>
<p>For example:
<pre class="example"> 1 <code>movw $_myfun@c,r1</code>
This loads the address of _myfun, shifted right by 1, into r1.
2 <code>movd $_myfun@c,(r2,r1)</code>
This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
3 <code>_myfun_ptr:</code>
<code>.long _myfun@c</code>
<code>loadd _myfun_ptr, (r1,r0)</code>
<code>jal (r1,r0)</code>
This .long directive, the address of _myfunc, shifted right by 1 at link time.
</pre>
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<h3 class="section">9.6 CR16 Dependent Features</h3>
<p><a name="index-CR16-support-666"></a>
<ul class="menu">
<li><a accesskey="1" href="CR16-Operand-Qualifiers.html#CR16-Operand-Qualifiers">CR16 Operand Qualifiers</a>: CR16 Machine Operand Qualifiers
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<h5 class="subsubsection">9.7.4.1 Special Characters</h5>
<p><a name="index-line-comment-characters_002c-CRIS-699"></a><a name="index-CRIS-line-comment-characters-700"></a>
The character <span class="samp">#</span> is a line comment character. It starts a
comment if and only if it is placed at the beginning of a line.
<p>A <span class="samp">;</span> character starts a comment anywhere on the line,
causing all characters up to the end of the line to be ignored.
<p>A <span class="samp">@</span> character is handled as a line separator equivalent
to a logical new-line character (except in a comment), so
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<h3 class="section">9.7 CRIS Dependent Features</h3>
<p><a name="index-CRIS-support-668"></a>
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<li><a accesskey="1" href="CRIS_002dOpts.html#CRIS_002dOpts">CRIS-Opts</a>: Command-line Options
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<h4 class="subsection">9.7.2 Instruction expansion</h4>
<p><a name="index-instruction-expansion_002c-CRIS-693"></a><a name="index-CRIS-instruction-expansion-694"></a><code>as</code> will silently choose an instruction that fits
the operand size for <span class="samp">[register+constant]</span> operands. For
example, the offset <code>127</code> in <code>move.d [r3+127],r4</code> fits
in an instruction using a signed-byte offset. Similarly,
<code>move.d [r2+32767],r1</code> will generate an instruction using a
16-bit offset. For symbolic expressions and constants that do
not fit in 16 bits including the sign bit, a 32-bit offset is
generated.
<p>For branches, <code>as</code> will expand from a 16-bit branch
instruction into a sequence of instructions that can reach a
full 32-bit address. Since this does not correspond to a single
instruction, such expansions can optionally be warned about.
See <a href="CRIS_002dOpts.html#CRIS_002dOpts">CRIS-Opts</a>.
<p>If the operand is found to fit the range, a <code>lapc</code> mnemonic
will translate to a <code>lapcq</code> instruction. Use <code>lapc.d</code>
to force the 32-bit <code>lapc</code> instruction.
<p>Similarly, the <code>addo</code> mnemonic will translate to the
shortest fitting instruction of <code>addoq</code>, <code>addo.w</code> and
<code>addo.d</code>, when used with a operand that is a constant known
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<h4 class="subsection">9.7.1 Command-line Options</h4>
<p><a name="index-options_002c-CRIS-669"></a><a name="index-CRIS-options-670"></a>The CRIS version of <code>as</code> has these
machine-dependent command-line options.
<p><a name="index-_0040option_007b_002d_002demulation_003dcriself_007d-command-line-option_002c-CRIS-671"></a><a name="index-_0040option_007b_002d_002demulation_003dcrisaout_007d-command-line-option_002c-CRIS-672"></a><a name="index-CRIS-_0040option_007b_002d_002demulation_003dcriself_007d-command-line-option-673"></a><a name="index-CRIS-_0040option_007b_002d_002demulation_003dcrisaout_007d-command-line-option-674"></a>
The format of the generated object files can be either ELF or
a.out, specified by the command-line options
<span class="option">--emulation=crisaout</span> and <span class="option">--emulation=criself</span>.
The default is ELF (criself), unless <code>as</code> has been
configured specifically for a.out by using the configuration
name <code>cris-axis-aout</code>.
<p><a name="index-_0040option_007b_002d_002dunderscore_007d-command-line-option_002c-CRIS-675"></a><a name="index-_0040option_007b_002d_002dno_002dunderscore_007d-command-line-option_002c-CRIS-676"></a><a name="index-CRIS-_0040option_007b_002d_002dunderscore_007d-command-line-option-677"></a><a name="index-CRIS-_0040option_007b_002d_002dno_002dunderscore_007d-command-line-option-678"></a>There are two different link-incompatible ELF object file
variants for CRIS, for use in environments where symbols are
expected to be prefixed by a leading <span class="samp">_</span> character and for
environments without such a symbol prefix. The variant used for
GNU/Linux port has no symbol prefix. Which variant to produce
is specified by either of the options <span class="option">--underscore</span> and
<span class="option">--no-underscore</span>. The default is <span class="option">--underscore</span>.
Since symbols in CRIS a.out objects are expected to have a
<span class="samp">_</span> prefix, specifying <span class="option">--no-underscore</span> when
generating a.out objects is an error. Besides the object format
difference, the effect of this option is to parse register names
differently (see <a href="crisnous.html#crisnous">crisnous</a>). The <span class="option">--no-underscore</span>
option makes a <span class="samp">$</span> register prefix mandatory.
<p><a name="index-_0040option_007b_002d_002dpic_007d-command-line-option_002c-CRIS-679"></a><a name="index-CRIS-_0040option_007b_002d_002dpic_007d-command-line-option-680"></a><a name="index-Position_002dindependent-code_002c-CRIS-681"></a><a name="index-CRIS-position_002dindependent-code-682"></a>The option <span class="option">--pic</span> must be passed to <code>as</code> in
order to recognize the symbol syntax used for ELF (SVR4 PIC)
position-independent-code (see <a href="crispic.html#crispic">crispic</a>). This will also
affect expansion of instructions. The expansion with
<span class="option">--pic</span> will use PC-relative rather than (slightly
faster) absolute addresses in those expansions.
<p><a name="index-_0040option_007b_002d_002dmarch_003d_0040var_007barchitecture_007d_007d-command-line-option_002c-CRIS-683"></a><a name="index-CRIS-_0040option_007b_002d_002dmarch_003d_0040var_007barchitecture_007d_007d-command-line-option-684"></a><a name="index-Architecture-variant-option_002c-CRIS-685"></a><a name="index-CRIS-architecture-variant-option-686"></a>The option <span class="option">--march=</span><var>architecture</var>
<a name="march_002doption"></a>specifies the recognized instruction set
and recognized register names. It also controls the
architecture type of the object file. Valid values for
<var>architecture</var> are:
<dl>
<dt><code>v0_v10</code><dd>All instructions and register names for any architecture variant
in the set v0<small class="dots">...</small>v10 are recognized. This is the
default if the target is configured as cris-*.
<br><dt><code>v10</code><dd>Only instructions and register names for CRIS v10 (as found in
ETRAX 100 LX) are recognized. This is the default if the target
is configured as crisv10-*.
<br><dt><code>v32</code><dd>Only instructions and register names for CRIS v32 (code name
Guinness) are recognized. This is the default if the target is
configured as crisv32-*. This value implies
<span class="option">--no-mul-bug-abort</span>. (A subsequent
<span class="option">--mul-bug-abort</span> will turn it back on.)
<br><dt><code>common_v10_v32</code><dd>Only instructions with register names and addressing modes with
opcodes common to the v10 and v32 are recognized.
</dl>
<p><a name="index-_0040option_007b_002dN_007d-command-line-option_002c-CRIS-687"></a><a name="index-CRIS-_0040option_007b_002dN_007d-command-line-option-688"></a>When <span class="option">-N</span> is specified, <code>as</code> will emit a
warning when a 16-bit branch instruction is expanded into a
32-bit multiple-instruction construct (see <a href="CRIS_002dExpand.html#CRIS_002dExpand">CRIS-Expand</a>).
<p><a name="index-_0040option_007b_002d_002dno_002dmul_002dbug_002dabort_007d-command-line-option_002c-CRIS-689"></a><a name="index-_0040option_007b_002d_002dmul_002dbug_002dabort_007d-command-line-option_002c-CRIS-690"></a><a name="index-CRIS-_0040option_007b_002d_002dno_002dmul_002dbug_002dabort_007d-command-line-option-691"></a><a name="index-CRIS-_0040option_007b_002d_002dmul_002dbug_002dabort_007d-command-line-option-692"></a>
Some versions of the CRIS v10, for example in the Etrax 100 LX,
contain a bug that causes destabilizing memory accesses when a
multiply instruction is executed with certain values in the
first operand just before a cache-miss. When the
<span class="option">--mul-bug-abort</span> command line option is active (the
default value), <code>as</code> will refuse to assemble a file
containing a multiply instruction at a dangerous offset, one
that could be the last on a cache-line, or is in a section with
insufficient alignment. This placement checking does not catch
any case where the multiply instruction is dangerously placed
because it is located in a delay-slot. The
<span class="option">--mul-bug-abort</span> command line option turns off the
checking.
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<h5 class="subsubsection">9.7.4.2 Symbols in position-independent code</h5>
<p><a name="index-Symbols-in-position_002dindependent-code_002c-CRIS-701"></a><a name="index-CRIS-symbols-in-position_002dindependent-code-702"></a><a name="index-Position_002dindependent-code_002c-symbols-in_002c-CRIS-703"></a>
When generating <a name="crispic"></a>position-independent code (SVR4
PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu
shared libraries, symbol
suffixes are used to specify what kind of run-time symbol lookup
will be used, expressed in the object as different
<em>relocation types</em>. Usually, all absolute symbol values
must be located in a table, the <em>global offset table</em>,
leaving the code position-independent; independent of values of
global symbols and independent of the address of the code. The
suffix modifies the value of the symbol, into for example an
index into the global offset table where the real symbol value
is entered, or a PC-relative value, or a value relative to the
start of the global offset table. All symbol suffixes start
with the character <span class="samp">:</span> (omitted in the list below). Every
symbol use in code or a read-only section must therefore have a
PIC suffix to enable a useful shared library to be created.
Usually, these constructs must not be used with an additive
constant offset as is usually allowed, i.e. no 4 as in
<code>symbol + 4</code> is allowed. This restriction is checked at
link-time, not at assembly-time.
<dl>
<dt><code>GOT</code><dd>
Attaching this suffix to a symbol in an instruction causes the
symbol to be entered into the global offset table. The value is
a 32-bit index for that symbol into the global offset table.
The name of the corresponding relocation is
<span class="samp">R_CRIS_32_GOT</span>. Example: <code>move.d
[$r0+extsym:GOT],$r9</code>
<br><dt><code>GOT16</code><dd>
Same as for <span class="samp">GOT</span>, but the value is a 16-bit index into the
global offset table. The corresponding relocation is
<span class="samp">R_CRIS_16_GOT</span>. Example: <code>move.d
[$r0+asymbol:GOT16],$r10</code>
<br><dt><code>PLT</code><dd>
This suffix is used for function symbols. It causes a
<em>procedure linkage table</em>, an array of code stubs, to be
created at the time the shared object is created or linked
against, together with a global offset table entry. The value
is a pc-relative offset to the corresponding stub code in the
procedure linkage table. This arrangement causes the run-time
symbol resolver to be called to look up and set the value of the
symbol the first time the function is called (at latest;
depending environment variables). It is only safe to leave the
symbol unresolved this way if all references are function calls.
The name of the relocation is <span class="samp">R_CRIS_32_PLT_PCREL</span>.
Example: <code>add.d fnname:PLT,$pc</code>
<br><dt><code>PLTG</code><dd>
Like PLT, but the value is relative to the beginning of the
global offset table. The relocation is
<span class="samp">R_CRIS_32_PLT_GOTREL</span>. Example: <code>move.d
fnname:PLTG,$r3</code>
<br><dt><code>GOTPLT</code><dd>
Similar to <span class="samp">PLT</span>, but the value of the symbol is a 32-bit
index into the global offset table. This is somewhat of a mix
between the effect of the <span class="samp">GOT</span> and the <span class="samp">PLT</span> suffix;
the difference to <span class="samp">GOT</span> is that there will be a procedure
linkage table entry created, and that the symbol is assumed to
be a function entry and will be resolved by the run-time
resolver as with <span class="samp">PLT</span>. The relocation is
<span class="samp">R_CRIS_32_GOTPLT</span>. Example: <code>jsr
[$r0+fnname:GOTPLT]</code>
<br><dt><code>GOTPLT16</code><dd>
A variant of <span class="samp">GOTPLT</span> giving a 16-bit value. Its
relocation name is <span class="samp">R_CRIS_16_GOTPLT</span>. Example: <code>jsr
[$r0+fnname:GOTPLT16]</code>
<br><dt><code>GOTOFF</code><dd>
This suffix must only be attached to a local symbol, but may be
used in an expression adding an offset. The value is the
address of the symbol relative to the start of the global offset
table. The relocation name is <span class="samp">R_CRIS_32_GOTREL</span>.
Example: <code>move.d [$r0+localsym:GOTOFF],r3</code>
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Up:&nbsp;<a rel="up" accesskey="u" href="CRIS_002dSyntax.html#CRIS_002dSyntax">CRIS-Syntax</a>
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<h5 class="subsubsection">9.7.4.4 Assembler Directives</h5>
<p><a name="index-assembler-directives_002c-CRIS-706"></a><a name="index-pseudo_002dops_002c-CRIS-707"></a><a name="index-CRIS-assembler-directives-708"></a><a name="index-CRIS-pseudo_002dops-709"></a>
There are a few CRIS-specific pseudo-directives in addition to
the generic ones. See <a href="Pseudo-Ops.html#Pseudo-Ops">Pseudo Ops</a>. Constants emitted by
pseudo-directives are in little-endian order for CRIS. There is
no support for floating-point-specific directives for CRIS.
<dl>
<dt><code>.dword EXPRESSIONS</code><dd><a name="index-assembler-directive-_002edword_002c-CRIS-710"></a><a name="index-pseudo_002dop-_002edword_002c-CRIS-711"></a><a name="index-CRIS-assembler-directive-_002edword-712"></a><a name="index-CRIS-pseudo_002dop-_002edword-713"></a>
The <code>.dword</code> directive is a synonym for <code>.int</code>,
expecting zero or more EXPRESSIONS, separated by commas. For
each expression, a 32-bit little-endian constant is emitted.
<br><dt><code>.syntax ARGUMENT</code><dd><a name="index-assembler-directive-_002esyntax_002c-CRIS-714"></a><a name="index-pseudo_002dop-_002esyntax_002c-CRIS-715"></a><a name="index-CRIS-assembler-directive-_002esyntax-716"></a><a name="index-CRIS-pseudo_002dop-_002esyntax-717"></a>The <code>.syntax</code> directive takes as <var>ARGUMENT</var> one of the
following case-sensitive choices.
<dl>
<dt><code>no_register_prefix</code><dd>
The <code>.syntax no_register_prefix</code> <a name="crisnous"></a>directive
makes a <span class="samp">$</span> character prefix on all registers optional. It
overrides a previous setting, including the corresponding effect
of the option <span class="option">--no-underscore</span>. If this directive is
used when ordinary symbols do not have a <span class="samp">_</span> character
prefix, care must be taken to avoid ambiguities whether an
operand is a register or a symbol; using symbols with names the
same as general or special registers then invoke undefined
behavior.
<br><dt><code>register_prefix</code><dd>
This directive makes a <span class="samp">$</span> character prefix on all
registers mandatory. It overrides a previous setting, including
the corresponding effect of the option <span class="option">--underscore</span>.
<br><dt><code>leading_underscore</code><dd>
This is an assertion directive, emitting an error if the
<span class="option">--no-underscore</span> option is in effect.
<br><dt><code>no_leading_underscore</code><dd>
This is the opposite of the <code>.syntax leading_underscore</code>
directive and emits an error if the option <span class="option">--underscore</span>
is in effect.
</dl>
<br><dt><code>.arch ARGUMENT</code><dd><a name="index-assembler-directive-_002earch_002c-CRIS-718"></a><a name="index-pseudo_002dop-_002earch_002c-CRIS-719"></a><a name="index-CRIS-assembler-directive-_002earch-720"></a><a name="index-CRIS-pseudo_002dop-_002earch-721"></a>This is an assertion directive, giving an error if the specified
<var>ARGUMENT</var> is not the same as the specified or default value
for the <span class="option">--march=</span><var>architecture</var> option
(see <a href="march_002doption.html#march_002doption">march-option</a>).
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<h5 class="subsubsection">9.7.4.3 Register names</h5>
<p><a name="index-register-names_002c-CRIS-704"></a><a name="index-CRIS-register-names-705"></a>
A <span class="samp">$</span> character may always prefix a general or special
register name in an instruction operand but is mandatory when
the option <span class="option">--no-underscore</span> is specified or when the
<code>.syntax register_prefix</code> directive is in effect
(see <a href="crisnous.html#crisnous">crisnous</a>). Register names are case-insensitive.
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<a name="CRIS_002dSymbols"></a>Next:&nbsp;<a rel="next" accesskey="n" href="CRIS_002dSyntax.html#CRIS_002dSyntax">CRIS-Syntax</a>,
Previous:&nbsp;<a rel="previous" accesskey="p" href="CRIS_002dExpand.html#CRIS_002dExpand">CRIS-Expand</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="CRIS_002dDependent.html#CRIS_002dDependent">CRIS-Dependent</a>
<hr><br>
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<h4 class="subsection">9.7.3 Symbols</h4>
<p><a name="index-Symbols_002c-built_002din_002c-CRIS-695"></a><a name="index-Symbols_002c-CRIS_002c-built_002din-696"></a><a name="index-CRIS-built_002din-symbols-697"></a><a name="index-Built_002din-symbols_002c-CRIS-698"></a>
Some symbols are defined by the assembler. They're intended to
be used in conditional assembly, for example:
<pre class="smallexample"> .if ..asm.arch.cris.v32
<var>code for CRIS v32</var>
.elseif ..asm.arch.cris.common_v10_v32
<var>code common to CRIS v32 and CRIS v10</var>
.elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
<var>code for v10</var>
.else
.error "Code needs to be added here."
.endif
</pre>
<p>These symbols are defined in the assembler, reflecting
command-line options, either when specified or the default.
They are always defined, to 0 or 1.
<dl>
<dt><code>..asm.arch.cris.any_v0_v10</code><dd>This symbol is non-zero when <span class="option">--march=v0_v10</span> is specified
or the default.
<br><dt><code>..asm.arch.cris.common_v10_v32</code><dd>Set according to the option <span class="option">--march=common_v10_v32</span>.
<br><dt><code>..asm.arch.cris.v10</code><dd>Reflects the option <span class="option">--march=v10</span>.
<br><dt><code>..asm.arch.cris.v32</code><dd>Corresponds to <span class="option">--march=v10</span>.
</dl>
<p>Speaking of symbols, when a symbol is used in code, it can have
a suffix modifying its value for use in position-independent
code. See <a href="CRIS_002dPic.html#CRIS_002dPic">CRIS-Pic</a>.
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<h4 class="subsection">9.7.4 Syntax</h4>
<p>There are different aspects of the CRIS assembly syntax.
<ul class="menu">
<li><a accesskey="1" href="CRIS_002dChars.html#CRIS_002dChars">CRIS-Chars</a>: Special Characters
<li><a accesskey="2" href="CRIS_002dPic.html#CRIS_002dPic">CRIS-Pic</a>: Position-Independent Code Symbols
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<h4 class="subsection">3.6.1 Character Constants</h4>
<p><a name="index-character-constants-140"></a><a name="index-constants_002c-character-141"></a>There are two kinds of character constants. A <dfn>character</dfn> stands
for one character in one byte and its value may be used in
numeric expressions. String constants (properly called string
<em>literals</em>) are potentially many bytes and their values may not be
used in arithmetic expressions.
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<h5 class="subsubsection">3.6.1.2 Characters</h5>
<p><a name="index-single-character-constant-164"></a><a name="index-character_002c-single-165"></a><a name="index-constant_002c-single-character-166"></a>A single character may be written as a single quote immediately
followed by that character. The same escapes apply to characters as
to strings. So if you want to write the character backslash, you
must write <kbd>'\\</kbd> where the first <code>\</code> escapes the second
<code>\</code>. As you can see, the quote is an acute accent, not a
grave accent. A newline
immediately following an acute accent is taken as a literal character
and does not count as the end of a statement. The value of a character
constant in a numeric expression is the machine's byte-wide code for
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<h3 class="section">7.8 <code>.comm </code><var>symbol</var><code> , </code><var>length</var> </h3>
<p><a name="index-_0040code_007bcomm_007d-directive-288"></a><a name="index-symbol_002c-common-289"></a><code>.comm</code> declares a common symbol named <var>symbol</var>. When linking, a
common symbol in one object file may be merged with a defined or common symbol
of the same name in another object file. If <code>ld</code> does not see a
definition for the symbol&ndash;just one or more common symbols&ndash;then it will
allocate <var>length</var> bytes of uninitialized memory. <var>length</var> must be an
absolute expression. If <code>ld</code> sees multiple common symbols with
the same name, and they do not all have the same size, it will allocate space
using the largest size.
<p>When using ELF, the <code>.comm</code> directive takes an optional third argument.
This is the desired alignment of the symbol, specified as a byte boundary (for
example, an alignment of 16 means that the least significant 4 bits of the
address should be zero). The alignment must be an absolute expression, and it
must be a power of two. If <code>ld</code> allocates uninitialized memory
for the common symbol, it will use the alignment when placing the symbol. If
no alignment is specified, <span class="command">as</span> will set the alignment to the
largest power of two less than or equal to the size of the symbol, up to a
maximum of 16.
<p>The syntax for <code>.comm</code> differs slightly on the HPPA. The syntax is
<var>symbol</var><span class="samp"> .comm, </span><var>length</var>; <var>symbol</var> is optional.
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<h3 class="section">1.4 Command Line</h3>
<p><a name="index-command-line-conventions-25"></a>
After the program name <span class="command">as</span>, the command line may contain
options and file names. Options may appear in any order, and may be
before, after, or between file names. The order of file names is
significant.
<p><a name="index-standard-input_002c-as-input-file-26"></a><a name="index-_002d_002d-27"></a><span class="file">--</span> (two hyphens) by itself names the standard input file
explicitly, as one of the files for <span class="command">as</span> to assemble.
<p><a name="index-options_002c-command-line-28"></a>Except for <span class="samp">--</span> any command line argument that begins with a
hyphen (<span class="samp">-</span>) is an option. Each option changes the behavior of
<span class="command">as</span>. No option changes the way another option works. An
option is a <span class="samp">-</span> followed by one or more letters; the case of
the letter is important. All options are optional.
<p>Some options expect exactly one file name to follow them. The file
name may either immediately follow the option's letter (compatible
with older assemblers) or it may be the next command argument (<span class="sc">gnu</span>
standard). These two command lines are equivalent:
<pre class="smallexample"> as -o my-object-file.o mumble.s
as -omy-object-file.o mumble.s
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<h3 class="section">3.3 Comments</h3>
<p><a name="index-comments-123"></a>There are two ways of rendering comments to <span class="command">as</span>. In both
cases the comment is equivalent to one space.
<p>Anything from <span class="samp">/*</span> through the next <span class="samp">*/</span> is a comment.
This means you may not nest these comments.
<pre class="smallexample"> /*
The only way to include a newline ('\n') in a comment
is to use this sort of comment.
*/
/* This sort of comment does not nest. */
</pre>
<p><a name="index-line-comment-character-124"></a>Anything from the <dfn>line comment</dfn> character to the next newline
is considered a comment and is ignored. The line comment character is
<span class="samp">;</span> on the ARC;
<span class="samp">@</span> on the ARM;
<span class="samp">;</span> for the H8/300 family;
<span class="samp">;</span> for the HPPA;
<span class="samp">#</span> on the i386 and x86-64;
<span class="samp">#</span> on the i960;
<span class="samp">;</span> for the PDP-11;
<span class="samp">;</span> for picoJava;
<span class="samp">#</span> for Motorola PowerPC;
<span class="samp">!</span> for the Renesas / SuperH SH;
<span class="samp">!</span> on the SPARC;
<span class="samp">#</span> on the ip2k;
<span class="samp">#</span> on the m32c;
<span class="samp">#</span> on the m32r;
<span class="samp">|</span> on the 680x0;
<span class="samp">#</span> on the 68HC11 and 68HC12;
<span class="samp">#</span> on the Vax;
<span class="samp">;</span> for the Z80;
<span class="samp">!</span> for the Z8000;
<span class="samp">#</span> on the V850;
<span class="samp">#</span> for Xtensa systems;
see <a href="Machine-Dependencies.html#Machine-Dependencies">Machine Dependencies</a>.
<!-- FIXME What about i860? -->
<p>On some machines there are two different line comment characters. One
character only begins a comment if it is the first non-whitespace character on
a line, while the other always begins a comment.
<p>The V850 assembler also supports a double dash as starting a comment that
extends to the end of the line.
<p><span class="samp">--</span>;
<p><a name="index-_0023-125"></a><a name="index-lines-starting-with-_0040code_007b_0023_007d-126"></a><a name="index-logical-line-numbers-127"></a>To be compatible with past assemblers, lines that begin with <span class="samp">#</span> have a
special interpretation. Following the <span class="samp">#</span> should be an absolute
expression (see <a href="Expressions.html#Expressions">Expressions</a>): the logical line number of the <em>next</em>
line. Then a string (see <a href="Strings.html#Strings">Strings</a>) is allowed: if present it is a
new logical file name. The rest of the line, if any, should be whitespace.
<p>If the first non-whitespace characters on the line are not numeric,
the line is ignored. (Just like a comment.)
<pre class="smallexample"> # This is an ordinary comment.
# 42-6 "new_file_name" # New logical file name
# This is logical line # 36.
</pre>
<p>This feature is deprecated, and may disappear from future versions
of <span class="command">as</span>.
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<h5 class="subsubsection">9.15.4.2 Compare-and-Branch</h5>
<p><a name="index-i960-compare_002fbranch-instructions-998"></a><a name="index-compare_002fbranch-instructions_002c-i960-999"></a>The 960 architectures provide combined Compare-and-Branch instructions
that permit you to store the branch target in the lower 13 bits of the
instruction word itself. However, if you specify a branch target far
enough away that its address won't fit in 13 bits, the assembler can
either issue an error, or convert your Compare-and-Branch instruction
into separate instructions to do the compare and the branch.
<p><a name="index-compare-and-jump-expansions_002c-i960-1000"></a><a name="index-i960-compare-and-jump-expansions-1001"></a>Whether <code>as</code> gives an error or expands the instruction depends
on two choices you can make: whether you use the <span class="samp">-no-relax</span> option,
and whether you use a &ldquo;Compare and Branch&rdquo; instruction or a &ldquo;Compare
and Jump&rdquo; instruction. The &ldquo;Jump&rdquo; instructions are <em>always</em>
expanded if necessary; the &ldquo;Branch&rdquo; instructions are expanded when
necessary <em>unless</em> you specify <code>-no-relax</code>&mdash;in which case
<code>as</code> gives an error instead.
<p>These are the Compare-and-Branch instructions, their &ldquo;Jump&rdquo; variants,
and the instruction pairs they may expand into:
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<h3 class="section">3.6 Constants</h3>
<p><a name="index-constants-139"></a>A constant is a number, written so that its value is known by
inspection, without knowing any context. Like this:
<pre class="smallexample"> .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
.ascii "Ring the bell\7" # A string constant.
.octa 0x123456789abcdef0123456789ABCDEF0 # A bignum.
.float 0f-314159265358979323846264338327\
95028841971.693993751E-40 # - pi, a flonum.
</pre>
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<h3 class="section">2.3 <span class="option">-D</span></h3>
<p><a name="index-_002dD-58"></a>This option has no effect whatsoever, but it is accepted to make it more
likely that scripts written for other assemblers also work with
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<h5 class="subsubsection">9.8.2.5 Addressing Modes</h5>
<p><a name="index-addressing-modes_002c-D10V-739"></a><a name="index-D10V-addressing-modes-740"></a><code>as</code> understands the following addressing modes for the D10V.
<code>R</code><var>n</var> in the following refers to any of the numbered
registers, but <em>not</em> the control registers.
<dl>
<dt><code>R</code><var>n</var><dd>Register direct
<br><dt><code>@R</code><var>n</var><dd>Register indirect
<br><dt><code>@R</code><var>n</var><code>+</code><dd>Register indirect with post-increment
<br><dt><code>@R</code><var>n</var><code>-</code><dd>Register indirect with post-decrement
<br><dt><code>@-SP</code><dd>Register indirect with pre-decrement
<br><dt><code>@(</code><var>disp</var><code>, R</code><var>n</var><code>)</code><dd>Register indirect with displacement
<br><dt><var>addr</var><dd>PC relative address (for branch or rep).
<br><dt><code>#</code><var>imm</var><dd>Immediate data (the <span class="samp">#</span> is optional and ignored)
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<h5 class="subsubsection">9.8.2.3 Special Characters</h5>
<p><a name="index-line-comment-character_002c-D10V-731"></a><a name="index-D10V-line-comment-character-732"></a><span class="samp">;</span> and <span class="samp">#</span> are the line comment characters.
<a name="index-sub_002dinstruction-ordering_002c-D10V-733"></a><a name="index-D10V-sub_002dinstruction-ordering-734"></a>Sub-instructions may be executed in order, in reverse-order, or in parallel.
Instructions listed in the standard one-per-line format will be executed sequentially.
To specify the executing order, use the following symbols:
<dl>
<dt><span class="samp">-&gt;</span><dd>Sequential with instruction on the left first.
<br><dt><span class="samp">&lt;-</span><dd>Sequential with instruction on the right first.
<br><dt><span class="samp">||</span><dd>Parallel
</dl>
The D10V syntax allows either one instruction per line, one instruction per line with
the execution symbol, or two instructions per line. For example
<dl>
<dt><code>abs a1 -&gt; abs r0</code><dd>Execute these sequentially. The instruction on the right is in the right
container and is executed second.
<br><dt><code>abs r0 &lt;- abs a1</code><dd>Execute these reverse-sequentially. The instruction on the right is in the right
container, and is executed first.
<br><dt><code>ld2w r2,@r8+ || mac a0,r0,r7</code><dd>Execute these in parallel.
<br><dt><code>ld2w r2,@r8+ ||</code><dt><code>mac a0,r0,r7</code><dd>Two-line format. Execute these in parallel.
<br><dt><code>ld2w r2,@r8+</code><dt><code>mac a0,r0,r7</code><dd>Two-line format. Execute these sequentially. Assembler will
put them in the proper containers.
<br><dt><code>ld2w r2,@r8+ -&gt;</code><dt><code>mac a0,r0,r7</code><dd>Two-line format. Execute these sequentially. Same as above but
second instruction will always go into right container.
</dl>
<a name="index-symbol-names_002c-_0040samp_007b_0024_007d-in-735"></a><a name="index-_0040code_007b_0024_007d-in-symbol-names-736"></a>Since <span class="samp">$</span> has no special meaning, you may use it in symbol names.
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<h3 class="section">9.8 D10V Dependent Features</h3>
<p><a name="index-D10V-support-722"></a>
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<li><a accesskey="1" href="D10V_002dOpts.html#D10V_002dOpts">D10V-Opts</a>: D10V Options
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<h4 class="subsection">9.8.3 Floating Point</h4>
<p><a name="index-floating-point_002c-D10V-743"></a><a name="index-D10V-floating-point-744"></a>The D10V has no hardware floating point, but the <code>.float</code> and <code>.double</code>
directives generates <span class="sc">ieee</span> floating-point numbers for compatibility
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<a name="D10V_002dOpcodes"></a>Previous:&nbsp;<a rel="previous" accesskey="p" href="D10V_002dFloat.html#D10V_002dFloat">D10V-Float</a>,
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<hr><br>
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<h4 class="subsection">9.8.4 Opcodes</h4>
<p><a name="index-D10V-opcode-summary-745"></a><a name="index-opcode-summary_002c-D10V-746"></a><a name="index-mnemonics_002c-D10V-747"></a><a name="index-instruction-summary_002c-D10V-748"></a>For detailed information on the D10V machine instruction set, see
<cite>D10V Architecture: A VLIW Microprocessor for Multimedia Applications</cite>
(Mitsubishi Electric Corp.).
<code>as</code> implements all the standard D10V opcodes. The only changes are those
described in the section on size modifiers
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<h4 class="subsection">9.8.1 D10V Options</h4>
<p><a name="index-options_002c-D10V-723"></a><a name="index-D10V-options-724"></a>The Mitsubishi D10V version of <code>as</code> has a few machine
dependent options.
<dl>
<dt><span class="samp">-O</span><dd>The D10V can often execute two sub-instructions in parallel. When this option
is used, <code>as</code> will attempt to optimize its output by detecting when
instructions can be executed in parallel.
<br><dt><span class="samp">--nowarnswap</span><dd>To optimize execution performance, <code>as</code> will sometimes swap the
order of instructions. Normally this generates a warning. When this option
is used, no warning will be generated when instructions are swapped.
<br><dt><span class="samp">--gstabs-packing</span><br><dt><span class="samp">--no-gstabs-packing</span><dd><code>as</code> packs adjacent short instructions into a single packed
instruction. <span class="samp">--no-gstabs-packing</span> turns instruction packing off if
<span class="samp">--gstabs</span> is specified as well; <span class="samp">--gstabs-packing</span> (the
default) turns instruction packing on even when <span class="samp">--gstabs</span> is
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<h5 class="subsubsection">9.8.2.4 Register Names</h5>
<p><a name="index-D10V-registers-737"></a><a name="index-registers_002c-D10V-738"></a>You can use the predefined symbols <span class="samp">r0</span> through <span class="samp">r15</span> to refer to the D10V
registers. You can also use <span class="samp">sp</span> as an alias for <span class="samp">r15</span>. The accumulators
are <span class="samp">a0</span> and <span class="samp">a1</span>. There are special register-pair names that may
optionally be used in opcodes that require even-numbered registers. Register names are
not case sensitive.
<p>Register Pairs
<dl>
<dt><code>r0-r1</code><br><dt><code>r2-r3</code><br><dt><code>r4-r5</code><br><dt><code>r6-r7</code><br><dt><code>r8-r9</code><br><dt><code>r10-r11</code><br><dt><code>r12-r13</code><br><dt><code>r14-r15</code><dd></dl>
<p>The D10V also has predefined symbols for these control registers and status bits:
<dl>
<dt><code>psw</code><dd>Processor Status Word
<br><dt><code>bpsw</code><dd>Backup Processor Status Word
<br><dt><code>pc</code><dd>Program Counter
<br><dt><code>bpc</code><dd>Backup Program Counter
<br><dt><code>rpt_c</code><dd>Repeat Count
<br><dt><code>rpt_s</code><dd>Repeat Start address
<br><dt><code>rpt_e</code><dd>Repeat End address
<br><dt><code>mod_s</code><dd>Modulo Start address
<br><dt><code>mod_e</code><dd>Modulo End address
<br><dt><code>iba</code><dd>Instruction Break Address
<br><dt><code>f0</code><dd>Flag 0
<br><dt><code>f1</code><dd>Flag 1
<br><dt><code>c</code><dd>Carry flag
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<h5 class="subsubsection">9.8.2.1 Size Modifiers</h5>
<p><a name="index-D10V-size-modifiers-727"></a><a name="index-size-modifiers_002c-D10V-728"></a>The D10V version of <code>as</code> uses the instruction names in the D10V
Architecture Manual. However, the names in the manual are sometimes ambiguous.
There are instruction names that can assemble to a short or long form opcode.
How does the assembler pick the correct form? <code>as</code> will always pick the
smallest form if it can. When dealing with a symbol that is not defined yet when a
line is being assembled, it will always use the long form. If you need to force the
assembler to use either the short or long form of the instruction, you can append
either <span class="samp">.s</span> (short) or <span class="samp">.l</span> (long) to it. For example, if you are writing
an assembly program and you want to do a branch to a symbol that is defined later
in your program, you can write <span class="samp">bra.s foo</span>.
Objdump and GDB will always append <span class="samp">.s</span> or <span class="samp">.l</span> to instructions which
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<h5 class="subsubsection">9.8.2.2 Sub-Instructions</h5>
<p><a name="index-D10V-sub_002dinstructions-729"></a><a name="index-sub_002dinstructions_002c-D10V-730"></a>The D10V assembler takes as input a series of instructions, either one-per-line,
or in the special two-per-line format described in the next section. Some of these
instructions will be short-form or sub-instructions. These sub-instructions can be packed
into a single instruction. The assembler will do this automatically. It will also detect
when it should not pack instructions. For example, when a label is defined, the next
instruction will never be packaged with the previous one. Whenever a branch and link
instruction is called, it will not be packaged with the next instruction so the return
address will be valid. Nops are automatically inserted when necessary.
<p>If you do not want the assembler automatically making these decisions, you can control
the packaging and execution type (parallel or sequential) with the special execution
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<hr><br>
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<h4 class="subsection">9.8.2 Syntax</h4>
<p><a name="index-D10V-syntax-725"></a><a name="index-syntax_002c-D10V-726"></a>
The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual.
The differences are detailed below.
<ul class="menu">
<li><a accesskey="1" href="D10V_002dSize.html#D10V_002dSize">D10V-Size</a>: Size Modifiers
<li><a accesskey="2" href="D10V_002dSubs.html#D10V_002dSubs">D10V-Subs</a>: Sub-Instructions
<li><a accesskey="3" href="D10V_002dChars.html#D10V_002dChars">D10V-Chars</a>: Special Characters
<li><a accesskey="4" href="D10V_002dRegs.html#D10V_002dRegs">D10V-Regs</a>: Register Names
<li><a accesskey="5" href="D10V_002dAddressing.html#D10V_002dAddressing">D10V-Addressing</a>: Addressing Modes
<li><a accesskey="6" href="D10V_002dWord.html#D10V_002dWord">D10V-Word</a>: @WORD Modifier
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<h5 class="subsubsection">9.8.2.6 @WORD Modifier</h5>
<p><a name="index-D10V-_0040_0040word-modifier-741"></a><a name="index-_0040_0040word-modifier_002c-D10V-742"></a>Any symbol followed by <code>@word</code> will be replaced by the symbol's value
shifted right by 2. This is used in situations such as loading a register
with the address of a function (or any other code fragment). For example, if
you want to load a register with the location of the function <code>main</code> then
jump to that function, you could do it as follows:
<pre class="smallexample"> ldi r2, main@word
jmp r2
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<hr><br>
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<h5 class="subsubsection">9.9.2.6 Addressing Modes</h5>
<p><a name="index-addressing-modes_002c-D30V-767"></a><a name="index-D30V-addressing-modes-768"></a><code>as</code> understands the following addressing modes for the D30V.
<code>R</code><var>n</var> in the following refers to any of the numbered
registers, but <em>not</em> the control registers.
<dl>
<dt><code>R</code><var>n</var><dd>Register direct
<br><dt><code>@R</code><var>n</var><dd>Register indirect
<br><dt><code>@R</code><var>n</var><code>+</code><dd>Register indirect with post-increment
<br><dt><code>@R</code><var>n</var><code>-</code><dd>Register indirect with post-decrement
<br><dt><code>@-SP</code><dd>Register indirect with pre-decrement
<br><dt><code>@(</code><var>disp</var><code>, R</code><var>n</var><code>)</code><dd>Register indirect with displacement
<br><dt><var>addr</var><dd>PC relative address (for branch or rep).
<br><dt><code>#</code><var>imm</var><dd>Immediate data (the <span class="samp">#</span> is optional and ignored)
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<hr><br>
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<h5 class="subsubsection">9.9.2.3 Special Characters</h5>
<p><a name="index-line-comment-character_002c-D30V-758"></a><a name="index-D30V-line-comment-character-759"></a><span class="samp">;</span> and <span class="samp">#</span> are the line comment characters.
<a name="index-sub_002dinstruction-ordering_002c-D30V-760"></a><a name="index-D30V-sub_002dinstruction-ordering-761"></a>Sub-instructions may be executed in order, in reverse-order, or in parallel.
Instructions listed in the standard one-per-line format will be executed
sequentially unless you use the <span class="samp">-O</span> option.
<p>To specify the executing order, use the following symbols:
<dl>
<dt><span class="samp">-&gt;</span><dd>Sequential with instruction on the left first.
<br><dt><span class="samp">&lt;-</span><dd>Sequential with instruction on the right first.
<br><dt><span class="samp">||</span><dd>Parallel
</dl>
<p>The D30V syntax allows either one instruction per line, one instruction per line with
the execution symbol, or two instructions per line. For example
<dl>
<dt><code>abs r2,r3 -&gt; abs r4,r5</code><dd>Execute these sequentially. The instruction on the right is in the right
container and is executed second.
<br><dt><code>abs r2,r3 &lt;- abs r4,r5</code><dd>Execute these reverse-sequentially. The instruction on the right is in the right
container, and is executed first.
<br><dt><code>abs r2,r3 || abs r4,r5</code><dd>Execute these in parallel.
<br><dt><code>ldw r2,@(r3,r4) ||</code><dt><code>mulx r6,r8,r9</code><dd>Two-line format. Execute these in parallel.
<br><dt><code>mulx a0,r8,r9</code><dt><code>stw r2,@(r3,r4)</code><dd>Two-line format. Execute these sequentially unless <span class="samp">-O</span> option is
used. If the <span class="samp">-O</span> option is used, the assembler will determine if
the instructions could be done in parallel (the above two instructions
can be done in parallel), and if so, emit them as parallel instructions.
The assembler will put them in the proper containers. In the above
example, the assembler will put the <span class="samp">stw</span> instruction in left
container and the <span class="samp">mulx</span> instruction in the right container.
<br><dt><code>stw r2,@(r3,r4) -&gt;</code><dt><code>mulx a0,r8,r9</code><dd>Two-line format. Execute the <span class="samp">stw</span> instruction followed by the
<span class="samp">mulx</span> instruction sequentially. The first instruction goes in the
left container and the second instruction goes into right container.
The assembler will give an error if the machine ordering constraints are
violated.
<br><dt><code>stw r2,@(r3,r4) &lt;-</code><dt><code>mulx a0,r8,r9</code><dd>Same as previous example, except that the <span class="samp">mulx</span> instruction is
executed before the <span class="samp">stw</span> instruction.
</dl>
<p><a name="index-symbol-names_002c-_0040samp_007b_0024_007d-in-762"></a><a name="index-_0040code_007b_0024_007d-in-symbol-names-763"></a>Since <span class="samp">$</span> has no special meaning, you may use it in symbol names.
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<h3 class="section">9.9 D30V Dependent Features</h3>
<p><a name="index-D30V-support-749"></a>
<ul class="menu">
<li><a accesskey="1" href="D30V_002dOpts.html#D30V_002dOpts">D30V-Opts</a>: D30V Options
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<h4 class="subsection">9.9.3 Floating Point</h4>
<p><a name="index-floating-point_002c-D30V-769"></a><a name="index-D30V-floating-point-770"></a>The D30V has no hardware floating point, but the <code>.float</code> and <code>.double</code>
directives generates <span class="sc">ieee</span> floating-point numbers for compatibility
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<h5 class="subsubsection">9.9.2.4 Guarded Execution</h5>
<p><a name="index-D30V-Guarded-Execution-764"></a><code>as</code> supports the full range of guarded execution
directives for each instruction. Just append the directive after the
instruction proper. The directives are:
<dl>
<dt><span class="samp">/tx</span><dd>Execute the instruction if flag f0 is true.
<br><dt><span class="samp">/fx</span><dd>Execute the instruction if flag f0 is false.
<br><dt><span class="samp">/xt</span><dd>Execute the instruction if flag f1 is true.
<br><dt><span class="samp">/xf</span><dd>Execute the instruction if flag f1 is false.
<br><dt><span class="samp">/tt</span><dd>Execute the instruction if both flags f0 and f1 are true.
<br><dt><span class="samp">/tf</span><dd>Execute the instruction if flag f0 is true and flag f1 is false.
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<h4 class="subsection">9.9.4 Opcodes</h4>
<p><a name="index-D30V-opcode-summary-771"></a><a name="index-opcode-summary_002c-D30V-772"></a><a name="index-mnemonics_002c-D30V-773"></a><a name="index-instruction-summary_002c-D30V-774"></a>For detailed information on the D30V machine instruction set, see
<cite>D30V Architecture: A VLIW Microprocessor for Multimedia Applications</cite>
(Mitsubishi Electric Corp.).
<code>as</code> implements all the standard D30V opcodes. The only changes are those
described in the section on size modifiers
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<h4 class="subsection">9.9.1 D30V Options</h4>
<p><a name="index-options_002c-D30V-750"></a><a name="index-D30V-options-751"></a>The Mitsubishi D30V version of <code>as</code> has a few machine
dependent options.
<dl>
<dt><span class="samp">-O</span><dd>The D30V can often execute two sub-instructions in parallel. When this option
is used, <code>as</code> will attempt to optimize its output by detecting when
instructions can be executed in parallel.
<br><dt><span class="samp">-n</span><dd>When this option is used, <code>as</code> will issue a warning every
time it adds a nop instruction.
<br><dt><span class="samp">-N</span><dd>When this option is used, <code>as</code> will issue a warning if it
needs to insert a nop after a 32-bit multiply before a load or 16-bit
multiply instruction.
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<h5 class="subsubsection">9.9.2.5 Register Names</h5>
<p><a name="index-D30V-registers-765"></a><a name="index-registers_002c-D30V-766"></a>You can use the predefined symbols <span class="samp">r0</span> through <span class="samp">r63</span> to refer
to the D30V registers. You can also use <span class="samp">sp</span> as an alias for
<span class="samp">r63</span> and <span class="samp">link</span> as an alias for <span class="samp">r62</span>. The accumulators
are <span class="samp">a0</span> and <span class="samp">a1</span>.
<p>The D30V also has predefined symbols for these control registers and status bits:
<dl>
<dt><code>psw</code><dd>Processor Status Word
<br><dt><code>bpsw</code><dd>Backup Processor Status Word
<br><dt><code>pc</code><dd>Program Counter
<br><dt><code>bpc</code><dd>Backup Program Counter
<br><dt><code>rpt_c</code><dd>Repeat Count
<br><dt><code>rpt_s</code><dd>Repeat Start address
<br><dt><code>rpt_e</code><dd>Repeat End address
<br><dt><code>mod_s</code><dd>Modulo Start address
<br><dt><code>mod_e</code><dd>Modulo End address
<br><dt><code>iba</code><dd>Instruction Break Address
<br><dt><code>f0</code><dd>Flag 0
<br><dt><code>f1</code><dd>Flag 1
<br><dt><code>f2</code><dd>Flag 2
<br><dt><code>f3</code><dd>Flag 3
<br><dt><code>f4</code><dd>Flag 4
<br><dt><code>f5</code><dd>Flag 5
<br><dt><code>f6</code><dd>Flag 6
<br><dt><code>f7</code><dd>Flag 7
<br><dt><code>s</code><dd>Same as flag 4 (saturation flag)
<br><dt><code>v</code><dd>Same as flag 5 (overflow flag)
<br><dt><code>va</code><dd>Same as flag 6 (sticky overflow flag)
<br><dt><code>c</code><dd>Same as flag 7 (carry/borrow flag)
<br><dt><code>b</code><dd>Same as flag 7 (carry/borrow flag)
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<h5 class="subsubsection">9.9.2.1 Size Modifiers</h5>
<p><a name="index-D30V-size-modifiers-754"></a><a name="index-size-modifiers_002c-D30V-755"></a>The D30V version of <code>as</code> uses the instruction names in the D30V
Architecture Manual. However, the names in the manual are sometimes ambiguous.
There are instruction names that can assemble to a short or long form opcode.
How does the assembler pick the correct form? <code>as</code> will always pick the
smallest form if it can. When dealing with a symbol that is not defined yet when a
line is being assembled, it will always use the long form. If you need to force the
assembler to use either the short or long form of the instruction, you can append
either <span class="samp">.s</span> (short) or <span class="samp">.l</span> (long) to it. For example, if you are writing
an assembly program and you want to do a branch to a symbol that is defined later
in your program, you can write <span class="samp">bra.s foo</span>.
Objdump and GDB will always append <span class="samp">.s</span> or <span class="samp">.l</span> to instructions which
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<h5 class="subsubsection">9.9.2.2 Sub-Instructions</h5>
<p><a name="index-D30V-sub_002dinstructions-756"></a><a name="index-sub_002dinstructions_002c-D30V-757"></a>The D30V assembler takes as input a series of instructions, either one-per-line,
or in the special two-per-line format described in the next section. Some of these
instructions will be short-form or sub-instructions. These sub-instructions can be packed
into a single instruction. The assembler will do this automatically. It will also detect
when it should not pack instructions. For example, when a label is defined, the next
instruction will never be packaged with the previous one. Whenever a branch and link
instruction is called, it will not be packaged with the next instruction so the return
address will be valid. Nops are automatically inserted when necessary.
<p>If you do not want the assembler automatically making these decisions, you can control
the packaging and execution type (parallel or sequential) with the special execution
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<h4 class="subsection">9.9.2 Syntax</h4>
<p><a name="index-D30V-syntax-752"></a><a name="index-syntax_002c-D30V-753"></a>
The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual.
The differences are detailed below.
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<h3 class="section">7.32 <code>.data </code><var>subsection</var></h3>
<p><a name="index-_0040code_007bdata_007d-directive-295"></a><code>.data</code> tells <span class="command">as</span> to assemble the following statements onto the
end of the data subsection numbered <var>subsection</var> (which is an
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<h3 class="section">7.33 <code>.def </code><var>name</var></h3>
<p><a name="index-_0040code_007bdef_007d-directive-296"></a><a name="index-COFF-symbols_002c-debugging-297"></a><a name="index-debugging-COFF-symbols-298"></a>Begin defining debugging information for a symbol <var>name</var>; the
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