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<h3 class="section">4.3 <span class="command">ld</span> and the Motorola 68HC11 and 68HC12 families</h3>
<p><a name="index-M68HC11-and-68HC12-support-528"></a>
<h4 class="subsection">4.3.1 Linker Relaxation</h4>
<p>For the Motorola 68HC11, <span class="command">ld</span> can perform these global
optimizations when you specify the <span class="samp">--relax</span> command-line option.
<a name="index-relaxing-on-M68HC11-529"></a>
<dl><dt><em>relaxing address modes</em><dd><span class="command">ld</span> finds all <code>jsr</code> and <code>jmp</code> instructions whose
targets are within eight bits, and turns them into eight-bit
program-counter relative <code>bsr</code> and <code>bra</code> instructions,
respectively.
<p><span class="command">ld</span> also looks at all 16-bit extended addressing modes and
transforms them in a direct addressing mode when the address is in
page 0 (between 0 and 0x0ff).
<br><dt><em>relaxing gcc instruction group</em><dd>When <span class="command">gcc</span> is called with <span class="option">-mrelax</span>, it can emit group
of instructions that the linker can optimize to use a 68HC11 direct
addressing mode. These instructions consists of <code>bclr</code> or
<code>bset</code> instructions.
</dl>
<h4 class="subsection">4.3.2 Trampoline Generation</h4>
<p><a name="index-trampoline-generation-on-M68HC11-530"></a><a name="index-trampoline-generation-on-M68HC12-531"></a>For 68HC11 and 68HC12, <span class="command">ld</span> can generate trampoline code to
call a far function using a normal <code>jsr</code> instruction. The linker
will also change the relocation to some far function to use the
trampoline address instead of the function address. This is typically the
case when a pointer to a function is taken. The pointer will in fact
point to the function trampoline.
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