arduino-0018-windows
This commit is contained in:
parent
157fd6f1a1
commit
f39fc49523
5182 changed files with 950586 additions and 0 deletions
|
@ -0,0 +1,247 @@
|
|||
#
|
||||
# $Id: README.opcodes,v 1.3 2001/12/02 21:54:45 troth Exp $
|
||||
#
|
||||
##############################################################################
|
||||
##
|
||||
## Most of the information in this file was taken directly from the Atmel
|
||||
## data sheets and is most likely copyrighted by Atmel. As such, this file
|
||||
## may need to disappear.
|
||||
##
|
||||
##############################################################################
|
||||
|
||||
Instruction Set Nomenclature:
|
||||
|
||||
Status Register (SREG)
|
||||
|
||||
SREG: Status register
|
||||
C: Carry flag in status register
|
||||
Z: Zero flag in status register
|
||||
N: Negative flag in status register
|
||||
V: Two's complement overflow indicator
|
||||
S: N A* V, For signed tests
|
||||
H: Half Carry flag in the status register
|
||||
T: Transfer bit used by BLD and BST instructions
|
||||
I: Global interrupt enable/disable flag
|
||||
|
||||
Registers and Operands
|
||||
|
||||
Rd: Destination (and source) register in the register file
|
||||
Rr: Source register in the register file
|
||||
R: Result after instruction is executed
|
||||
K: Constant data
|
||||
k: Constant address
|
||||
b: Bit in the register file or I/O register (3 bit)
|
||||
s: Bit in the status register (3 bit)
|
||||
X,Y,Z: Indirect address register (X=R27:R26, Y=R29:R28 and Z=R31:R30)
|
||||
A: I/O location address
|
||||
q: Displacement for direct addressing (6 bit)
|
||||
|
||||
I/O Registers
|
||||
|
||||
RAMPX, RAMPY, RAMPZ
|
||||
Registers concatenated with the X, Y and Z registers enabling indirect
|
||||
addressing of the whole data space on MCUs withmore than 64K bytes data space,
|
||||
and constant data fetch on MCUs with more than 64K bytes program space.
|
||||
|
||||
RAMPD
|
||||
Register concatenated with the Z register enabling direct addressing of the
|
||||
whole data space on MCUs with more than 64Kbytes data space.
|
||||
|
||||
EIND
|
||||
Register concatenated with the instruction word enabling indirect jump and
|
||||
call to the whole program space on MCUs withmore than 64K bytes program space.
|
||||
|
||||
Stack
|
||||
STACK: Stack for return address and pushed registers
|
||||
SP: Stack Pointer to STACK
|
||||
|
||||
Flags
|
||||
<=>: Flag affected by instruction
|
||||
0: Flag cleared by instruction
|
||||
1: Flag set by instruction
|
||||
-: Flag not affected by instruction
|
||||
|
||||
Conditional Branch Summary
|
||||
|
||||
Note: 1. Interchange Rd and Rr in the operation before the test. i.e.
|
||||
CP Rd,Rr -> CP Rr,Rd
|
||||
|
||||
Test Boolean Mnemonic Complementary Boolean Mnemonic Comment
|
||||
Rd > Rr Z&(N ^ V) = 0 BRLT(1) Rd <= Rr Z+(N ^ V) = 1 BRGE* Signed
|
||||
Rd >= Rr (N ^ V) = 0 BRGE Rd < Rr (N ^ V) = 1 BRLT Signed
|
||||
Rd = Rr Z = 1 BREQ Rd != Rr Z = 0 BRNE Signed
|
||||
Rd <= Rr Z+(N ^ V) = 1 BRGE(1) Rd > Rr Z&(N ^ V) = 0 BRLT* Signed
|
||||
Rd < Rr (N ^ V) = 1 BRLT Rd >= Rr (N ^ V) = 0 BRGE Signed
|
||||
Rd > Rr C + Z = 0 BRLO(1) Rd <= Rr C + Z = 1 BRSH* Unsigned
|
||||
Rd >= Rr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS Unsigned
|
||||
Rd = Rr Z = 1 BREQ Rd != Rr Z = 0 BRNE Unsigned
|
||||
Rd <= Rr C + Z = 1 BRSH(1) Rd > Rr C + Z = 0 BRLO* Unsigned
|
||||
Rd < Rr C = 1 BRLO/BRCS Rd >= Rr C = 0 BRSH/BRCC Unsigned
|
||||
Carry C = 1 BRCS No carry C = 0 BRCC Simple
|
||||
Negative N = 1 BRMI Positive N = 0 BRPL Simple
|
||||
Overflow V = 1 BRVS No overflow V = 0 BRVC Simple
|
||||
Zero Z = 1 BREQ Not zero Z = 0 BRNE Simple
|
||||
|
||||
|
||||
Complete Instruction Set Summary
|
||||
|
||||
Notes:
|
||||
|
||||
1. Not all instructions are available in all devices. Refer to the device
|
||||
specific instruction summary.
|
||||
|
||||
2. Cycle times for data memory accesses assume internal memory accesses, and
|
||||
are not valid for accesses via the external RAM interface. For LD, ST, LDS,
|
||||
STS, PUSH, POP, add one cycle plus one cycle for each wait state. For CALL,
|
||||
ICALL, EICALL, RCALL, RET, RETI in devices with 16 bit PC, add three cycles
|
||||
plus two cycles for each wait state. For CALL, ICALL, EICALL, RCALL, RET,
|
||||
RETI in devices with 22 bit PC, add five cycles plus three cycles for each
|
||||
wait state.
|
||||
|
||||
Instruction Set Summary
|
||||
|
||||
Arithmetic and Logic Instructions
|
||||
|
||||
| | | | Device Availability|
|
||||
Mnem | Opcode | Operands | Method Name | 1200 | 4414 | 8515 |
|
||||
=======|=====================|==========|=============|======|======|======|
|
||||
ADC | 0001 11rd dddd rrrr | Rd, Rr | ADC | * | * | * |
|
||||
ADD | 0000 11rd dddd rrrr | Rd, Rr | ADD | * | * | * |
|
||||
ADIW | 1001 0110 KKdd KKKK | Rd, Rr | ADIW | - | * | * |
|
||||
AND | 0010 00rd dddd rrrr | Rd, Rr | AND | * | * | * |
|
||||
ANDI | 0111 KKKK dddd KKKK | Rd, K | ANDI | * | * | * |
|
||||
ASR | 1001 010d dddd 0101 | Rd | ASR | * | * | * |
|
||||
BCLR | 1001 0100 1sss 1000 | s | BCLR | * | * | * |
|
||||
BLD | 1111 100d dddd 0bbb | Rd, b | BLD | * | * | * |
|
||||
BRBC | 1111 01kk kkkk ksss | s, k | BRCS | * | * | * |
|
||||
BRBS | 1111 00kk kkkk ksss | s, k | BRBS | * | * | * |
|
||||
BRCC | 1111 01kk kkkk k000 | k | BRCC | * | * | * |
|
||||
BRCS | 1111 00kk kkkk k000 | k | BRCS | * | * | * |
|
||||
BREQ | 1111 00kk kkkk k001 | k | BREQ | * | * | * |
|
||||
BRGE | 1111 01kk kkkk k100 | k | BRGE | * | * | * |
|
||||
BRHC | 1111 01kk kkkk k101 | k | BRHC | * | * | * |
|
||||
BRHS | 1111 00kk kkkk k101 | k | BRHS | * | * | * |
|
||||
BRID | 1111 01kk kkkk k111 | k | BRID | * | * | * |
|
||||
BRIE | 1111 00kk kkkk k111 | k | BRIE | * | * | * |
|
||||
BRLO | 1111 00kk kkkk k000 | k | BRCS | * | * | * |
|
||||
BRLT | 1111 00kk kkkk k100 | k | BRLT | * | * | * |
|
||||
BRMI | 1111 00kk kkkk k010 | k | BRMI | * | * | * |
|
||||
BRNE | 1111 01kk kkkk k001 | k | BRNE | * | * | * |
|
||||
BRPL | 1111 01kk kkkk k010 | k | BRPL | * | * | * |
|
||||
BRSH | 1111 01kk kkkk k000 | k | BRCC | * | * | * |
|
||||
BRTC | 1111 01kk kkkk k110 | k | BRTC | * | * | * |
|
||||
BRTS | 1111 00kk kkkk k110 | k | BRTS | * | * | * |
|
||||
BRVC | 1111 01kk kkkk k011 | k | BRVC | * | * | * |
|
||||
BRVS | 1111 00kk kkkk k011 | k | BRVS | * | * | * |
|
||||
BSET | 1001 0100 0sss 1000 | s | BSET | * | * | * |
|
||||
BST | 1111 101d dddd 0bbb | Rr, b | BST | * | * | * |
|
||||
CALL | 1001 010k kkkk 111k | k | CALL | - | - | - |
|
||||
| kkkk kkkk kkkk kkkk | | | | | |
|
||||
CBI | 1001 1000 AAAA Abbb | A, b | CBI | * | * | * |
|
||||
CBR | 0111 KKKK dddd KKKK | Rd, K | CBR | * | * | * |
|
||||
CLC | 1001 0100 1000 1000 | | CLC | * | * | * |
|
||||
CLH | 1001 0100 1101 1000 | | CLH | * | * | * |
|
||||
CLI | 1001 0100 1111 1000 | | CLI | * | * | * |
|
||||
CLN | 1001 0100 1010 1000 | | CLN | * | * | * |
|
||||
CLR | 0010 01dd dddd dddd | Rd | EOR | * | * | * |
|
||||
CLS | 1001 0100 1100 1000 | | CLS | * | * | * |
|
||||
CLT | 1001 0100 1110 1000 | | CLT | * | * | * |
|
||||
CLV | 1001 0100 1011 1000 | | CLV | * | * | * |
|
||||
CLZ | 1001 0100 1001 1000 | | CLZ | * | * | * |
|
||||
COM | 1001 010d dddd 0000 | Rd | COM | * | * | * |
|
||||
CP | 0001 01rd dddd rrrr | Rd, Rr | CP | * | * | * |
|
||||
CPC | 0000 01rd dddd rrrr | Rd, Rr | CPC | * | * | * |
|
||||
CPI | 0011 KKKK dddd KKKK | Rd, K | CPI | * | * | * |
|
||||
CPSE | 0001 00rd dddd rrrr | Rd, Rr | CPSE | * | * | * |
|
||||
DEC | 1001 010d dddd 1010 | Rd | DEC | * | * | * |
|
||||
EICALL | 1001 0101 0001 1001 | | EICALL | - | - | - |
|
||||
EIJMP | 1001 0100 0001 1001 | | EIJMP | - | - | - |
|
||||
ELPM | 1001 0101 1101 1000 | | ELPM | - | - | - |
|
||||
ELPM | 1001 000d dddd 0110 | Rd, Z | ELPM_Z | - | - | - |
|
||||
ELPM | 1001 000d dddd 0111 | Rd, Z+ | ELPM_Z_incr | - | - | - |
|
||||
EOR | 0010 01rd dddd rrrr | Rd, Rr | EOR | * | * | * |
|
||||
ESPM | 1001 0101 1111 1000 | | ESPM | - | - | - |
|
||||
FMUL | 0000 0011 0ddd 1rrr | Rd, Rr | FMUL | - | - | - |
|
||||
FMULS | 0000 0011 1ddd 0rrr | Rd, Rr | FMULS | - | - | - |
|
||||
FMULSU | 0000 0011 1ddd 1rrr | Rd, Rr | FMULSU | - | - | - |
|
||||
ICALL | 1001 0101 0000 1001 | | ICALL | - | * | * |
|
||||
IJMP | 1001 0100 0000 1001 | | IJMP | - | * | * |
|
||||
IN | 1011 0AAd dddd AAAA | Rd, A | IN | * | * | * |
|
||||
INC | 1001 010d dddd 0011 | Rd | INC | * | * | * |
|
||||
JMP | 1001 010k kkkk 110k | k | JMP | - | - | - |
|
||||
| kkkk kkkk kkkk kkkk | | | | | |
|
||||
LD | 1000 000d dddd 1000 | Rd, Y | LDD_Y | - | * | * |
|
||||
LD | 1001 000d dddd 1001 | Rd, Y+ | LD_Y_incr | - | * | * |
|
||||
LD | 1000 000d dddd 0000 | Rd, Z | LDD_Z | * | * | * |
|
||||
LD | 1001 000d dddd 0001 | Rd, Z+ | LD_Z_incr | - | * | * |
|
||||
LD | 1001 000d dddd 1110 | Rd, -X | LD_X_decr | - | * | * |
|
||||
LD | 1001 000d dddd 1010 | Rd, -Y | LD_Y_decr | - | * | * |
|
||||
LD | 1001 000d dddd 0010 | Rd, -Z | LD_Z_decr | - | * | * |
|
||||
LD | 1001 000d dddd 1100 | Rd, X | LD_X | - | * | * |
|
||||
LD | 1001 000d dddd 1101 | Rd, X+ | LD_X_incr | - | * | * |
|
||||
LDD | 10q0 qq0d dddd 1qqq | Rd, Y+q | LDD_Y | - | * | * |
|
||||
LDD | 10q0 qq0d dddd 0qqq | Rd, Z+q | LDD_Z | - | * | * |
|
||||
LDI | 1110 KKKK dddd KKKK | Rd, K | LDI | * | * | * |
|
||||
LDS | 1001 000d dddd 0000 | Rd, k | LDS | - | * | * |
|
||||
| kkkk kkkk kkkk kkkk | | | | | |
|
||||
LPM | 1001 0101 1100 1000 | | LPM | - | * | * |
|
||||
LPM | 1001 000d dddd 0100 | Rd, Z | LPM_Z | - | - | - |
|
||||
LPM | 1001 000d dddd 0101 | Rd, Z+ | LPM_Z_incr | - | - | - |
|
||||
LSL | 0000 11dd dddd dddd | Rd | AND | * | * | * |
|
||||
LSR | 1001 010d dddd 0110 | Rd | LSR | * | * | * |
|
||||
MOV | 0010 11rd dddd rrrr | Rd, Rr | MOV | * | * | * |
|
||||
MOVW | 0000 0001 dddd rrrr | Rd, Rr | MOVW | - | - | - |
|
||||
MUL | 1001 11rd dddd rrrr | Rd, Rr | MUL | - | - | - |
|
||||
MULS | 0000 0010 dddd rrrr | Rd, Rr | MULS | - | - | - |
|
||||
MULSU | 0000 0011 dddd rrrr | Rd, Rr | MULSU | - | - | - |
|
||||
NEG | 1001 010d dddd 0001 | Rd | NEG | * | * | * |
|
||||
NOP | 0000 0000 0000 0000 | | NOP | * | * | * |
|
||||
OR | 0010 10rd dddd rrrr | Rd, Rr | OR | * | * | * |
|
||||
ORI | 0110 KKKK dddd KKKK | Rd, K | ORI | * | * | * |
|
||||
OUT | 1011 1AAd dddd AAAA | A, Rd | OUT | * | * | * |
|
||||
POP | 1001 000d dddd 1111 | Rd | POP | - | * | * |
|
||||
PUSH | 1001 001d dddd 1111 | Rd | PUSH | - | * | * |
|
||||
RCALL | 1101 kkkk kkkk kkkk | k | RCALL | * | * | * |
|
||||
RET | 1001 0101 0000 1000 | | RET | * | * | * |
|
||||
RETI | 1001 0101 0001 1000 | | RETI | * | * | * |
|
||||
RJMP | 1100 kkkk kkkk kkkk | k | RJMP | * | * | * |
|
||||
ROL | 0001 11dd dddd dddd | Rd | ADC | * | * | * |
|
||||
ROR | 1001 010d dddd 0111 | Rd | ROR | * | * | * |
|
||||
SBC | 0000 10rd dddd rrrr | Rd, Rr | SBC | * | * | * |
|
||||
SBCI | 0100 KKKK dddd KKKK | Rd, K | SBCI | * | * | * |
|
||||
SBI | 1001 1010 AAAA Abbb | A, b | SBI | * | * | * |
|
||||
SBIC | 1001 1001 AAAA Abbb | A, b | SBIC | * | * | * |
|
||||
SBIS | 1001 1011 AAAA Abbb | A, b | SBIS | * | * | * |
|
||||
SBIW | 1001 0111 KKdd KKKK | Rd, K | SBIW | - | - | - |
|
||||
SBR | 0110 KKKK dddd KKKK | Rd, K | SBR | * | * | * |
|
||||
SBRC | 1111 110d dddd 0bbb | Rd, b | SBRC | * | * | * |
|
||||
SBRS | 1111 111d dddd 0bbb | Rd, b | SBRS | * | * | * |
|
||||
SEC | 1001 0100 0000 1000 | | SEC | * | * | * |
|
||||
SEH | 1001 0100 0101 1000 | | SEH | * | * | * |
|
||||
SEI | 1001 0100 0111 1000 | | SEI | * | * | * |
|
||||
SEN | 1001 0100 0010 1000 | | SEN | * | * | * |
|
||||
SER | 1110 1111 dddd 1111 | Rd | LDI | * | * | * |
|
||||
SES | 1001 0100 0100 1000 | | SES | * | * | * |
|
||||
SET | 1001 0100 0110 1000 | | SET | * | * | * |
|
||||
SEV | 1001 0100 0011 1000 | | SEV | * | * | * |
|
||||
SEZ | 1001 0100 0001 1000 | | SEZ | * | * | * |
|
||||
SLEEP | 1001 0101 1000 1000 | | SLEEP | * | * | * |
|
||||
SPM | 1001 0101 1110 1000 | | SPM | - | - | - |
|
||||
ST | 1001 001d dddd 1101 | X+, Rd | ST_X_incr | - | * | * |
|
||||
ST | 1001 001d dddd 1100 | X, Rd | ST_X | - | * | * |
|
||||
ST | 1001 001d dddd 1001 | Y+, Rd | ST_Y_incr | - | * | * |
|
||||
ST | 1000 001d dddd 1000 | Y, Rd | STD_Y | - | * | * |
|
||||
ST | 1001 001d dddd 0001 | Z+, Rd | ST_Z_incr | - | * | * |
|
||||
ST | 1000 001d dddd 0000 | Z, Rd | STD_Z | * | * | * |
|
||||
ST | 1001 001d dddd 1110 |-X, Rd | ST_X_decr | - | * | * |
|
||||
ST | 1001 001d dddd 1010 |-Y, Rd | ST_Y_decr | - | * | * |
|
||||
ST | 1001 001d dddd 0010 |-Z, Rd | ST_Z_decr | - | * | * |
|
||||
STD | 10q0 qq1d dddd 1qqq | Y+q, Rd | STD_Y | - | * | * |
|
||||
STD | 10q0 qq1d dddd 0qqq | Z+q, Rd | STD_Z | - | * | * |
|
||||
STS | 1001 001d dddd 0000 | k, Rd | STS | - | * | * |
|
||||
| kkkk kkkk kkkk kkkk | | | | | |
|
||||
SUB | 0001 10rd dddd rrrr | Rd, Rr | SUB | * | * | * |
|
||||
SUBI | 0101 KKKK dddd KKKK | Rd, K | SUBI | * | * | * |
|
||||
SWAP | 1001 010d dddd 0010 | Rd | SWAP | * | * | * |
|
||||
TST | 0010 00dd dddd dddd | Rd | AND | * | * | * |
|
||||
WDR | 1001 0101 1010 1000 | | WDR | * | * | * |
|
Reference in a new issue