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<a name="ARM-Directives"></a>Next: <a rel="next" accesskey="n" href="ARM-Opcodes.html#ARM-Opcodes">ARM Opcodes</a>,
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<h4 class="subsection">9.3.4 ARM Machine Directives</h4>
<p><a name="index-machine-directives_002c-ARM-600"></a><a name="index-ARM-machine-directives-601"></a>
<a name="index-_0040code_007balign_007d-directive_002c-ARM-602"></a>
<dl><dt><code>.align </code><var>expression</var><code> [, </code><var>expression</var><code>]</code><dd>This is the generic <var>.align</var> directive. For the ARM however if the
first argument is zero (ie no alignment is needed) the assembler will
behave as if the argument had been 2 (ie pad to the next four byte
boundary). This is for compatibility with ARM's own assembler.
<p><a name="index-_0040code_007breq_007d-directive_002c-ARM-603"></a><br><dt><var>name</var><code> .req </code><var>register name</var><dd>This creates an alias for <var>register name</var> called <var>name</var>. For
example:
<pre class="smallexample"> foo .req r0
</pre>
<p><a name="index-_0040code_007bunreq_007d-directive_002c-ARM-604"></a><br><dt><code>.unreq </code><var>alias-name</var><dd>This undefines a register alias which was previously defined using the
<code>req</code>, <code>dn</code> or <code>qn</code> directives. For example:
<pre class="smallexample"> foo .req r0
.unreq foo
</pre>
<p>An error occurs if the name is undefined. Note - this pseudo op can
be used to delete builtin in register name aliases (eg 'r0'). This
should only be done if it is really necessary.
<p><a name="index-_0040code_007bdn_007d-and-_0040code_007bqn_007d-directives_002c-ARM-605"></a><br><dt><var>name</var><code> .dn </code><var>register name</var><code> [</code><var>.type</var><code>] [[</code><var>index</var><code>]]</code><br><dt><var>name</var><code> .qn </code><var>register name</var><code> [</code><var>.type</var><code>] [[</code><var>index</var><code>]]</code><dd>
The <code>dn</code> and <code>qn</code> directives are used to create typed
and/or indexed register aliases for use in Advanced SIMD Extension
(Neon) instructions. The former should be used to create aliases
of double-precision registers, and the latter to create aliases of
quad-precision registers.
<p>If these directives are used to create typed aliases, those aliases can
be used in Neon instructions instead of writing types after the mnemonic
or after each operand. For example:
<pre class="smallexample"> x .dn d2.f32
y .dn d3.f32
z .dn d4.f32[1]
vmul x,y,z
</pre>
<p>This is equivalent to writing the following:
<pre class="smallexample"> vmul.f32 d2,d3,d4[1]
</pre>
<p>Aliases created using <code>dn</code> or <code>qn</code> can be destroyed using
<code>unreq</code>.
<p><a name="index-_0040code_007bcode_007d-directive_002c-ARM-606"></a><br><dt><code>.code [16|32]</code><dd>This directive selects the instruction set being generated. The value 16
selects Thumb, with the value 32 selecting ARM.
<p><a name="index-_0040code_007bthumb_007d-directive_002c-ARM-607"></a><br><dt><code>.thumb</code><dd>This performs the same action as <var>.code 16</var>.
<p><a name="index-_0040code_007barm_007d-directive_002c-ARM-608"></a><br><dt><code>.arm</code><dd>This performs the same action as <var>.code 32</var>.
<p><a name="index-_0040code_007bforce_005fthumb_007d-directive_002c-ARM-609"></a><br><dt><code>.force_thumb</code><dd>This directive forces the selection of Thumb instructions, even if the
target processor does not support those instructions
<p><a name="index-_0040code_007bthumb_005ffunc_007d-directive_002c-ARM-610"></a><br><dt><code>.thumb_func</code><dd>This directive specifies that the following symbol is the name of a
Thumb encoded function. This information is necessary in order to allow
the assembler and linker to generate correct code for interworking
between Arm and Thumb instructions and should be used even if
interworking is not going to be performed. The presence of this
directive also implies <code>.thumb</code>
<p>This directive is not neccessary when generating EABI objects. On these
targets the encoding is implicit when generating Thumb code.
<p><a name="index-_0040code_007bthumb_005fset_007d-directive_002c-ARM-611"></a><br><dt><code>.thumb_set</code><dd>This performs the equivalent of a <code>.set</code> directive in that it
creates a symbol which is an alias for another symbol (possibly not yet
defined). This directive also has the added property in that it marks
the aliased symbol as being a thumb function entry point, in the same
way that the <code>.thumb_func</code> directive does.
<p><a name="index-_0040code_007b_002eltorg_007d-directive_002c-ARM-612"></a><br><dt><code>.ltorg</code><dd>This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
<code>GAS</code> maintains a separate literal pool for each section and each
sub-section. The <code>.ltorg</code> directive will only affect the literal
pool of the current section and sub-section. At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
<p>Note - older versions of <code>GAS</code> would dump the current literal
pool any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
<p><a name="index-_0040code_007b_002epool_007d-directive_002c-ARM-613"></a><br><dt><code>.pool</code><dd>This is a synonym for .ltorg.
<p><a name="arm_005ffnstart"></a>
<a name="index-_0040code_007b_002efnstart_007d-directive_002c-ARM-614"></a><br><dt><code>.fnstart</code><dd>Marks the start of a function with an unwind table entry.
<p><a name="arm_005ffnend"></a>
<a name="index-_0040code_007b_002efnend_007d-directive_002c-ARM-615"></a><br><dt><code>.fnend</code><dd>Marks the end of a function with an unwind table entry. The unwind index
table entry is created when this directive is processed.
<p>If no personality routine has been specified then standard personality
routine 0 or 1 will be used, depending on the number of unwind opcodes
required.
<p><a name="index-_0040code_007b_002ecantunwind_007d-directive_002c-ARM-616"></a><br><dt><code>.cantunwind</code><dd>Prevents unwinding through the current function. No personality routine
or exception table data is required or permitted.
<p><a name="index-_0040code_007b_002epersonality_007d-directive_002c-ARM-617"></a><br><dt><code>.personality </code><var>name</var><dd>Sets the personality routine for the current function to <var>name</var>.
<p><a name="index-_0040code_007b_002epersonalityindex_007d-directive_002c-ARM-618"></a><br><dt><code>.personalityindex </code><var>index</var><dd>Sets the personality routine for the current function to the EABI standard
routine number <var>index</var>
<p><a name="index-_0040code_007b_002ehandlerdata_007d-directive_002c-ARM-619"></a><br><dt><code>.handlerdata</code><dd>Marks the end of the current function, and the start of the exception table
entry for that function. Anything between this directive and the
<code>.fnend</code> directive will be added to the exception table entry.
<p>Must be preceded by a <code>.personality</code> or <code>.personalityindex</code>
directive.
<p><a name="arm_005fsave"></a>
<a name="index-_0040code_007b_002esave_007d-directive_002c-ARM-620"></a><br><dt><code>.save </code><var>reglist</var><dd>Generate unwinder annotations to restore the registers in <var>reglist</var>.
The format of <var>reglist</var> is the same as the corresponding store-multiple
instruction.
<pre class="smallexample"> <br><em>core registers</em><br>
.save {r4, r5, r6, lr}
stmfd sp!, {r4, r5, r6, lr}
<br><em>FPA registers</em><br>
.save f4, 2
sfmfd f4, 2, [sp]!
<br><em>VFP registers</em><br>
.save {d8, d9, d10}
fstmdx sp!, {d8, d9, d10}
<br><em>iWMMXt registers</em><br>
.save {wr10, wr11}
wstrd wr11, [sp, #-8]!
wstrd wr10, [sp, #-8]!
or
.save wr11
wstrd wr11, [sp, #-8]!
.save wr10
wstrd wr10, [sp, #-8]!
</pre>
<p><a name="index-_0040code_007b_002evsave_007d-directive_002c-ARM-621"></a><br><dt><code>.vsave </code><var>vfp-reglist</var><dd>Generate unwinder annotations to restore the VFP registers in <var>vfp-reglist</var>
using FLDMD. Also works for VFPv3 registers
that are to be restored using VLDM.
The format of <var>vfp-reglist</var> is the same as the corresponding store-multiple
instruction.
<pre class="smallexample"> <br><em>VFP registers</em><br>
.vsave {d8, d9, d10}
fstmdd sp!, {d8, d9, d10}
<br><em>VFPv3 registers</em><br>
.vsave {d15, d16, d17}
vstm sp!, {d15, d16, d17}
</pre>
<p>Since FLDMX and FSTMX are now deprecated, this directive should be
used in favour of <code>.save</code> for saving VFP registers for ARMv6 and above.
<p><a name="arm_005fpad"></a>
<a name="index-_0040code_007b_002epad_007d-directive_002c-ARM-622"></a><br><dt><code>.pad #</code><var>count</var><dd>Generate unwinder annotations for a stack adjustment of <var>count</var> bytes.
A positive value indicates the function prologue allocated stack space by
decrementing the stack pointer.
<p><a name="arm_005fmovsp"></a>
<a name="index-_0040code_007b_002emovsp_007d-directive_002c-ARM-623"></a><br><dt><code>.movsp </code><var>reg</var><code> [, #</code><var>offset</var><code>]</code><dd>Tell the unwinder that <var>reg</var> contains an offset from the current
stack pointer. If <var>offset</var> is not specified then it is assumed to be
zero.
<p><a name="arm_005fsetfp"></a>
<a name="index-_0040code_007b_002esetfp_007d-directive_002c-ARM-624"></a><br><dt><code>.setfp </code><var>fpreg</var><code>, </code><var>spreg</var><code> [, #</code><var>offset</var><code>]</code><dd>Make all unwinder annotations relaive to a frame pointer. Without this
the unwinder will use offsets from the stack pointer.
<p>The syntax of this directive is the same as the <code>sub</code> or <code>mov</code>
instruction used to set the frame pointer. <var>spreg</var> must be either
<code>sp</code> or mentioned in a previous <code>.movsp</code> directive.
<pre class="smallexample"> .movsp ip
mov ip, sp
...
.setfp fp, ip, #4
sub fp, ip, #4
</pre>
<p><a name="index-_0040code_007b_002eunwind_005fraw_007d-directive_002c-ARM-625"></a><br><dt><code>.raw </code><var>offset</var><code>, </code><var>byte1</var><code>, ...</code><dd>Insert one of more arbitary unwind opcode bytes, which are known to adjust
the stack pointer by <var>offset</var> bytes.
<p>For example <code>.unwind_raw 4, 0xb1, 0x01</code> is equivalent to
<code>.save {r0}</code>
<p><a name="index-_0040code_007b_002ecpu_007d-directive_002c-ARM-626"></a><br><dt><code>.cpu </code><var>name</var><dd>Select the target processor. Valid values for <var>name</var> are the same as
for the <span class="option">-mcpu</span> commandline option.
<p><a name="index-_0040code_007b_002earch_007d-directive_002c-ARM-627"></a><br><dt><code>.arch </code><var>name</var><dd>Select the target architecture. Valid values for <var>name</var> are the same as
for the <span class="option">-march</span> commandline option.
<p><a name="index-_0040code_007b_002eobject_005farch_007d-directive_002c-ARM-628"></a><br><dt><code>.object_arch </code><var>name</var><dd>Override the architecture recorded in the EABI object attribute section.
Valid values for <var>name</var> are the same as for the <code>.arch</code> directive.
Typically this is useful when code uses runtime detection of CPU features.
<p><a name="index-_0040code_007b_002efpu_007d-directive_002c-ARM-629"></a><br><dt><code>.fpu </code><var>name</var><dd>Select the floating point unit to assemble for. Valid values for <var>name</var>
are the same as for the <span class="option">-mfpu</span> commandline option.
<p><a name="index-_0040code_007b_002eeabi_005fattribute_007d-directive_002c-ARM-630"></a><br><dt><code>.eabi_attribute </code><var>tag</var><code>, </code><var>value</var><dd>Set the EABI object attribute number <var>tag</var> to <var>value</var>. The value
is either a <code>number</code>, <code>"string"</code>, or <code>number, "string"</code>
depending on the tag.
</dl>
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