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<a name="SH-Opcodes"></a>Previous: <a rel="previous" accesskey="p" href="SH-Directives.html#SH-Directives">SH Directives</a>,
Up: <a rel="up" accesskey="u" href="SH_002dDependent.html#SH_002dDependent">SH-Dependent</a>
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<h4 class="subsection">9.28.5 Opcodes</h4>
<p><a name="index-SH-opcode-summary-1463"></a><a name="index-opcode-summary_002c-SH-1464"></a><a name="index-mnemonics_002c-SH-1465"></a><a name="index-instruction-summary_002c-SH-1466"></a>For detailed information on the SH machine instruction set, see
<cite>SH-Microcomputer User's Manual</cite> (Renesas) or
<cite>SH-4 32-bit CPU Core Architecture</cite> (SuperH) and
<cite>SuperH (SH) 64-Bit RISC Series</cite> (SuperH).
<p><code>as</code> implements all the standard SH opcodes. No additional
pseudo-instructions are needed on this family. Note, however, that
because <code>as</code> supports a simpler form of PC-relative
addressing, you may simply write (for example)
<pre class="example"> mov.l bar,r0
</pre>
<p class="noindent">where other assemblers might require an explicit displacement to
<code>bar</code> from the program counter:
<pre class="example"> mov.l @(<var>disp</var>, PC)
</pre>
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