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324 lines
11 KiB
Diff
324 lines
11 KiB
Diff
Index: gcc/config/avr/avr.md
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===================================================================
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--- gcc/config/avr/avr.md (revision 129892)
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+++ gcc/config/avr/avr.md (working copy)
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@@ -45,21 +45,22 @@
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(REG_SP 32)
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(TMP_REGNO 0) ; temporary register r0
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(ZERO_REGNO 1) ; zero register r1
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(SREG_ADDR 0x5F)
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(RAMPZ_ADDR 0x5B)
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(UNSPEC_STRLEN 0)
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(UNSPEC_INDEX_JMP 1)
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(UNSPEC_SEI 2)
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(UNSPEC_CLI 3)
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+ (UNSPEC_SWAP 4)
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(UNSPECV_PROLOGUE_SAVES 0)
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(UNSPECV_EPILOGUE_RESTORES 1)])
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(include "predicates.md")
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(include "constraints.md")
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;; Condition code settings.
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(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
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(const_string "none"))
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@@ -1185,20 +1186,33 @@
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return (AS2 (andi, %A0,lo8(%2)) CR_TAB
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AS2 (andi, %B0,hi8(%2)) CR_TAB
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AS2 (andi, %C0,hlo8(%2)) CR_TAB
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AS2 (andi, %D0,hhi8(%2)));
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}
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return \"bug\";
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}"
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[(set_attr "length" "4,4")
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(set_attr "cc" "set_n,set_n")])
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+(define_peephole2 ; andi
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+ [(set (match_operand:QI 0 "d_register_operand" "")
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+ (and:QI (match_dup 0)
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+ (match_operand:QI 1 "const_int_operand" "")))
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+ (set (match_dup 0)
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+ (and:QI (match_dup 0)
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+ (match_operand:QI 2 "const_int_operand" "")))]
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+ ""
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+ [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
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+ {
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+ operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
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+ })
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+
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;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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;; ior
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(define_insn "iorqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,d")
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(ior:QI (match_operand:QI 1 "register_operand" "%0,0")
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(match_operand:QI 2 "nonmemory_operand" "r,i")))]
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""
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"@
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or %0,%2
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@@ -1313,24 +1327,71 @@
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(xor:SI (match_operand:SI 1 "register_operand" "%0")
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(match_operand:SI 2 "register_operand" "r")))]
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""
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"eor %0,%2
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eor %B0,%B2
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eor %C0,%C2
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eor %D0,%D2"
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[(set_attr "length" "4")
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(set_attr "cc" "set_n")])
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+;; swap
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+
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+(define_insn "*swap"
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+ [(set (match_operand:QI 0 "register_operand" "=r")
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+ (unspec:QI [(match_operand:QI 1 "register_operand" "0")]
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+ UNSPEC_SWAP))]
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+ ""
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+ "swap %0"
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+ [(set_attr "length" "1")
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+ (set_attr "cc" "none")])
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+
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;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
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;; arithmetic shift left
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-(define_insn "ashlqi3"
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+(define_expand "ashlqi3"
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+ [(set (match_operand:QI 0 "register_operand" "")
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+ (ashift:QI (match_operand:QI 1 "register_operand" "")
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+ (match_operand:QI 2 "general_operand" "")))]
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+ ""
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+ "")
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+
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+(define_split ; ashlqi3_const4
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+ [(set (match_operand:QI 0 "d_register_operand" "")
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+ (ashift:QI (match_operand:QI 1 "d_register_operand" "")
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+ (const_int 4)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
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+ "")
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+
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+(define_split ; ashlqi3_const5
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+ [(set (match_operand:QI 0 "d_register_operand" "")
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+ (ashift:QI (match_operand:QI 1 "d_register_operand" "")
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+ (const_int 5)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
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+ (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
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+ "")
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+
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+(define_split ; ashlqi3_const6
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+ [(set (match_operand:QI 0 "d_register_operand" "")
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+ (ashift:QI (match_operand:QI 1 "d_register_operand" "")
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+ (const_int 6)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
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+ (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
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+ "")
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+
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+(define_insn "*ashlqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
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(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
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""
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"* return ashlqi3_out (insn, operands, NULL);"
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[(set_attr "length" "5,0,1,2,4,6,9")
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(set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
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(define_insn "ashlhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
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@@ -1346,20 +1407,61 @@
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(ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
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""
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"* return ashlsi3_out (insn, operands, NULL);"
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[(set_attr "length" "8,0,4,4,8,10,12")
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(set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
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;; Optimize if a scratch register from LD_REGS happens to be available.
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(define_peephole2
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+ [(match_scratch:QI 2 "d")
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+ (set (match_operand:QI 0 "l_register_operand" "")
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+ (ashift:QI (match_operand:QI 1 "l_register_operand" "")
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+ (const_int 4)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 2) (const_int -16))
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+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 2)))
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+ (clobber (match_dup 2))]
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+ "if (!avr_peep2_scratch_safe (operands[2]))
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+ FAIL;")
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+
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+(define_peephole2
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+ [(match_scratch:QI 2 "d")
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+ (set (match_operand:QI 0 "l_register_operand" "")
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+ (ashift:QI (match_operand:QI 1 "l_register_operand" "")
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+ (const_int 5)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
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+ (set (match_dup 2) (const_int -32))
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+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 2)))
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+ (clobber (match_dup 2))]
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+ "if (!avr_peep2_scratch_safe (operands[2]))
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+ FAIL;")
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+
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+(define_peephole2
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+ [(match_scratch:QI 2 "d")
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+ (set (match_operand:QI 0 "l_register_operand" "")
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+ (ashift:QI (match_operand:QI 1 "l_register_operand" "")
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+ (const_int 6)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
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+ (set (match_dup 2) (const_int -64))
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+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 2)))
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+ (clobber (match_dup 2))]
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+ "if (!avr_peep2_scratch_safe (operands[2]))
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+ FAIL;")
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+
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+(define_peephole2
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[(match_scratch:QI 3 "d")
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(set (match_operand:HI 0 "register_operand" "")
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(ashift:HI (match_operand:HI 1 "register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))]
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""
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[(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
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(clobber (match_dup 3))])]
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"if (!avr_peep2_scratch_safe (operands[3]))
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FAIL;")
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@@ -1464,21 +1566,63 @@
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(match_operand:QI 2 "const_int_operand" "L,P,O,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
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"reload_completed"
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"* return ashrsi3_out (insn, operands, NULL);"
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[(set_attr "length" "0,4,4,10")
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(set_attr "cc" "none,clobber,set_n,clobber")])
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;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
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;; logical shift right
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-(define_insn "lshrqi3"
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+(define_expand "lshrqi3"
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+ [(set (match_operand:QI 0 "register_operand" "")
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+ (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
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+ (match_operand:QI 2 "general_operand" "")))]
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+ ""
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+ "")
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+
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+(define_insn_and_split "*lshrqi3_const4"
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+ [(set (match_operand:QI 0 "d_register_operand" "=d")
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+ (lshiftrt:QI (match_operand:QI 1 "d_register_operand" "0")
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+ (const_int 4)))]
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+ ""
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+ "#"
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
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+ "")
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+
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+(define_insn_and_split "*lshrqi3_const5"
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+ [(set (match_operand:QI 0 "d_register_operand" "=d")
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+ (lshiftrt:QI (match_operand:QI 1 "d_register_operand" "0")
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+ (const_int 5)))]
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+ ""
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+ "#"
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
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+ (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
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+ "")
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+
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+(define_insn_and_split "*lshrqi3_const6"
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+ [(set (match_operand:QI 0 "d_register_operand" "=d")
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+ (lshiftrt:QI (match_operand:QI 1 "d_register_operand" "0")
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+ (const_int 6)))]
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+ ""
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+ "#"
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
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+ (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
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+ "")
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+
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+(define_insn "*lshrqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
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(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
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""
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"* return lshrqi3_out (insn, operands, NULL);"
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[(set_attr "length" "5,0,1,2,4,6,9")
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(set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
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(define_insn "lshrhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
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@@ -1494,20 +1638,61 @@
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(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
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""
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"* return lshrsi3_out (insn, operands, NULL);"
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[(set_attr "length" "8,0,4,4,8,10,12")
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(set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
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;; Optimize if a scratch register from LD_REGS happens to be available.
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(define_peephole2
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+ [(match_scratch:QI 2 "d")
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+ (set (match_operand:QI 0 "l_register_operand" "")
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+ (lshiftrt:QI (match_operand:QI 1 "l_register_operand" "")
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+ (const_int 4)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 2) (const_int 15))
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+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 2)))
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+ (clobber (match_dup 2))]
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+ "if (!avr_peep2_scratch_safe (operands[2]))
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+ FAIL;")
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+
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+(define_peephole2
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+ [(match_scratch:QI 2 "d")
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+ (set (match_operand:QI 0 "l_register_operand" "")
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+ (lshiftrt:QI (match_operand:QI 1 "l_register_operand" "")
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+ (const_int 5)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
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+ (set (match_dup 2) (const_int 7))
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+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 2)))
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+ (clobber (match_dup 2))]
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+ "if (!avr_peep2_scratch_safe (operands[2]))
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+ FAIL;")
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+
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+(define_peephole2
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+ [(match_scratch:QI 2 "d")
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+ (set (match_operand:QI 0 "l_register_operand" "")
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+ (lshiftrt:QI (match_operand:QI 1 "l_register_operand" "")
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+ (const_int 6)))]
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+ ""
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+ [(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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+ (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
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+ (set (match_dup 2) (const_int 3))
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+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 2)))
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+ (clobber (match_dup 2))]
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+ "if (!avr_peep2_scratch_safe (operands[2]))
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+ FAIL;")
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+
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+(define_peephole2
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[(match_scratch:QI 3 "d")
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(set (match_operand:HI 0 "register_operand" "")
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(lshiftrt:HI (match_operand:HI 1 "register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))]
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""
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[(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
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(clobber (match_dup 3))])]
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"if (!avr_peep2_scratch_safe (operands[3]))
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FAIL;")
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