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87 lines
4.2 KiB
XML
87 lines
4.2 KiB
XML
<?xml version="1.0" ?>
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<Scheme>
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access after alias all architecture array assert attribute begin block body buffer bus case component
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configuration constant disconnect downto else elsif end entity exit file for function generate generic
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group guarded if impure in inertial inout is label library linkage literal loop map new next null of
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on open others out package port postponed procedure process pure range record register reject report
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return select severity shared signal subtype then to transport type unaffected units until use variable
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wait when while with
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<keyword-class name="operators">
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abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
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left right low high ascending image value pos val succ pred leftof rightof base range reverse_range
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length delayed stable quiet transaction event active last_event last_active last_value driving
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driving_value simple_name path_name instance_name
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</keyword-class>
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<keyword-class name="functions">
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now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector
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to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left
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rotate_right resize to_integer to_unsigned to_signed std_match to_01
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</keyword-class>
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std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed
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std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives
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vital_timing
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</keyword-class>
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<keyword-class name="types">
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boolean bit character severity_level integer real time delay_length natural positive string bit_vector
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file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic
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std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
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userword
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'base 'left 'right 'high 'low 'ascending 'image 'value 'pos
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'val 'succ 'pred 'leftof 'rightof 'range 'reverse_range 'length
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'delayed 'stable 'quiet 'transaction 'event 'last_event 'last_active
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'last_value 'driving 'driving_value 'simple_name 'instance_name 'path_name
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</keyword-class>
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<keyword-class name="vhdl3">
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std_logic std_logic_vector
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</keyword-class>
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<keyword-class name="vhdl4">
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string integer time
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</keyword-class>
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<keyword-class name="vhdl5">
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dummy
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</keyword-class>
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</keyword-classes>
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</Scheme> |