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<a name="Xtensa-Automatic-Alignment"></a>Previous: <a rel="previous" accesskey="p" href="Density-Instructions.html#Density-Instructions">Density Instructions</a>,
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Up: <a rel="up" accesskey="u" href="Xtensa-Optimizations.html#Xtensa-Optimizations">Xtensa Optimizations</a>
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<h5 class="subsubsection">9.36.3.2 Automatic Instruction Alignment</h5>
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<p><a name="index-alignment-of-_0040code_007bLOOP_007d-instructions-1859"></a><a name="index-alignment-of-branch-targets-1860"></a><a name="index-_0040code_007bLOOP_007d-instructions_002c-alignment-1861"></a><a name="index-branch-target-alignment-1862"></a>
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The Xtensa assembler will automatically align certain instructions, both
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to optimize performance and to satisfy architectural requirements.
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<p>As an optimization to improve performance, the assembler attempts to
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align branch targets so they do not cross instruction fetch boundaries.
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(Xtensa processors can be configured with either 32-bit or 64-bit
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instruction fetch widths.) An
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instruction immediately following a call is treated as a branch target
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in this context, because it will be the target of a return from the
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call. This alignment has the potential to reduce branch penalties at
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some expense in code size.
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This optimization is enabled by default. You can disable it with the
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<span class="samp">--no-target-align</span> command-line option (see <a href="Xtensa-Options.html#Xtensa-Options">Command Line Options</a>).
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<p>The target alignment optimization is done without adding instructions
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that could increase the execution time of the program. If there are
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density instructions in the code preceding a target, the assembler can
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change the target alignment by widening some of those instructions to
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the equivalent 24-bit instructions. Extra bytes of padding can be
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inserted immediately following unconditional jump and return
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instructions.
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This approach is usually successful in aligning many, but not all,
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branch targets.
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<p>The <code>LOOP</code> family of instructions must be aligned such that the
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first instruction in the loop body does not cross an instruction fetch
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boundary (e.g., with a 32-bit fetch width, a <code>LOOP</code> instruction
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must be on either a 1 or 2 mod 4 byte boundary). The assembler knows
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about this restriction and inserts the minimal number of 2 or 3 byte
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no-op instructions to satisfy it. When no-op instructions are added,
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any label immediately preceding the original loop will be moved in order
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to refer to the loop instruction, not the newly generated no-op
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instruction. To preserve binary compatibility across processors with
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different fetch widths, the assembler conservatively assumes a 32-bit
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fetch width when aligning <code>LOOP</code> instructions (except if the first
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instruction in the loop is a 64-bit instruction).
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<p>Previous versions of the assembler automatically aligned <code>ENTRY</code>
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instructions to 4-byte boundaries, but that alignment is now the
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programmer's responsibility.
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