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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
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2006, 2007 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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<p>
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<a name="ARC-Directives"></a>Next: <a rel="next" accesskey="n" href="ARC-Opcodes.html#ARC-Opcodes">ARC Opcodes</a>,
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Previous: <a rel="previous" accesskey="p" href="ARC-Floating-Point.html#ARC-Floating-Point">ARC Floating Point</a>,
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Up: <a rel="up" accesskey="u" href="ARC_002dDependent.html#ARC_002dDependent">ARC-Dependent</a>
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<h4 class="subsection">9.2.4 ARC Machine Directives</h4>
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<p><a name="index-machine-directives_002c-ARC-548"></a><a name="index-ARC-machine-directives-549"></a>The ARC version of <code>as</code> supports the following additional
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machine directives:
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<a name="index-_0040code_007b2byte_007d-directive_002c-ARC-550"></a>
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<dl><dt><code>.2byte </code><var>expressions</var><dd>*TODO*
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<p><a name="index-_0040code_007b3byte_007d-directive_002c-ARC-551"></a><br><dt><code>.3byte </code><var>expressions</var><dd>*TODO*
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<p><a name="index-_0040code_007b4byte_007d-directive_002c-ARC-552"></a><br><dt><code>.4byte </code><var>expressions</var><dd>*TODO*
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<p><a name="index-_0040code_007bextAuxRegister_007d-directive_002c-ARC-553"></a><br><dt><code>.extAuxRegister </code><var>name</var><code>,</code><var>address</var><code>,</code><var>mode</var><dd>The ARCtangent A4 has extensible auxiliary register space. The
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auxiliary registers can be defined in the assembler source code by
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using this directive. The first parameter is the <var>name</var> of the
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new auxiallry register. The second parameter is the <var>address</var> of
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the register in the auxiliary register memory map for the variant of
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the ARC. The third parameter specifies the <var>mode</var> in which the
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register can be operated is and it can be one of:
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<dl>
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<dt><code>r (readonly)</code><br><dt><code>w (write only)</code><br><dt><code>r|w (read or write)</code><dd></dl>
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<p>For example:
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<pre class="smallexample"> .extAuxRegister mulhi,0x12,w
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</pre>
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<p>This specifies an extension auxiliary register called <em>mulhi</em>
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which is at address 0x12 in the memory space and which is only
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writable.
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<p><a name="index-_0040code_007bextCondCode_007d-directive_002c-ARC-554"></a><br><dt><code>.extCondCode </code><var>suffix</var><code>,</code><var>value</var><dd>The condition codes on the ARCtangent A4 are extensible and can be
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specified by means of this assembler directive. They are specified
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by the suffix and the value for the condition code. They can be used to
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specify extra condition codes with any values. For example:
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<pre class="smallexample"> .extCondCode is_busy,0x14
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add.is_busy r1,r2,r3
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bis_busy _main
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</pre>
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<p><a name="index-_0040code_007bextCoreRegister_007d-directive_002c-ARC-555"></a><br><dt><code>.extCoreRegister </code><var>name</var><code>,</code><var>regnum</var><code>,</code><var>mode</var><code>,</code><var>shortcut</var><dd>Specifies an extension core register <var>name</var> for the application.
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This allows a register <var>name</var> with a valid <var>regnum</var> between 0
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and 60, with the following as valid values for <var>mode</var>
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<dl>
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<dt><em>r</em><span class="samp"> (readonly)</span><br><dt><em>w</em><span class="samp"> (write only)</span><br><dt><em>r|w</em><span class="samp"> (read or write)</span><dd></dl>
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<p>The other parameter gives a description of the register having a
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<var>shortcut</var> in the pipeline. The valid values are:
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<dl>
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<dt><code>can_shortcut</code><br><dt><code>cannot_shortcut</code><dd></dl>
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<p>For example:
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<pre class="smallexample"> .extCoreRegister mlo,57,r,can_shortcut
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</pre>
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<p>This defines an extension core register mlo with the value 57 which
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can shortcut the pipeline.
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<p><a name="index-_0040code_007bextInstruction_007d-directive_002c-ARC-556"></a><br><dt><code>.extInstruction </code><var>name</var><code>,</code><var>opcode</var><code>,</code><var>subopcode</var><code>,</code><var>suffixclass</var><code>,</code><var>syntaxclass</var><dd>The ARCtangent A4 allows the user to specify extension instructions.
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The extension instructions are not macros. The assembler creates
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encodings for use of these instructions according to the specification
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by the user. The parameters are:
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<dl>
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<dt>•<var>name</var><dd>Name of the extension instruction
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<br><dt>•<var>opcode</var><dd>Opcode to be used. (Bits 27:31 in the encoding). Valid values
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0x10-0x1f or 0x03
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<br><dt>•<var>subopcode</var><dd>Subopcode to be used. Valid values are from 0x09-0x3f. However the
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correct value also depends on <var>syntaxclass</var>
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<br><dt>•<var>suffixclass</var><dd>Determines the kinds of suffixes to be allowed. Valid values are
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<code>SUFFIX_NONE</code>, <code>SUFFIX_COND</code>,
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<code>SUFFIX_FLAG</code> which indicates the absence or presence of
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conditional suffixes and flag setting by the extension instruction.
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It is also possible to specify that an instruction sets the flags and
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is conditional by using <code>SUFFIX_CODE</code> | <code>SUFFIX_FLAG</code>.
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<br><dt>•<var>syntaxclass</var><dd>Determines the syntax class for the instruction. It can have the
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following values:
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<dl>
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<dt><code>SYNTAX_2OP:</code><dd>2 Operand Instruction
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<br><dt><code>SYNTAX_3OP:</code><dd>3 Operand Instruction
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</dl>
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<p>In addition there could be modifiers for the syntax class as described
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below:
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<ul>
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Syntax Class Modifiers are:
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<li><code>OP1_MUST_BE_IMM</code>:
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Modifies syntax class SYNTAX_3OP, specifying that the first operand
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of a three-operand instruction must be an immediate (i.e., the result
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is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
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SYNTAX_3OP as given in the example below. This could usually be used
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to set the flags using specific instructions and not retain results.
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<li><code>OP1_IMM_IMPLIED</code>:
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Modifies syntax class SYNTAX_20P, it specifies that there is an
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implied immediate destination operand which does not appear in the
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syntax. For example, if the source code contains an instruction like:
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<pre class="smallexample"> inst r1,r2
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</pre>
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<p>it really means that the first argument is an implied immediate (that
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is, the result is discarded). This is the same as though the source
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code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
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with SYNTAX_20P.
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</ul>
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</dl>
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<p>For example, defining 64-bit multiplier with immediate operands:
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<pre class="smallexample"> .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
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SYNTAX_3OP|OP1_MUST_BE_IMM
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</pre>
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<p>The above specifies an extension instruction called mp64 which has 3 operands,
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sets the flags, can be used with a condition code, for which the
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first operand is an immediate. (Equivalent to discarding the result
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of the operation).
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<pre class="smallexample"> .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
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</pre>
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<p>This describes a 2 operand instruction with an implicit first
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immediate operand. The result of this operation would be discarded.
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<p><a name="index-_0040code_007bhalf_007d-directive_002c-ARC-557"></a><br><dt><code>.half </code><var>expressions</var><dd>*TODO*
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<p><a name="index-_0040code_007blong_007d-directive_002c-ARC-558"></a><br><dt><code>.long </code><var>expressions</var><dd>*TODO*
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<p><a name="index-_0040code_007boption_007d-directive_002c-ARC-559"></a><br><dt><code>.option </code><var>arc|arc5|arc6|arc7|arc8</var><dd>The <code>.option</code> directive must be followed by the desired core
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version. Again <code>arc</code> is an alias for
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<code>arc6</code>.
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<p>Note: the <code>.option</code> directive overrides the command line option
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<code>-marc</code>; a warning is emitted when the version is not consistent
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between the two - even for the implicit default core version
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(arc6).
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<p><a name="index-_0040code_007bshort_007d-directive_002c-ARC-560"></a><br><dt><code>.short </code><var>expressions</var><dd>*TODO*
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<p><a name="index-_0040code_007bword_007d-directive_002c-ARC-561"></a><br><dt><code>.word </code><var>expressions</var><dd>*TODO*
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</dl>
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</body></html>
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