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This file documents the GNU Assembler "as".
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Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
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2006, 2007 Free Software Foundation, Inc.
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<a name="Directives_002di860"></a>Next: <a rel="next" accesskey="n" href="Opcodes-for-i860.html#Opcodes-for-i860">Opcodes for i860</a>,
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Previous: <a rel="previous" accesskey="p" href="Options_002di860.html#Options_002di860">Options-i860</a>,
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Up: <a rel="up" accesskey="u" href="i860_002dDependent.html#i860_002dDependent">i860-Dependent</a>
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<h4 class="subsection">9.14.3 i860 Machine Directives</h4>
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<p><a name="index-machine-directives_002c-i860-967"></a><a name="index-i860-machine-directives-968"></a>
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<a name="index-_0040code_007bdual_007d-directive_002c-i860-969"></a>
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<dl><dt><code>.dual</code><dd>Enter dual instruction mode. While this directive is supported, the
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preferred way to use dual instruction mode is to explicitly code
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the dual bit with the <code>d.</code> prefix.
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</dl>
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<a name="index-_0040code_007benddual_007d-directive_002c-i860-970"></a>
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<dl><dt><code>.enddual</code><dd>Exit dual instruction mode. While this directive is supported, the
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preferred way to use dual instruction mode is to explicitly code
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the dual bit with the <code>d.</code> prefix.
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</dl>
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<a name="index-_0040code_007batmp_007d-directive_002c-i860-971"></a>
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<dl><dt><code>.atmp</code><dd>Change the temporary register used when expanding pseudo operations. The
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default register is <code>r31</code>.
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</dl>
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<p>The <code>.dual</code>, <code>.enddual</code>, and <code>.atmp</code> directives are available only in the Intel syntax mode.
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<p>Both syntaxes allow for the standard <code>.align</code> directive. However,
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the Intel syntax additionally allows keywords for the alignment
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parameter: "<code>.align type</code>", where `type' is one of <code>.short</code>, <code>.long</code>,
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<code>.quad</code>, <code>.single</code>, <code>.double</code> representing alignments of 2, 4,
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16, 4, and 8, respectively.
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