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<p>
<a name="MIPS-Opts"></a>Next:&nbsp;<a rel="next" accesskey="n" href="MIPS-Object.html#MIPS-Object">MIPS Object</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="MIPS_002dDependent.html#MIPS_002dDependent">MIPS-Dependent</a>
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<h4 class="subsection">9.22.1 Assembler options</h4>
<p>The <span class="sc">mips</span> configurations of <span class="sc">gnu</span> <code>as</code> support these
special options:
<a name="index-_0040code_007b_002dG_007d-option-_0028MIPS_0029-1194"></a>
<dl><dt><code>-G </code><var>num</var><dd>This option sets the largest size of an object that can be referenced
implicitly with the <code>gp</code> register. It is only accepted for targets
that use <span class="sc">ecoff</span> format. The default value is 8.
<p><a name="index-_0040code_007b_002dEB_007d-option-_0028MIPS_0029-1195"></a><a name="index-_0040code_007b_002dEL_007d-option-_0028MIPS_0029-1196"></a><a name="index-MIPS-big_002dendian-output-1197"></a><a name="index-MIPS-little_002dendian-output-1198"></a><a name="index-big_002dendian-output_002c-MIPS-1199"></a><a name="index-little_002dendian-output_002c-MIPS-1200"></a><br><dt><code>-EB</code><dt><code>-EL</code><dd>Any <span class="sc">mips</span> configuration of <code>as</code> can select big-endian or
little-endian output at run time (unlike the other <span class="sc">gnu</span> development
tools, which must be configured for one or the other). Use <span class="samp">-EB</span>
to select big-endian output, and <span class="samp">-EL</span> for little-endian.
<br><dt><code>-KPIC</code><dd><a name="index-PIC-selection_002c-MIPS-1201"></a><a name="index-_0040option_007b_002dKPIC_007d-option_002c-MIPS-1202"></a>Generate SVR4-style PIC. This option tells the assembler to generate
SVR4-style position-independent macro expansions. It also tells the
assembler to mark the output file as PIC.
<br><dt><code>-mvxworks-pic</code><dd><a name="index-_0040option_007b_002dmvxworks_002dpic_007d-option_002c-MIPS-1203"></a>Generate VxWorks PIC. This option tells the assembler to generate
VxWorks-style position-independent macro expansions.
<p><a name="index-MIPS-architecture-options-1204"></a><br><dt><code>-mips1</code><dt><code>-mips2</code><dt><code>-mips3</code><dt><code>-mips4</code><dt><code>-mips5</code><dt><code>-mips32</code><dt><code>-mips32r2</code><dt><code>-mips64</code><dt><code>-mips64r2</code><dd>Generate code for a particular MIPS Instruction Set Architecture level.
<span class="samp">-mips1</span> corresponds to the <span class="sc">r2000</span> and <span class="sc">r3000</span> processors,
<span class="samp">-mips2</span> to the <span class="sc">r6000</span> processor, <span class="samp">-mips3</span> to the
<span class="sc">r4000</span> processor, and <span class="samp">-mips4</span> to the <span class="sc">r8000</span> and
<span class="sc">r10000</span> processors. <span class="samp">-mips5</span>, <span class="samp">-mips32</span>, <span class="samp">-mips32r2</span>,
<span class="samp">-mips64</span>, and <span class="samp">-mips64r2</span>
correspond to generic
<span class="sc">MIPS V</span>, <span class="sc">MIPS32</span>, <span class="sc">MIPS32 Release 2</span>, <span class="sc">MIPS64</span>,
and <span class="sc">MIPS64 Release 2</span>
ISA processors, respectively. You can also switch
instruction sets during the assembly; see <a href="MIPS-ISA.html#MIPS-ISA">Directives to override the ISA level</a>.
<br><dt><code>-mgp32</code><dt><code>-mfp32</code><dd>Some macros have different expansions for 32-bit and 64-bit registers.
The register sizes are normally inferred from the ISA and ABI, but these
flags force a certain group of registers to be treated as 32 bits wide at
all times. <span class="samp">-mgp32</span> controls the size of general-purpose registers
and <span class="samp">-mfp32</span> controls the size of floating-point registers.
<p>The <code>.set gp=32</code> and <code>.set fp=32</code> directives allow the size
of registers to be changed for parts of an object. The default value is
restored by <code>.set gp=default</code> and <code>.set fp=default</code>.
<p>On some MIPS variants there is a 32-bit mode flag; when this flag is
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
save the 32-bit registers on a context switch, so it is essential never
to use the 64-bit registers.
<br><dt><code>-mgp64</code><dt><code>-mfp64</code><dd>Assume that 64-bit registers are available. This is provided in the
interests of symmetry with <span class="samp">-mgp32</span> and <span class="samp">-mfp32</span>.
<p>The <code>.set gp=64</code> and <code>.set fp=64</code> directives allow the size
of registers to be changed for parts of an object. The default value is
restored by <code>.set gp=default</code> and <code>.set fp=default</code>.
<br><dt><code>-mips16</code><dt><code>-no-mips16</code><dd>Generate code for the MIPS 16 processor. This is equivalent to putting
<code>.set mips16</code> at the start of the assembly file. <span class="samp">-no-mips16</span>
turns off this option.
<br><dt><code>-msmartmips</code><dt><code>-mno-smartmips</code><dd>Enables the SmartMIPS extensions to the MIPS32 instruction set, which
provides a number of new instructions which target smartcard and
cryptographic applications. This is equivalent to putting
<code>.set smartmips</code> at the start of the assembly file.
<span class="samp">-mno-smartmips</span> turns off this option.
<br><dt><code>-mips3d</code><dt><code>-no-mips3d</code><dd>Generate code for the MIPS-3D Application Specific Extension.
This tells the assembler to accept MIPS-3D instructions.
<span class="samp">-no-mips3d</span> turns off this option.
<br><dt><code>-mdmx</code><dt><code>-no-mdmx</code><dd>Generate code for the MDMX Application Specific Extension.
This tells the assembler to accept MDMX instructions.
<span class="samp">-no-mdmx</span> turns off this option.
<br><dt><code>-mdsp</code><dt><code>-mno-dsp</code><dd>Generate code for the DSP Release 1 Application Specific Extension.
This tells the assembler to accept DSP Release 1 instructions.
<span class="samp">-mno-dsp</span> turns off this option.
<br><dt><code>-mdspr2</code><dt><code>-mno-dspr2</code><dd>Generate code for the DSP Release 2 Application Specific Extension.
This option implies -mdsp.
This tells the assembler to accept DSP Release 2 instructions.
<span class="samp">-mno-dspr2</span> turns off this option.
<br><dt><code>-mmt</code><dt><code>-mno-mt</code><dd>Generate code for the MT Application Specific Extension.
This tells the assembler to accept MT instructions.
<span class="samp">-mno-mt</span> turns off this option.
<br><dt><code>-mfix7000</code><dt><code>-mno-fix7000</code><dd>Cause nops to be inserted if the read of the destination register
of an mfhi or mflo instruction occurs in the following two instructions.
<br><dt><code>-mfix-vr4120</code><dt><code>-no-mfix-vr4120</code><dd>Insert nops to work around certain VR4120 errata. This option is
intended to be used on GCC-generated code: it is not designed to catch
all problems in hand-written assembler code.
<br><dt><code>-mfix-vr4130</code><dt><code>-no-mfix-vr4130</code><dd>Insert nops to work around the VR4130 <span class="samp">mflo</span>/<span class="samp">mfhi</span> errata.
<br><dt><code>-m4010</code><dt><code>-no-m4010</code><dd>Generate code for the LSI <span class="sc">r4010</span> chip. This tells the assembler to
accept the <span class="sc">r4010</span> specific instructions (<span class="samp">addciu</span>, <span class="samp">ffc</span>,
etc.), and to not schedule <span class="samp">nop</span> instructions around accesses to
the <span class="samp">HI</span> and <span class="samp">LO</span> registers. <span class="samp">-no-m4010</span> turns off this
option.
<br><dt><code>-m4650</code><dt><code>-no-m4650</code><dd>Generate code for the MIPS <span class="sc">r4650</span> chip. This tells the assembler to accept
the <span class="samp">mad</span> and <span class="samp">madu</span> instruction, and to not schedule <span class="samp">nop</span>
instructions around accesses to the <span class="samp">HI</span> and <span class="samp">LO</span> registers.
<span class="samp">-no-m4650</span> turns off this option.
<dt><code>-m3900</code><dt><code>-no-m3900</code><dt><code>-m4100</code><dt><code>-no-m4100</code><dd>For each option <span class="samp">-m</span><var>nnnn</var>, generate code for the MIPS
<span class="sc">r</span><var>nnnn</var> chip. This tells the assembler to accept instructions
specific to that chip, and to schedule for that chip's hazards.
<br><dt><code>-march=</code><var>cpu</var><dd>Generate code for a particular MIPS cpu. It is exactly equivalent to
<span class="samp">-m</span><var>cpu</var>, except that there are more value of <var>cpu</var>
understood. Valid <var>cpu</var> value are:
<blockquote>
2000,
3000,
3900,
4000,
4010,
4100,
4111,
vr4120,
vr4130,
vr4181,
4300,
4400,
4600,
4650,
5000,
rm5200,
rm5230,
rm5231,
rm5261,
rm5721,
vr5400,
vr5500,
6000,
rm7000,
8000,
rm9000,
10000,
12000,
4kc,
4km,
4kp,
4ksc,
4kec,
4kem,
4kep,
4ksd,
m4k,
m4kp,
24kc,
24kf2_1,
24kf,
24kf1_1,
24kec,
24kef2_1,
24kef,
24kef1_1,
34kc,
34kf2_1,
34kf,
34kf1_1,
74kc,
74kf2_1,
74kf,
74kf1_1,
74kf3_2,
5kc,
5kf,
20kc,
25kf,
sb1,
sb1a,
loongson2e,
loongson2f,
octeon
</blockquote>
<p>For compatibility reasons, <var>n</var><span class="samp">x</span> and <var>b</var><span class="samp">fx</span> are
accepted as synonyms for <var>n</var><span class="samp">f1_1</span>. These values are
deprecated.
<br><dt><code>-mtune=</code><var>cpu</var><dd>Schedule and tune for a particular MIPS cpu. Valid <var>cpu</var> values are
identical to <span class="samp">-march=</span><var>cpu</var>.
<br><dt><code>-mabi=</code><var>abi</var><dd>Record which ABI the source code uses. The recognized arguments
are: <span class="samp">32</span>, <span class="samp">n32</span>, <span class="samp">o64</span>, <span class="samp">64</span> and <span class="samp">eabi</span>.
<br><dt><code>-msym32</code><dt><code>-mno-sym32</code><dd><a name="index-_002dmsym32-1205"></a><a name="index-_002dmno_002dsym32-1206"></a>Equivalent to adding <code>.set sym32</code> or <code>.set nosym32</code> to
the beginning of the assembler input. See <a href="MIPS-symbol-sizes.html#MIPS-symbol-sizes">MIPS symbol sizes</a>.
<p><a name="index-_0040code_007b_002dnocpp_007d-ignored-_0028MIPS_0029-1207"></a><br><dt><code>-nocpp</code><dd>This option is ignored. It is accepted for command-line compatibility with
other assemblers, which use it to turn off C style preprocessing. With
<span class="sc">gnu</span> <code>as</code>, there is no need for <span class="samp">-nocpp</span>, because the
<span class="sc">gnu</span> assembler itself never runs the C preprocessor.
<br><dt><code>-msoft-float</code><dt><code>-mhard-float</code><dd>Disable or enable floating-point instructions. Note that by default
floating-point instructions are always allowed even with CPU targets
that don't have support for these instructions.
<br><dt><code>-msingle-float</code><dt><code>-mdouble-float</code><dd>Disable or enable double-precision floating-point operations. Note
that by default double-precision floating-point operations are always
allowed even with CPU targets that don't have support for these
operations.
<br><dt><code>--construct-floats</code><dt><code>--no-construct-floats</code><dd>The <code>--no-construct-floats</code> option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
the double width register. This feature is useful if the processor
support the FR bit in its status register, and this bit is known (by
the programmer) to be set. This bit prevents the aliasing of the double
width register by the single width registers.
<p>By default <code>--construct-floats</code> is selected, allowing construction
of these floating point constants.
<br><dt><code>--trap</code><dt><code>--no-break</code><dd><!-- FIXME! (1) reflect these options (next item too) in option summaries; -->
<!-- (2) stop teasing, say _which_ instructions expanded _how_. -->
<code>as</code> automatically macro expands certain division and
multiplication instructions to check for overflow and division by zero. This
option causes <code>as</code> to generate code to take a trap exception
rather than a break exception when an error is detected. The trap instructions
are only supported at Instruction Set Architecture level 2 and higher.
<br><dt><code>--break</code><dt><code>--no-trap</code><dd>Generate code to take a break exception rather than a trap exception when an
error is detected. This is the default.
<br><dt><code>-mpdr</code><dt><code>-mno-pdr</code><dd>Control generation of <code>.pdr</code> sections. Off by default on IRIX, on
elsewhere.
<br><dt><code>-mshared</code><dt><code>-mno-shared</code><dd>When generating code using the Unix calling conventions (selected by
<span class="samp">-KPIC</span> or <span class="samp">-mcall_shared</span>), gas will normally generate code
which can go into a shared library. The <span class="samp">-mno-shared</span> option
tells gas to generate code which uses the calling convention, but can
not go into a shared library. The resulting code is slightly more
efficient. This option only affects the handling of the
<span class="samp">.cpload</span> and <span class="samp">.cpsetup</span> pseudo-ops.
</dl>
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