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This file documents the GNU Assembler "as".
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Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
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<p>
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<a name="MIPS-Opts"></a>Next: <a rel="next" accesskey="n" href="MIPS-Object.html#MIPS-Object">MIPS Object</a>,
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Up: <a rel="up" accesskey="u" href="MIPS_002dDependent.html#MIPS_002dDependent">MIPS-Dependent</a>
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<hr><br>
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</div>
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<h4 class="subsection">9.22.1 Assembler options</h4>
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<p>The <span class="sc">mips</span> configurations of <span class="sc">gnu</span> <code>as</code> support these
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special options:
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<a name="index-_0040code_007b_002dG_007d-option-_0028MIPS_0029-1194"></a>
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<dl><dt><code>-G </code><var>num</var><dd>This option sets the largest size of an object that can be referenced
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implicitly with the <code>gp</code> register. It is only accepted for targets
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that use <span class="sc">ecoff</span> format. The default value is 8.
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<p><a name="index-_0040code_007b_002dEB_007d-option-_0028MIPS_0029-1195"></a><a name="index-_0040code_007b_002dEL_007d-option-_0028MIPS_0029-1196"></a><a name="index-MIPS-big_002dendian-output-1197"></a><a name="index-MIPS-little_002dendian-output-1198"></a><a name="index-big_002dendian-output_002c-MIPS-1199"></a><a name="index-little_002dendian-output_002c-MIPS-1200"></a><br><dt><code>-EB</code><dt><code>-EL</code><dd>Any <span class="sc">mips</span> configuration of <code>as</code> can select big-endian or
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little-endian output at run time (unlike the other <span class="sc">gnu</span> development
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tools, which must be configured for one or the other). Use <span class="samp">-EB</span>
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to select big-endian output, and <span class="samp">-EL</span> for little-endian.
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<br><dt><code>-KPIC</code><dd><a name="index-PIC-selection_002c-MIPS-1201"></a><a name="index-_0040option_007b_002dKPIC_007d-option_002c-MIPS-1202"></a>Generate SVR4-style PIC. This option tells the assembler to generate
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SVR4-style position-independent macro expansions. It also tells the
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assembler to mark the output file as PIC.
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<br><dt><code>-mvxworks-pic</code><dd><a name="index-_0040option_007b_002dmvxworks_002dpic_007d-option_002c-MIPS-1203"></a>Generate VxWorks PIC. This option tells the assembler to generate
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VxWorks-style position-independent macro expansions.
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<p><a name="index-MIPS-architecture-options-1204"></a><br><dt><code>-mips1</code><dt><code>-mips2</code><dt><code>-mips3</code><dt><code>-mips4</code><dt><code>-mips5</code><dt><code>-mips32</code><dt><code>-mips32r2</code><dt><code>-mips64</code><dt><code>-mips64r2</code><dd>Generate code for a particular MIPS Instruction Set Architecture level.
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<span class="samp">-mips1</span> corresponds to the <span class="sc">r2000</span> and <span class="sc">r3000</span> processors,
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<span class="samp">-mips2</span> to the <span class="sc">r6000</span> processor, <span class="samp">-mips3</span> to the
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<span class="sc">r4000</span> processor, and <span class="samp">-mips4</span> to the <span class="sc">r8000</span> and
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<span class="sc">r10000</span> processors. <span class="samp">-mips5</span>, <span class="samp">-mips32</span>, <span class="samp">-mips32r2</span>,
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<span class="samp">-mips64</span>, and <span class="samp">-mips64r2</span>
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correspond to generic
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<span class="sc">MIPS V</span>, <span class="sc">MIPS32</span>, <span class="sc">MIPS32 Release 2</span>, <span class="sc">MIPS64</span>,
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and <span class="sc">MIPS64 Release 2</span>
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ISA processors, respectively. You can also switch
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instruction sets during the assembly; see <a href="MIPS-ISA.html#MIPS-ISA">Directives to override the ISA level</a>.
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<br><dt><code>-mgp32</code><dt><code>-mfp32</code><dd>Some macros have different expansions for 32-bit and 64-bit registers.
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The register sizes are normally inferred from the ISA and ABI, but these
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flags force a certain group of registers to be treated as 32 bits wide at
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all times. <span class="samp">-mgp32</span> controls the size of general-purpose registers
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and <span class="samp">-mfp32</span> controls the size of floating-point registers.
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<p>The <code>.set gp=32</code> and <code>.set fp=32</code> directives allow the size
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of registers to be changed for parts of an object. The default value is
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restored by <code>.set gp=default</code> and <code>.set fp=default</code>.
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<p>On some MIPS variants there is a 32-bit mode flag; when this flag is
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set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
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save the 32-bit registers on a context switch, so it is essential never
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to use the 64-bit registers.
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<br><dt><code>-mgp64</code><dt><code>-mfp64</code><dd>Assume that 64-bit registers are available. This is provided in the
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interests of symmetry with <span class="samp">-mgp32</span> and <span class="samp">-mfp32</span>.
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<p>The <code>.set gp=64</code> and <code>.set fp=64</code> directives allow the size
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of registers to be changed for parts of an object. The default value is
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restored by <code>.set gp=default</code> and <code>.set fp=default</code>.
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<br><dt><code>-mips16</code><dt><code>-no-mips16</code><dd>Generate code for the MIPS 16 processor. This is equivalent to putting
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<code>.set mips16</code> at the start of the assembly file. <span class="samp">-no-mips16</span>
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turns off this option.
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<br><dt><code>-msmartmips</code><dt><code>-mno-smartmips</code><dd>Enables the SmartMIPS extensions to the MIPS32 instruction set, which
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provides a number of new instructions which target smartcard and
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cryptographic applications. This is equivalent to putting
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<code>.set smartmips</code> at the start of the assembly file.
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<span class="samp">-mno-smartmips</span> turns off this option.
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<br><dt><code>-mips3d</code><dt><code>-no-mips3d</code><dd>Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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<span class="samp">-no-mips3d</span> turns off this option.
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<br><dt><code>-mdmx</code><dt><code>-no-mdmx</code><dd>Generate code for the MDMX Application Specific Extension.
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This tells the assembler to accept MDMX instructions.
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<span class="samp">-no-mdmx</span> turns off this option.
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<br><dt><code>-mdsp</code><dt><code>-mno-dsp</code><dd>Generate code for the DSP Release 1 Application Specific Extension.
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This tells the assembler to accept DSP Release 1 instructions.
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<span class="samp">-mno-dsp</span> turns off this option.
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<br><dt><code>-mdspr2</code><dt><code>-mno-dspr2</code><dd>Generate code for the DSP Release 2 Application Specific Extension.
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This option implies -mdsp.
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This tells the assembler to accept DSP Release 2 instructions.
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<span class="samp">-mno-dspr2</span> turns off this option.
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<br><dt><code>-mmt</code><dt><code>-mno-mt</code><dd>Generate code for the MT Application Specific Extension.
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This tells the assembler to accept MT instructions.
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<span class="samp">-mno-mt</span> turns off this option.
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<br><dt><code>-mfix7000</code><dt><code>-mno-fix7000</code><dd>Cause nops to be inserted if the read of the destination register
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of an mfhi or mflo instruction occurs in the following two instructions.
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<br><dt><code>-mfix-vr4120</code><dt><code>-no-mfix-vr4120</code><dd>Insert nops to work around certain VR4120 errata. This option is
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intended to be used on GCC-generated code: it is not designed to catch
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all problems in hand-written assembler code.
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<br><dt><code>-mfix-vr4130</code><dt><code>-no-mfix-vr4130</code><dd>Insert nops to work around the VR4130 <span class="samp">mflo</span>/<span class="samp">mfhi</span> errata.
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<br><dt><code>-m4010</code><dt><code>-no-m4010</code><dd>Generate code for the LSI <span class="sc">r4010</span> chip. This tells the assembler to
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accept the <span class="sc">r4010</span> specific instructions (<span class="samp">addciu</span>, <span class="samp">ffc</span>,
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etc.), and to not schedule <span class="samp">nop</span> instructions around accesses to
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the <span class="samp">HI</span> and <span class="samp">LO</span> registers. <span class="samp">-no-m4010</span> turns off this
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option.
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<br><dt><code>-m4650</code><dt><code>-no-m4650</code><dd>Generate code for the MIPS <span class="sc">r4650</span> chip. This tells the assembler to accept
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the <span class="samp">mad</span> and <span class="samp">madu</span> instruction, and to not schedule <span class="samp">nop</span>
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instructions around accesses to the <span class="samp">HI</span> and <span class="samp">LO</span> registers.
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<span class="samp">-no-m4650</span> turns off this option.
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<dt><code>-m3900</code><dt><code>-no-m3900</code><dt><code>-m4100</code><dt><code>-no-m4100</code><dd>For each option <span class="samp">-m</span><var>nnnn</var>, generate code for the MIPS
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<span class="sc">r</span><var>nnnn</var> chip. This tells the assembler to accept instructions
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specific to that chip, and to schedule for that chip's hazards.
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<br><dt><code>-march=</code><var>cpu</var><dd>Generate code for a particular MIPS cpu. It is exactly equivalent to
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<span class="samp">-m</span><var>cpu</var>, except that there are more value of <var>cpu</var>
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understood. Valid <var>cpu</var> value are:
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<blockquote>
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2000,
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3000,
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3900,
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4000,
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4010,
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4100,
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4111,
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vr4120,
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vr4130,
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vr4181,
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4300,
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4400,
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4600,
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4650,
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5000,
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rm5200,
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rm5230,
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rm5231,
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rm5261,
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rm5721,
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vr5400,
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vr5500,
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6000,
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rm7000,
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8000,
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rm9000,
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10000,
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12000,
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4kc,
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4km,
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4kp,
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4ksc,
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4kec,
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4kem,
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4kep,
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4ksd,
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m4k,
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m4kp,
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24kc,
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24kf2_1,
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24kf,
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24kf1_1,
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24kec,
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24kef2_1,
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24kef,
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24kef1_1,
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34kc,
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34kf2_1,
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34kf,
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34kf1_1,
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74kc,
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74kf2_1,
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74kf,
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74kf1_1,
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74kf3_2,
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5kc,
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5kf,
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20kc,
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25kf,
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sb1,
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sb1a,
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loongson2e,
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loongson2f,
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octeon
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</blockquote>
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<p>For compatibility reasons, <var>n</var><span class="samp">x</span> and <var>b</var><span class="samp">fx</span> are
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accepted as synonyms for <var>n</var><span class="samp">f1_1</span>. These values are
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deprecated.
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<br><dt><code>-mtune=</code><var>cpu</var><dd>Schedule and tune for a particular MIPS cpu. Valid <var>cpu</var> values are
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identical to <span class="samp">-march=</span><var>cpu</var>.
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<br><dt><code>-mabi=</code><var>abi</var><dd>Record which ABI the source code uses. The recognized arguments
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are: <span class="samp">32</span>, <span class="samp">n32</span>, <span class="samp">o64</span>, <span class="samp">64</span> and <span class="samp">eabi</span>.
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<br><dt><code>-msym32</code><dt><code>-mno-sym32</code><dd><a name="index-_002dmsym32-1205"></a><a name="index-_002dmno_002dsym32-1206"></a>Equivalent to adding <code>.set sym32</code> or <code>.set nosym32</code> to
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the beginning of the assembler input. See <a href="MIPS-symbol-sizes.html#MIPS-symbol-sizes">MIPS symbol sizes</a>.
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<p><a name="index-_0040code_007b_002dnocpp_007d-ignored-_0028MIPS_0029-1207"></a><br><dt><code>-nocpp</code><dd>This option is ignored. It is accepted for command-line compatibility with
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other assemblers, which use it to turn off C style preprocessing. With
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<span class="sc">gnu</span> <code>as</code>, there is no need for <span class="samp">-nocpp</span>, because the
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<span class="sc">gnu</span> assembler itself never runs the C preprocessor.
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<br><dt><code>-msoft-float</code><dt><code>-mhard-float</code><dd>Disable or enable floating-point instructions. Note that by default
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floating-point instructions are always allowed even with CPU targets
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that don't have support for these instructions.
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<br><dt><code>-msingle-float</code><dt><code>-mdouble-float</code><dd>Disable or enable double-precision floating-point operations. Note
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that by default double-precision floating-point operations are always
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allowed even with CPU targets that don't have support for these
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operations.
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<br><dt><code>--construct-floats</code><dt><code>--no-construct-floats</code><dd>The <code>--no-construct-floats</code> option disables the construction of
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double width floating point constants by loading the two halves of the
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value into the two single width floating point registers that make up
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the double width register. This feature is useful if the processor
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support the FR bit in its status register, and this bit is known (by
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the programmer) to be set. This bit prevents the aliasing of the double
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width register by the single width registers.
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<p>By default <code>--construct-floats</code> is selected, allowing construction
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of these floating point constants.
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<br><dt><code>--trap</code><dt><code>--no-break</code><dd><!-- FIXME! (1) reflect these options (next item too) in option summaries; -->
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<!-- (2) stop teasing, say _which_ instructions expanded _how_. -->
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<code>as</code> automatically macro expands certain division and
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multiplication instructions to check for overflow and division by zero. This
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option causes <code>as</code> to generate code to take a trap exception
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rather than a break exception when an error is detected. The trap instructions
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are only supported at Instruction Set Architecture level 2 and higher.
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<br><dt><code>--break</code><dt><code>--no-trap</code><dd>Generate code to take a break exception rather than a trap exception when an
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error is detected. This is the default.
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<br><dt><code>-mpdr</code><dt><code>-mno-pdr</code><dd>Control generation of <code>.pdr</code> sections. Off by default on IRIX, on
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elsewhere.
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<br><dt><code>-mshared</code><dt><code>-mno-shared</code><dd>When generating code using the Unix calling conventions (selected by
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<span class="samp">-KPIC</span> or <span class="samp">-mcall_shared</span>), gas will normally generate code
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which can go into a shared library. The <span class="samp">-mno-shared</span> option
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tells gas to generate code which uses the calling convention, but can
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not go into a shared library. The resulting code is slightly more
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efficient. This option only affects the handling of the
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<span class="samp">.cpload</span> and <span class="samp">.cpsetup</span> pseudo-ops.
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</dl>
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</body></html>
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