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59 lines
1.9 KiB
C
59 lines
1.9 KiB
C
//-----------------------------------------------------------------------------
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//AVR Mega168 SPI HAL
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#define BIT0 0x01
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#define BIT1 0x02
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#define BIT2 0x04
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#define BIT3 0x08
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#define BIT4 0x10
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#define BIT5 0x20
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#define BIT6 0x40
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#define BIT7 0x80
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#define SPI0_SS_BIT BIT2
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#define SPI0_SS_DDR DDRB
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#define SPI0_SS_PORT PORTB
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#define SPI0_SCLK_BIT BIT5
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#define SPI0_SCLK_DDR DDRB
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#define SPI0_SCLK_PORT PORTB
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#define SPI0_MOSI_BIT BIT3
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#define SPI0_MOSI_DDR DDRB
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#define SPI0_MOSI_PORT PORTB
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#define SPI0_MISO_BIT BIT4
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#define SPI0_MISO_DDR DDRB
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#define SPI0_MISO_PORT PORTB
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#define SPI0_WaitForReceive()
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#define SPI0_RxData() (SPDR)
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#define SPI0_TxData(Data) (SPDR = Data)
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#define SPI0_WaitForSend() while( (SPSR & 0x80)==0x00 )
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#define SPI0_SendByte(Data) SPI0_TxData(Data);SPI0_WaitForSend()
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#define SPI0_RecvBute() SPI0_RxData()
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// PB4(MISO), PB3(MOSI), PB5(SCK), PB2(/SS) // CS=1, waiting for SPI start // SPI mode 0, 4MHz
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#define SPI0_Init() DDRB |= SPI0_SS_BIT|SPI0_SCLK_BIT|SPI0_MOSI_BIT;\
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PORTB |= SPI0_SS_BIT; PORTB &= ~(SPI0_SCLK_BIT|SPI0_MOSI_BIT);\
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SPCR = 0x50
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//IInChip SPI HAL
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#define IINCHIP_SpiInit SPI0_Init
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#define IINCHIP_SpiSendData SPI0_SendByte
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#define IINCHIP_SpiRecvData SPI0_RxData
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#define IINCHIP_CS_BIT BIT2
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#define IINCHIP_CS_DDR DDRB
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#define IINCHIP_CS_PORT PORTB
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#define IINCHIP_CSInit() (IINCHIP_CS_DDR |= IINCHIP_CS_BIT)
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#define IINCHIP_CSon() (IINCHIP_CS_PORT |= IINCHIP_CS_BIT)
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#define IINCHIP_CSoff() (IINCHIP_CS_PORT &= ~IINCHIP_CS_BIT)
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//-----------------------------------------------------------------------------
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