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Index: gcc/config/avr/predicates.md
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===================================================================
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--- gcc/config/avr/predicates.md (revision 134489)
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+++ gcc/config/avr/predicates.md (working copy)
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@@ -27,6 +27,11 @@
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(and (match_code "reg")
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(match_test "REGNO (op) >= 16 && REGNO (op) <= 31")))
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+;; Registers from r16 to 24.
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+(define_predicate "a_register_operand"
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+ (and (match_code "reg")
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+ (match_test "REGNO (op) >= 16 && REGNO (op) <= 24")))
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+
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(define_predicate "even_register_operand"
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(and (match_code "reg")
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(and (match_test "REGNO (op) <= 31")
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--- gcc/config/avr/avr.md.orig 2008-12-02 12:44:25.418762100 -0700
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+++ gcc/config/avr/avr.md 2008-12-02 15:31:40.788948300 -0700
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@@ -49,12 +49,26 @@
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(UNSPEC_STRLEN 0)
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(UNSPEC_INDEX_JMP 1)
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- (UNSPEC_SEI 2)
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- (UNSPEC_CLI 3)
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- (UNSPEC_SWAP 4)
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-
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+ (UNSPEC_SWAP 2)
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+ (UNSPEC_FMUL 3)
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+ (UNSPEC_FMULS 4)
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+ (UNSPEC_FMULSU 5)
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+
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(UNSPECV_PROLOGUE_SAVES 0)
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- (UNSPECV_EPILOGUE_RESTORES 1)])
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+ (UNSPECV_EPILOGUE_RESTORES 1)
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+ (UNSPECV_SEI 2)
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+ (UNSPECV_CLI 3)
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+ (UNSPECV_NOP 4)
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+ (UNSPECV_NOP2 5)
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+ (UNSPECV_SLEEP 6)
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+ (UNSPECV_WDR 7)
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+
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+ (UNSPECV_DELAY_CYCLES 100)
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+ (UNSPECV_DELAY_CYCLES_1 101)
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+ (UNSPECV_DELAY_CYCLES_2 102)
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+ (UNSPECV_DELAY_CYCLES_3 103)
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+ (UNSPECV_DELAY_CYCLES_4 104)])
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+
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(include "predicates.md")
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(include "constraints.md")
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@@ -2537,13 +2551,6 @@
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(const_int 1))
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(const_int 3)])])
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-(define_insn "nop"
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- [(const_int 0)]
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- ""
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- "nop"
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- [(set_attr "cc" "none")
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- (set_attr "length" "1")])
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-
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; indirect jump
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(define_insn "indirect_jump"
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[(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
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@@ -2923,7 +2930,7 @@
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;; Enable Interrupts
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(define_insn "enable_interrupt"
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- [(unspec [(const_int 0)] UNSPEC_SEI)]
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+ [(unspec_volatile [(const_int 0)] UNSPECV_SEI)]
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""
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"sei"
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[(set_attr "length" "1")
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@@ -2932,7 +2939,7 @@
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;; Disable Interrupts
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(define_insn "disable_interrupt"
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- [(unspec [(const_int 0)] UNSPEC_CLI)]
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+ [(unspec_volatile [(const_int 0)] UNSPECV_CLI)]
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""
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"cli"
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[(set_attr "length" "1")
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@@ -3032,3 +3039,219 @@
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expand_epilogue ();
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DONE;
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}")
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+
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+;;delay_cycles_delay_cycles_delay_cycles_delay_cycles_delay_cycles_delay
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+;; delay_cycles
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+
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+(define_expand "delay_cycles"
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+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")]
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+ UNSPECV_DELAY_CYCLES)]
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+ ""
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+ "
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+ rtx loop_reg;
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+ unsigned int cycles = INTVAL (operands[0]);
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+ if (IN_RANGE(cycles, 83886082, 0xFFFFFFFF))
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+ {
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+ unsigned int loop_count = ((cycles - 9) / 6) + 1;
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+ unsigned int cycles_used = (((loop_count - 1) * 6) + 9);
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+ emit_insn (gen_delay_cycles_4 (gen_int_mode (loop_count, SImode)));
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+ cycles -= cycles_used;
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+ }
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+ if (IN_RANGE(cycles, 262145, 83886081))
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+ {
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+ unsigned int loop_count = ((cycles - 7) / 5) + 1;
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+ if (loop_count > 0xFFFFFF)
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+ loop_count = 0xFFFFFF;
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+ unsigned int cycles_used = (((loop_count - 1) * 5) + 7);
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+ emit_insn (gen_delay_cycles_3 (gen_int_mode (loop_count, SImode)));
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+ cycles -= cycles_used;
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+ }
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+ if (IN_RANGE(cycles, 768, 262144))
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+ {
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+ unsigned int loop_count = ((cycles - 5) / 4) + 1;
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+ if (loop_count > 0xFFFF)
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+ loop_count = 0xFFFF;
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+ unsigned int cycles_used = (((loop_count - 1) * 4) + 5);
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+ emit_insn (gen_delay_cycles_2 (gen_int_mode (loop_count, HImode)));
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+ cycles -= cycles_used;
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+ }
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+ if (IN_RANGE(cycles, 6, 767))
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+ {
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+ unsigned int loop_count = (cycles/ 3);
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+ if (loop_count > 255)
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+ loop_count = 255;
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+ unsigned int cycles_used = (loop_count * 3);
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+ emit_insn (gen_delay_cycles_1 (gen_int_mode (loop_count, QImode)));
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+ cycles -= cycles_used;
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+ }
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+ while (cycles >= 2)
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+ {
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+ emit_insn (gen_nop2 ());
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+ cycles -= 2;
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+ }
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+ if (cycles == 1)
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+ {
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+ emit_insn (gen_nop ());
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+ cycles--;
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+ }
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+ DONE;
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+ ")
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+
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+(define_insn "delay_cycles_1"
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+[(unspec_volatile [(const_int 0)] UNSPECV_DELAY_CYCLES_1)
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+ (match_operand:QI 0 "immediate_operand" "")
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+ (clobber (match_scratch:QI 1 "=&d"))]
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+ ""
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+ " ldi %1,lo8(%0)
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+ 1:dec %1
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+ brne 1b"
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+ [(set_attr "length" "3")
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+ (set_attr "cc" "clobber")])
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+
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+(define_insn "delay_cycles_2"
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+ [(unspec_volatile [(const_int 0)] UNSPECV_DELAY_CYCLES_2)
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+ (match_operand:HI 0 "immediate_operand" "")
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+ (clobber (match_scratch:HI 1 "=&w"))]
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+ ""
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+ " ldi %A1,lo8(%0)
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+ ldi %B1,hi8(%0)
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+ 1:sbiw %A1,1
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+ brne 1b"
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+ [(set_attr "length" "4")
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+ (set_attr "cc" "clobber")])
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+
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+(define_insn "delay_cycles_3"
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+ [(unspec_volatile [(const_int 0)] UNSPECV_DELAY_CYCLES_3)
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+ (match_operand:SI 0 "immediate_operand" "")
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+ (clobber (match_scratch:SI 1 "=&d"))]
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+ ""
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+ " ldi %A1,lo8(%0)
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+ ldi %B1,hi8(%0)
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+ ldi %C1,hlo8(%0)
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+ 1:subi %A1,1
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+ sbci %B1,0
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+ sbci %C1,0
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+ brne 1b"
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+ [(set_attr "length" "7")
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+ (set_attr "cc" "clobber")])
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+
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+(define_insn "delay_cycles_4"
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+ [(unspec_volatile [(const_int 0)] UNSPECV_DELAY_CYCLES_4)
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+ (match_operand:SI 0 "immediate_operand" "")
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+ (clobber (match_scratch:SI 1 "=&d"))]
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+ ""
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+ " ldi %A1,lo8(%0)
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+ ldi %B1,hi8(%0)
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+ ldi %C1,hlo8(%0)
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+ ldi %D1,hhi8(%0)
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+ 1:subi %A1,1
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+ sbci %B1,0
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+ sbci %C1,0
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+ sbci %D1,0
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+ brne 1b"
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+ [(set_attr "length" "9")
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+ (set_attr "cc" "clobber")])
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+
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+;; CPU instructions
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+
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+;; NOP
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+(define_insn "nop"
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+ [(unspec_volatile [(const_int 0)] UNSPECV_NOP)]
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+ ""
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+ "nop"
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+ [(set_attr "length" "1")
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+ (set_attr "cc" "none")])
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+
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+;; NOP2
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+(define_insn "nop2"
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+ [(unspec_volatile [(const_int 0)] UNSPECV_NOP2)]
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+ ""
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+ "rjmp ."
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+ [(set_attr "length" "1")
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+ (set_attr "cc" "none")])
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+
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+;; SEI, Enable Interrupts
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+;(define_insn "sei"
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+; [(unspec_volatile [(const_int 0)] UNSPECV_SEI)]
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+; ""
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+; "sei"
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+; [(set_attr "length" "1")
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+; (set_attr "cc" "none")
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+; ])
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+
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+;; CLI, Disable Interrupts
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+;(define_insn "cli"
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+; [(unspec_volatile [(const_int 0)] UNSPECV_CLI)]
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+; ""
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+; "cli"
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+; [(set_attr "length" "1")
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+; (set_attr "cc" "none")
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+; ])
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+
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+;; SLEEP
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+(define_insn "sleep"
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+ [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)]
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+ ""
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+ "sleep"
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+ [(set_attr "length" "1")
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+ (set_attr "cc" "none")
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+ ])
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+
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+;; WDR
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+(define_insn "wdr"
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+ [(unspec_volatile [(const_int 0)] UNSPECV_WDR)]
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+ ""
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+ "wdr"
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+ [(set_attr "length" "1")
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+ (set_attr "cc" "none")
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+ ])
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+
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+;; SWAP
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+(define_insn "swap"
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+ [(set (match_operand:QI 0 "register_operand" "=r")
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+ (unspec:QI [(match_operand:QI 1 "register_operand" "0")]
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+ UNSPEC_SWAP))]
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+ ""
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+ "swap %0"
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+ [(set_attr "length" "1")
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+ (set_attr "cc" "none")])
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+
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+;; FMUL
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+(define_insn "fmul"
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+ [(set (match_operand:HI 0 "a_register_operand" "=r")
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+ (unspec:HI [(match_operand:QI 1 "a_register_operand" "r")
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+ (match_operand:QI 2 "a_register_operand" "r")]
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+ UNSPEC_FMUL))]
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+ "AVR_HAVE_MUL"
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+ "fmul %1,%2
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+ movw %0,r0
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+ clr r1"
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+ [(set_attr "length" "3")
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+ (set_attr "cc" "clobber")])
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+
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+;; FMULS
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+(define_insn "fmuls"
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+ [(set (match_operand:HI 0 "a_register_operand" "=r")
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+ (unspec:HI [(match_operand:QI 1 "a_register_operand" "r")
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+ (match_operand:QI 2 "a_register_operand" "r")]
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+ UNSPEC_FMULS))]
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+ "AVR_HAVE_MUL"
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+ "fmuls %1,%2
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+ movw %0,r0
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+ clr r1"
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+ [(set_attr "length" "3")
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+ (set_attr "cc" "clobber")])
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+
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+;; FMULSU
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+(define_insn "fmulsu"
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+ [(set (match_operand:HI 0 "a_register_operand" "=r")
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+ (unspec:HI [(match_operand:QI 1 "a_register_operand" "r")
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+ (match_operand:QI 2 "a_register_operand" "r")]
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+ UNSPEC_FMULSU))]
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+ "AVR_HAVE_MUL"
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+ "fmulsu %1,%2
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+ movw %0,r0
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+ clr r1"
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+ [(set_attr "length" "3")
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+ (set_attr "cc" "clobber")])
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+
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--- gcc/config/avr/avr.c.orig 2008-12-01 10:51:45.062273700 -0700
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+++ gcc/config/avr/avr.c 2008-12-01 11:18:33.980387900 -0700
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@@ -30,6 +30,7 @@
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-attr.h"
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+#include "insn-codes.h"
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#include "flags.h"
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#include "reload.h"
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#include "tree.h"
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@@ -39,7 +40,9 @@
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#include "obstack.h"
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#include "function.h"
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#include "recog.h"
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+#include "optabs.h"
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#include "ggc.h"
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+#include "langhooks.h"
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#include "tm_p.h"
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#include "target.h"
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#include "target-def.h"
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@@ -83,6 +86,9 @@ static bool avr_rtx_costs (rtx, int, int
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static int avr_address_cost (rtx);
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static bool avr_return_in_memory (const_tree, const_tree);
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static struct machine_function * avr_init_machine_status (void);
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+static void avr_init_builtins (void);
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+static rtx avr_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
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+
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/* Allocate registers from r25 to r8 for parameters for function calls. */
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#define FIRST_CUM_REG 26
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@@ -373,6 +379,12 @@ int avr_case_values_threshold = 30000;
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#undef TARGET_STRICT_ARGUMENT_NAMING
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#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
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|
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+#undef TARGET_INIT_BUILTINS
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+#define TARGET_INIT_BUILTINS avr_init_builtins
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+
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+#undef TARGET_EXPAND_BUILTIN
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+#define TARGET_EXPAND_BUILTIN avr_expand_builtin
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+
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struct gcc_target targetm = TARGET_INITIALIZER;
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|
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|
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void
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@@ -6258,4 +6270,237 @@ avr_return_in_memory (const_tree type, c
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return false;
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}
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|
|
|
|
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+/* Codes for all the AVR builtins. */
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+
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+enum avr_builtins
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+{
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+ AVR_BUILTIN_SEI,
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+ AVR_BUILTIN_CLI,
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+ AVR_BUILTIN_WDR,
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+ AVR_BUILTIN_SLEEP,
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+ AVR_BUILTIN_SWAP,
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+ AVR_BUILTIN_FMUL,
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+ AVR_BUILTIN_FMULS,
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+ AVR_BUILTIN_FMULSU,
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+ AVR_BUILTIN_DELAY_CYCLES
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+};
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+
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|
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+#define def_builtin(NAME, TYPE, CODE) \
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+do { \
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+ add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
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+ NULL, NULL_TREE); \
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+} while (0)
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+
|
|
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+/* Set up all builtin functions for this target. */
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+
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+static void
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+avr_init_builtins (void)
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+{
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|
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+ tree void_ftype_void
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|
|
+ = build_function_type (void_type_node, void_list_node);
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|
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+ tree uchar_ftype_uchar
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|
|
+ = build_function_type_list (unsigned_char_type_node,
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|
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+ unsigned_char_type_node,
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|
|
+ NULL_TREE);
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|
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+ tree uint_ftype_uchar_uchar
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|
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+ = build_function_type_list (unsigned_type_node,
|
|
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+ unsigned_char_type_node,
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|
|
+ unsigned_char_type_node,
|
|
|
+ NULL_TREE);
|
|
|
+ tree int_ftype_char_char
|
|
|
+ = build_function_type_list (integer_type_node,
|
|
|
+ char_type_node,
|
|
|
+ char_type_node,
|
|
|
+ NULL_TREE);
|
|
|
+ tree int_ftype_char_uchar
|
|
|
+ = build_function_type_list (integer_type_node,
|
|
|
+ char_type_node,
|
|
|
+ unsigned_char_type_node,
|
|
|
+ NULL_TREE);
|
|
|
+ tree void_ftype_ulong
|
|
|
+ = build_function_type_list (void_type_node,
|
|
|
+ long_unsigned_type_node,
|
|
|
+ NULL_TREE);
|
|
|
+
|
|
|
+ def_builtin ("__builtin_avr_sei", void_ftype_void, AVR_BUILTIN_SEI);
|
|
|
+ def_builtin ("__builtin_avr_cli", void_ftype_void, AVR_BUILTIN_CLI);
|
|
|
+ def_builtin ("__builtin_avr_wdr", void_ftype_void, AVR_BUILTIN_WDR);
|
|
|
+ def_builtin ("__builtin_avr_sleep", void_ftype_void, AVR_BUILTIN_SLEEP);
|
|
|
+
|
|
|
+ if (AVR_HAVE_MUL)
|
|
|
+ {
|
|
|
+ def_builtin ("__builtin_avr_fmul", uint_ftype_uchar_uchar,
|
|
|
+ AVR_BUILTIN_FMUL);
|
|
|
+ def_builtin ("__builtin_avr_fmuls", int_ftype_char_char,
|
|
|
+ AVR_BUILTIN_FMULS);
|
|
|
+ def_builtin ("__builtin_avr_fmulsu", int_ftype_char_uchar,
|
|
|
+ AVR_BUILTIN_FMULSU);
|
|
|
+ }
|
|
|
+
|
|
|
+ def_builtin ("__builtin_avr_swap", uchar_ftype_uchar, AVR_BUILTIN_SWAP);
|
|
|
+ def_builtin ("__builtin_avr_delay_cycles", void_ftype_ulong,
|
|
|
+ AVR_BUILTIN_DELAY_CYCLES);
|
|
|
+}
|
|
|
+
|
|
|
+struct builtin_description
|
|
|
+{
|
|
|
+ const enum insn_code icode;
|
|
|
+ const char *const name;
|
|
|
+ const enum avr_builtins code;
|
|
|
+};
|
|
|
+
|
|
|
+static const struct builtin_description bdesc_1arg[] =
|
|
|
+{
|
|
|
+ { CODE_FOR_swap, "__builtin_avr_swap", AVR_BUILTIN_SWAP }
|
|
|
+};
|
|
|
+
|
|
|
+static const struct builtin_description bdesc_2arg[] =
|
|
|
+{
|
|
|
+ { CODE_FOR_fmul, "__builtin_avr_fmul", AVR_BUILTIN_FMUL },
|
|
|
+ { CODE_FOR_fmuls, "__builtin_avr_fmuls", AVR_BUILTIN_FMULS },
|
|
|
+ { CODE_FOR_fmulsu, "__builtin_avr_fmulsu", AVR_BUILTIN_FMULSU }
|
|
|
+};
|
|
|
+
|
|
|
+/* Subroutine of avr_expand_builtin to take care of unop insns. */
|
|
|
+
|
|
|
+static rtx
|
|
|
+avr_expand_unop_builtin (enum insn_code icode, tree exp,
|
|
|
+ rtx target)
|
|
|
+{
|
|
|
+ rtx pat;
|
|
|
+ tree arg0 = CALL_EXPR_ARG (exp, 0);
|
|
|
+ rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
|
|
|
+ enum machine_mode op0mode = GET_MODE (op0);
|
|
|
+ enum machine_mode tmode = insn_data[icode].operand[0].mode;
|
|
|
+ enum machine_mode mode0 = insn_data[icode].operand[1].mode;
|
|
|
+
|
|
|
+ if (! target
|
|
|
+ || GET_MODE (target) != tmode
|
|
|
+ || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
|
|
|
+ target = gen_reg_rtx (tmode);
|
|
|
+
|
|
|
+ if (op0mode == SImode && mode0 == HImode)
|
|
|
+ {
|
|
|
+ op0mode = HImode;
|
|
|
+ op0 = gen_lowpart (HImode, op0);
|
|
|
+ }
|
|
|
+ gcc_assert (op0mode == mode0 || op0mode == VOIDmode);
|
|
|
+
|
|
|
+ if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
|
|
|
+ op0 = copy_to_mode_reg (mode0, op0);
|
|
|
+
|
|
|
+ pat = GEN_FCN (icode) (target, op0);
|
|
|
+ if (! pat)
|
|
|
+ return 0;
|
|
|
+ emit_insn (pat);
|
|
|
+ return target;
|
|
|
+}
|
|
|
+
|
|
|
+/* Subroutine of avr_expand_builtin to take care of binop insns. */
|
|
|
+
|
|
|
+static rtx
|
|
|
+avr_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
|
|
|
+{
|
|
|
+ rtx pat;
|
|
|
+ tree arg0 = CALL_EXPR_ARG (exp, 0);
|
|
|
+ tree arg1 = CALL_EXPR_ARG (exp, 1);
|
|
|
+ rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
|
|
|
+ rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
|
|
|
+ enum machine_mode op0mode = GET_MODE (op0);
|
|
|
+ enum machine_mode op1mode = GET_MODE (op1);
|
|
|
+ enum machine_mode tmode = insn_data[icode].operand[0].mode;
|
|
|
+ enum machine_mode mode0 = insn_data[icode].operand[1].mode;
|
|
|
+ enum machine_mode mode1 = insn_data[icode].operand[2].mode;
|
|
|
+
|
|
|
+ if (! target
|
|
|
+ || GET_MODE (target) != tmode
|
|
|
+ || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
|
|
|
+ target = gen_reg_rtx (tmode);
|
|
|
+
|
|
|
+ if ((op0mode == SImode || op0mode == VOIDmode) && mode0 == HImode)
|
|
|
+ {
|
|
|
+ op0mode = HImode;
|
|
|
+ op0 = gen_lowpart (HImode, op0);
|
|
|
+ }
|
|
|
+ if ((op1mode == SImode || op1mode == VOIDmode) && mode1 == HImode)
|
|
|
+ {
|
|
|
+ op1mode = HImode;
|
|
|
+ op1 = gen_lowpart (HImode, op1);
|
|
|
+ }
|
|
|
+ /* In case the insn wants input operands in modes different from
|
|
|
+ the result, abort. */
|
|
|
+ gcc_assert ((op0mode == mode0 || op0mode == VOIDmode)
|
|
|
+ && (op1mode == mode1 || op1mode == VOIDmode));
|
|
|
+
|
|
|
+ if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
|
|
|
+ op0 = copy_to_mode_reg (mode0, op0);
|
|
|
+ if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
|
|
|
+ op1 = copy_to_mode_reg (mode1, op1);
|
|
|
+
|
|
|
+ pat = GEN_FCN (icode) (target, op0, op1);
|
|
|
+ if (! pat)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ emit_insn (pat);
|
|
|
+ return target;
|
|
|
+}
|
|
|
+
|
|
|
+/* Expand an expression EXP that calls a built-in function,
|
|
|
+ with result going to TARGET if that's convenient
|
|
|
+ (and in mode MODE if that's convenient).
|
|
|
+ SUBTARGET may be used as the target for computing one of EXP's operands.
|
|
|
+ IGNORE is nonzero if the value is to be ignored. */
|
|
|
+
|
|
|
+static rtx
|
|
|
+avr_expand_builtin (tree exp, rtx target,
|
|
|
+ rtx subtarget ATTRIBUTE_UNUSED,
|
|
|
+ enum machine_mode mode ATTRIBUTE_UNUSED,
|
|
|
+ int ignore ATTRIBUTE_UNUSED)
|
|
|
+{
|
|
|
+ size_t i;
|
|
|
+ const struct builtin_description *d;
|
|
|
+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
|
|
|
+ unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
|
|
|
+ rtx pat;
|
|
|
+ tree arg0;
|
|
|
+ rtx op0;
|
|
|
+
|
|
|
+ switch (fcode)
|
|
|
+ {
|
|
|
+ case AVR_BUILTIN_SEI:
|
|
|
+ emit_insn (gen_enable_interrupt ());
|
|
|
+ return 0;
|
|
|
+ case AVR_BUILTIN_CLI:
|
|
|
+ emit_insn (gen_disable_interrupt ());
|
|
|
+ return 0;
|
|
|
+ case AVR_BUILTIN_WDR:
|
|
|
+ emit_insn (gen_wdr ());
|
|
|
+ return 0;
|
|
|
+ case AVR_BUILTIN_SLEEP:
|
|
|
+ emit_insn (gen_sleep ());
|
|
|
+ return 0;
|
|
|
+ case AVR_BUILTIN_DELAY_CYCLES:
|
|
|
+ {
|
|
|
+ arg0 = CALL_EXPR_ARG (exp, 0);
|
|
|
+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
|
|
|
+
|
|
|
+ if (!CONSTANT_P (op0))
|
|
|
+ error ("__builtin_avr_delay_cycles expects an integer constant.");
|
|
|
+
|
|
|
+ emit_insn (gen_delay_cycles (op0));
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
|
|
|
+ if (d->code == fcode)
|
|
|
+ return avr_expand_unop_builtin (d->icode, exp, target);
|
|
|
+
|
|
|
+ for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
|
|
|
+ if (d->code == fcode)
|
|
|
+ return avr_expand_binop_builtin (d->icode, exp, target);
|
|
|
+
|
|
|
+ gcc_unreachable ();
|
|
|
+}
|
|
|
+
|
|
|
#include "gt-avr.h"
|