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<title>ARM Opcodes - Using as</title>
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This file documents the GNU Assembler "as".
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Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
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2006, 2007 Free Software Foundation, Inc.
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<p>
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<a name="ARM-Opcodes"></a>Next: <a rel="next" accesskey="n" href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols">ARM Mapping Symbols</a>,
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Previous: <a rel="previous" accesskey="p" href="ARM-Directives.html#ARM-Directives">ARM Directives</a>,
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Up: <a rel="up" accesskey="u" href="ARM_002dDependent.html#ARM_002dDependent">ARM-Dependent</a>
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<h4 class="subsection">9.3.5 Opcodes</h4>
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<p><a name="index-ARM-opcodes-631"></a><a name="index-opcodes-for-ARM-632"></a><code>as</code> implements all the standard ARM opcodes. It also
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implements several pseudo opcodes, including several synthetic load
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instructions.
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<a name="index-_0040code_007bNOP_007d-pseudo-op_002c-ARM-633"></a>
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<dl><dt><code>NOP</code><dd>
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<pre class="smallexample"> nop
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</pre>
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<p>This pseudo op will always evaluate to a legal ARM instruction that does
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nothing. Currently it will evaluate to MOV r0, r0.
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<p><a name="index-_0040code_007bLDR-reg_002c_003d_003clabel_003e_007d-pseudo-op_002c-ARM-634"></a><br><dt><code>LDR</code><dd>
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<pre class="smallexample"> ldr <register> , = <expression>
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</pre>
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<p>If expression evaluates to a numeric constant then a MOV or MVN
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instruction will be used in place of the LDR instruction, if the
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constant can be generated by either of these instructions. Otherwise
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the constant will be placed into the nearest literal pool (if it not
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already there) and a PC relative LDR instruction will be generated.
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<p><a name="index-_0040code_007bADR-reg_002c_003clabel_003e_007d-pseudo-op_002c-ARM-635"></a><br><dt><code>ADR</code><dd>
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<pre class="smallexample"> adr <register> <label>
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</pre>
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<p>This instruction will load the address of <var>label</var> into the indicated
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register. The instruction will evaluate to a PC relative ADD or SUB
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instruction depending upon where the label is located. If the label is
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out of range, or if it is not defined in the same file (and section) as
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the ADR instruction, then an error will be generated. This instruction
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will not make use of the literal pool.
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<p><a name="index-_0040code_007bADRL-reg_002c_003clabel_003e_007d-pseudo-op_002c-ARM-636"></a><br><dt><code>ADRL</code><dd>
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<pre class="smallexample"> adrl <register> <label>
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</pre>
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<p>This instruction will load the address of <var>label</var> into the indicated
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register. The instruction will evaluate to one or two PC relative ADD
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or SUB instructions depending upon where the label is located. If a
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second instruction is not needed a NOP instruction will be generated in
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its place, so that this instruction is always 8 bytes long.
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<p>If the label is out of range, or if it is not defined in the same file
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(and section) as the ADRL instruction, then an error will be generated.
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This instruction will not make use of the literal pool.
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</dl>
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<p>For information on the ARM or Thumb instruction sets, see <cite>ARM
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Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines
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Ltd.
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